[alsa-devel] [PATCH] ASoC: fsl-asrc: Convert to use regmap framework's endianness method.

[Li.Xiubo at freescale.com]

>>  Documentation/devicetree/bindings/sound/fsl,asrc.txt | 10 +++++++---
>>  sound/soc/fsl/fsl_asrc.c                             |  6 +-----
>>  2 files changed, 8 insertions(+), 8 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/sound/fsl,asrc.txt b/Documentation/devicetree/bindings/sound/fsl,asrc.txt
>> index b93362a..791f372 100644
>> --- a/Documentation/devicetree/bindings/sound/fsl,asrc.txt
>> +++ b/Documentation/devicetree/bindings/sound/fsl,asrc.txt
>> @@ -26,9 +26,12 @@ Required properties:
>>       "ipg"             Peripheral clock to driver module.
>>       "asrck_<0-f>"     Clock sources for input and output clock.
>>
>> -   - big-endian              : If this property is absent, the little endian mode
>>-                       will be in use as default. Otherwise, the big endian
>> -                       mode will be in use for all the device registers.
>> +   - big-endian              : If this property is absent, the native endian mode
>> +                       (same with CPU) will be in use as default. Otherwise,
>> +                       the big endian mode will be in use for all the device
>> +                       registers.
>> +                       See Documentation/devicetree/bindings/regmap/regmap.txt
>> +                       for more detail.
>
>Why does this have to change the semantics of the DT binding?
>

I'm thinking that maybe in the late fulture, this device will be applied to some PowerPC SoC, 
from the regmap framework code, we can see that the 'big-endian' property could be ignored.

So,in this case,  if it is absent, the default endian mode should be used as defualt or native as 
the regmap framework said.

Thanks,

BRs
Xiubo



>
>
>Mark.
>
>>
>>     - fsl,asrc-rate   : Defines a mutual sample rate used by DPCM Back Ends.
>>