[alsa-devel] am335x: mcasp in DIT mode

[Yegor Yefremov]

On Mon, Mar 4, 2013 at 12:25 PM, Bedia, Vaibhav <vaibhav.bedia at ti.com> wrote:
> On Mon, Mar 04, 2013 at 15:56:47, Yegor Yefremov wrote:
> [...]
>>
>> I found this passage in 22.3.8.3.2 of the "AM335x ARM® Cortex™-A8
>> Microprocessors (MPUs) Technical Reference Manual" Literature Number:
>> SPRUH73G
>>
>> The DIT transmitter only works in the following configuration:
>> • In transmit frame control register (AFSXCTL):
>> – Internally-generated transmit frame sync, FSXM = 1.
>> – Rising-edge frame sync, FSXP = 0.
>> – Bit-width frame sync, FXWID = 0.
>> – 384-slot TDM, XMOD = 1 1000 0000b.
>> • In transmit clock control register (ACLKXCTL), ASYNC = 1.
>> • In transmit bitstream format register (XFMT), XSSZ = 1111 (32-bit slot size).
>>
>> So slot size does matter for DIT mode. On the same page you have frame
>> format description. It says that two following rotation settings are
>> valid for DIT XROT = 010 and XROT = 000, but the only one working with
>> right-aligned data is 0x6 i.e. 24-bit rotation. This value was used in
>> the davinci-mcasp.c driver source.
>>
>
> Ok. Since you seem to have a h/w handy, if you have time to spare, could you
> please try out a config which sets the slot size to 16 instead of 32 and let
> us know whether it works? Depending on the test result we'll know for sure
> whether the original code ever worked.

I've made test with XSSZ == 0x7 (16-bit) and I heard sound. So the
initial version could be functional, because only XSSZ was touched.
Later came settings for mask and rotation. It seems like rotation is
the most important setting for DIT. So the Technical Reference Manual
should be thoroughly revised:

1. XSSZ 32-bit is not mandatory
2. rotation for right-aligned data must properly specified (0x6 -
24-bit and not 0x0)

Yegor