[alsa-devel] [PATCH v3 1/3] ASoC: codecs: adau1701: allow configuration of PLL mode pins

[Mark Brown]

On Fri, Jun 21, 2013 at 09:54:42AM +0200, Daniel Mack wrote:

> To avoid excessive reset cycles and firmware downloads, the default
> clock divider can be specified in DT as well. Whenever a ratio change is
> detected in the hw_params callback, the PLL mode lines are updates and a
> full reset cycle is issued.

Why isn't it enough to just use the first setting we see - I'd expect
the device to normally be powered off before audio starts including when
hw_params() is called?
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