[alsa-devel] [RFC PATCH 07/11] dmaengine: PL08x: Fix reading the byte count in cctl

[Tomasz Figa]

On Monday 17 of June 2013 15:53:14 Linus Walleij wrote:
> On Sun, Jun 16, 2013 at 10:54 PM, Tomasz Figa <tomasz.figa at gmail.com> 
wrote:
> > From: Alban Bedel <alban.bedel at avionic-design.de>
> > 
> > There are more fields than just SWIDTH in CH_CONTROL register, so read
> > register value must be masked in addition to shifting.
> > 
> > Signed-off-by: Alban Bedel <alban.bedel at avionic-design.de>
> > Signed-off-by: Tomasz Figa <tomasz.figa at gmail.com>
> 
> Acked-by: Linus Walleij <linus.walleij at linaro.org>
> 
> Are we just lucky on current variants such that all unmasked bits
> happen to be zero on them?

This is really interesting, because if you look at the bit layout, there 
is a lot of other bitfields above the SWIDTH field, like DWIDTH, src and 
dest AHB master selection, src and dest incerement setting, protection and 
terminal count interrupt enable bits.

Best regards,
Tomasz