[alsa-devel] [PATCH] ASoC: Improve EP93xx I2S clocks management.

[Alexander Sverdlin]

Dear Ryan,

On Mon, 2011-03-07 at 11:02 +1300, Ryan Mallon wrote:
> > +	sdiv = 4;
> > +	if (div > (256 + 512) / 2) {
> > +		lrdiv = 128;
> > +	} else {
> > +		lrdiv = 64;
> > +		if (div < (128 + 256) / 2)
> > +			sdiv = 2;
> > +	}
> 
> I don't understand where the magic numbers above come from? Does it work
> correctly for all rates? I think a comment is needed to explain how this
> works.

The Magic is simply centers between divisors. The loop produced only 3
variants of divisors. So do this code. But it's simpler and it prefers
LRDIV = 64. I do not know what do you mean by all rates, with fixed MCLK
there is no way to produce all the rates. With variable MCLK I'm having
full 8000-192000 range now.

> 
> An alternative would be to keep the existing loop form, but try and find
> the closest match rather than an exact match. Something like this
> (untested):

This is huge comparing to 2 ifs... But the main task of keeping LRCLK=64
where possible still can be achieved if we swap to lines:


> 	for (sdiv = 2; sdiv <= 4; sdiv += 2) {
> 		for (lrdiv = 64; lrdiv <= 128; lrdiv <<= 1) {

But I'm sure code proposed by me should work just like previous variant
for you. Could you try it with your configuration please?