[alsa-devel] snd soc spi read/write

[Mark Brown]

On Fri, Aug 05, 2011 at 04:00:52PM +0800, Scott Jiang wrote:

> > Why are you replying off-list?  You should implement 16x8 SPI reads in
> > the core stuff I'd expect, then disable cache for the CODEC.

> Sorry, I just forgot to CC.
> I wonder if rbtree compress type can support this kind of sparse register?

Yes, rbtree works fine with this.  You'd still take a hit on the size of
your register defaults though.

> And should the patch aginst 3.0 or 3.2?

3.0 can't be patched, though you could try submitting a patch to the
stable guys.  Probably best to start off with 3.1 and see where we go
from there.