[alsa-devel] ASoC updates for 2.6.37

[Mark Brown]

On Wed, Oct 06, 2010 at 09:10:23AM +0200, Takashi Iwai wrote:

> If the above difference is intentional, it should be commented
> somewhere.

Meh, yes.  Dimitris, please fix or add a comment as appropriate.

> > They also differ in the type of the cache variable.  You could do
> > something with macros but it'd not be terribly pleasant.

> Hm, this can be tricky.  Meanwhile, we could have it always int,
> instead of different types.  The amount of memory you save by
> supporting different size might be more than the waste of 3 bytes for
> 1 byte data array.

Given the size of the register maps for modern chips with visible DSPs
in them the overhead can be non-trivial.  Doing this also inhibits
operations like doing bulk writes of data from cache (which we don't do
right now but may wish to do in future) since the data can't just be
passed to the bus I/O functions so it's not purely a memory efficiency
thing.