[alsa-devel] [PATCH 4/4] ASoC: soc-cache: Add support for rbtree based register caching

[Mark Brown]

On Thu, Nov 04, 2010 at 02:49:48PM -0400, Mark Brown wrote:

> Hrm, dirty handling is kind of interesting.  It is unconditionally set
> in the write function and never cleared so we'll always rewrite a
> register if it's ever been touched.  Is it worth remembering the default
> values and just comparing with them, the memory overhead will probably
> be low since we only have one bitfield value here...  (and remember that
> we'll be unlikely to allocate memory in 21 byte packed hunks with no
> overhead...).

BTW, this does look like a very nice win overall.