[alsa-devel] [PATCH] ASoC - Add support for upto 16 channels on OMAP MCBSP
Liam Girdwood
lrg at slimlogic.co.uk
Thu Nov 5 15:55:30 CET 2009
On Thu, 2009-11-05 at 09:51 +0200, Jarkko Nikula wrote:
> On Wed, 04 Nov 2009 19:46:49 +0000
> Liam Girdwood <lrg at slimlogic.co.uk> wrote:
>
> > > > + /* calc best frame size for rate and clock divider */
> > > > + do {
> > > > + frame_size = (mcbsp_data->in_freq / div) / params_rate(params);
> > > > + pr_debug("freq %d, rate %d, frame size %d, div %d\n",
> > > > + mcbsp_data->in_freq, params_rate(params), frame_size, div);
> > > > +
> > > > + if (frame_size > 256)
> > > > + div++;
> > > > + } while (frame_size > 256);
> > > > +
>
> This would be better if it tries to calculate minimum frame size. Now
> the algorithm stops when the frame_size is 256 and leads to higher
> bit clock.
>
> E.g. 4 * 16bits * 48 kHz and using 96 MHz internal clock:
>
> Algorithm: div = 8, frame_size = 250 and bit clock = 12 MHz.
>
> Possible dividers and frame_sizes:
>
> 25*80 (-> best, bit clock = 3.840 MHz)
> 20*100
> 16*125
> 10*200
> 8*250
>
I've reworked this myself now. It does appear that the current FPER
calculations assume BCLK scales with rate
i.e. BCLK = rate * channels * word len
This is fine for when McBSP is FRM/BCLK slave (all users except pandora)
as FPER should be ignored internally.
However, when BCLK is constant (e.g. McBSP BCLK derived from constant
source) and we run McBSP as FRM/BCLK master we currently break our
sample rate generation.
Imho, it's better to generate FPER based upon BCLK and rate. e.g. we
calculate the frame size required for the given BCLK and rate.
/* In McBSP master modes, FRAME (i.e. sample rate) is generated
* by _counting_ BCLKs. Calculate frame size in BCLKs */
div = mcbsp_data->clk_div ? mcbsp_data->clk_div : 1;
framesize = (mcbsp_data->in_freq / div) / params_rate(params);
if (framesize < wlen * channels) {
printk(KERN_ERR "%s: not enough bandwidth for desired rate and channels\n",
__func__);
return -EINVAL;
}
/* Set FS period and length in terms of bit clock periods */
switch (format) {
case SND_SOC_DAIFMT_I2S:
regs->srgr2 |= FPER(framesize - 1);
regs->srgr1 |= FWID((framesize >> 1) - 1);
break;
case SND_SOC_DAIFMT_DSP_A:
case SND_SOC_DAIFMT_DSP_B:
regs->srgr2 |= FPER(framesize - 1);
regs->srgr1 |= FWID(0);
break;
}
I'm now slightly curious about how pandora handles different rates since
it uses the McBSP in master mode too. I guess they can only handle a
single sample rate ?
Liam
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