[alsa-devel] Output frequency configuration for I2S in beagleboard? (underrun problem)

[Ernesto Torres]

Thanks for the information, I'll try this approach and see how it goes

BR,
Ernesto

On Fri, May 15, 2009 at 1:23 AM, Peter Ujfalusi <peter.ujfalusi at nokia.com>wrote:

> On Thursday 14 May 2009 18:12:54 ext Ernesto Torres wrote:
> > Hi,
> >
> > The external codec is connected to McBSP3, it has been pinmuxed to use
> the
> > pins on the expansion.
> >
> > The code from the TWL4030 has been erased and replaced by the code for
> the
> > external codec. The files remain the same for now. Board still believes
> is
> > twl4030 but sends info via other addresses.(I2C2 & McBSP3)
> >
> > External codec has 12.288 Mhz clock
> > Beagle has 26Mhz
>
> To be precise:
> TWL4030 codec on Beagle board has 26MHz MCLK.
> This has nothing to do with the McBSP clocking at all.
>
> >
> > From your code:
> > case 48000: /* 48.032 */
> >        div = 54;
> >        clk_id = OMAP_MCBSP_SYSCLK_CLK;
> >        freq = 83000000;
> >        break;
> >
> > If I understand correctly, 48.032 will be the result of the mclk
> division.
> > *
> > (input clock frequency)/(CLKGDV + 1)*= 48.032
>
> Not really, with the clkdiv you get the bitclock.
>
> >
> > *input clock frequency*=OMAP_MCBSP_SYSCLK_CLK
> > *CLKGDV*=div=53(according to : * regs->srgr1    |= CLKGDV(div - 1);)*
> >
> > Doing some math:
> > CLKGDV=div-1=54-1=53
> > 48032*54=input clock frequency=2593728?
>
> This is how you are calculating it:
> 48032*16*2*54=82999296
>
> If we want to have the clocks for 48KHz 16bit stereo playback, and we going
> to
> use OMAP as master:
> Select the clock source for McBSP as OMAP_MCBSP_SYSCLK_CLK, which means
> that
> we are using McBSPi_ICLK for the SRG divider source
> In my HW the McBSPi_ICLK is 83MHz
> Than:
> 83000000 / 16 / 2 / div = 48000
> div = 83000000 / 16 / 2 / 48000
> div = 54.0364 ~= 54
>
> --
> Péter
>



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