[alsa-devel] [PATCH] ASoC: tlv320aic3x: Enable PLL when not bypassed

[Mani, Arun]

Hi Chaithrika,
Do you know why it worked in dm644x. I don't see any specific path taken for the DM644x.

Arun

-----Original Message-----
From: davinci-linux-open-source-bounces at linux.davincidsp.com [mailto:davinci-linux-open-source-bounces at linux.davincidsp.com] On Behalf Of Subrahmanya, Chaithrika
Sent: Wednesday, July 22, 2009 7:45 AM
To: alsa-devel at alsa-project.org
Cc: davinci-linux-open-source at linux.davincidsp.com; broonie at opensource.wolfsonmicro.com
Subject: [PATCH] ASoC: tlv320aic3x: Enable PLL when not bypassed

PLL was not being enabled when it was not bypassed. This patch
enables the PLL when it is used. Additionally, it disables the PLL
when it is bypassed.

Without this patch, the audio on TI DM646x EVM and DM355 EVM
does not work properly. The bit clocks and the frame sync signals
from the codec are not correct and hence the playback/record are faster
than usual for most sample rates. The reason for this was that the PLL
was not enabled when it was not bypassed.

Tested on DM6467 EVM, playback tested on DM355 EVM.

Signed-off-by: Chaithrika U S <chaithrika at ti.com>
---
Applies to master branch of ALSA GIT tree at
http://git.kernel.org/?p=linux/kernel/git/tiwai/sound-2.6.git;a=summary

 sound/soc/codecs/tlv320aic3x.c |   11 ++++++++++-
 1 files changed, 10 insertions(+), 1 deletions(-)

diff --git a/sound/soc/codecs/tlv320aic3x.c b/sound/soc/codecs/tlv320aic3x.c
index ab099f4..cb0d1bf 100644
--- a/sound/soc/codecs/tlv320aic3x.c
+++ b/sound/soc/codecs/tlv320aic3x.c
@@ -767,6 +767,7 @@ static int aic3x_hw_params(struct snd_pcm_substream *substream,
 	int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
 	u8 data, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
 	u16 pll_d = 1;
+	u8 reg;
 
 	/* select data word length */
 	data =
@@ -801,8 +802,16 @@ static int aic3x_hw_params(struct snd_pcm_substream *substream,
 		pll_q &= 0xf;
 		aic3x_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
 		aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
-	} else
+		/* disable PLL if it is bypassed */
+		reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
+		aic3x_write(codec, AIC3X_PLL_PROGA_REG, reg & ~PLL_ENABLE);
+
+	} else {
 		aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
+		/* enable PLL when it is used */
+		reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
+		aic3x_write(codec, AIC3X_PLL_PROGA_REG, reg | PLL_ENABLE);
+	}
 
 	/* Route Left DAC to left channel input and
 	 * right DAC to right channel input */
-- 
1.5.6

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