[alsa-devel] [Pull request] Support for wm9705 codec and two machines that use it.

[Mark Brown]

On Fri, Jan 16, 2009 at 11:34:41AM +0000, Ian Molton wrote:

> It looks like register caching is a very common thing, would you be 
> interested in a patch that consolidates the cache handling in soc-core, 
> rather than having multiple possibly broken implementations around?

There's gotchas with variable register sizes and volatile bits (this was
originally done more in the core but pushed out).  I've looked at it
before and it looked like the best way to handle it was to do it along
with a factoring out of common I/O routines.  Possibly best to leave it
for now.

> Also, I could be wrong, but wm8980 caching looks completely broken 
> (array is type u16 but there is no register shift applied, AFAICT)

There's normally a reason for the non-mainline drivers being that way
but in this case that's not it - the chip has 16 bit registers and the
cache is being worked with as u16 * so natural array indexing should
DTRT.

Please post an incremental patch with your other changes.