[alsa-devel] ASOC, master clock direction

[Jon Smirl]

The MPC5200 has three clock configurations

1) Clock out, normal master mode
2) Clock in, normal slave mode
3) Something Freescale calls cellphone slave but it is more like clock
distribution.

In cellslave mode one i2s port is in normal slave mode. The clock from
this port is used to drive up to three other i2s ports in master mode.

I have two choices for set_sysclk:
#define SND_SOC_CLOCK_IN        0
#define SND_SOC_CLOCK_OUT       1

When the clock frequency changes I need to notify the i2s drivers for
the dependent channels. Do we need a third choice,
SND_SOC_CLOCK_SLAVE? Alternatively I can use another clock id value.

-- 
Jon Smirl
jonsmirl at gmail.com