[alsa-devel] [PATCH] asoc tlv320aic33: skip usage of PLL in some cases

[Jarkko Nikula]

On Fri, Apr 18, 2008 at 2:41 PM, Daniel Mack <daniel at caiaq.org> wrote:

>
> Ok, I agree. I changed that to find an appropriate value for Q
> programmatically. Have a look at the attached patch, please. I hope i
> finally got it now ;)


That sounds a good idea. Then more cases will be covered.

What I noticed that instead of params_rate, I think we should compare here
the FSref of 44.1 and 48 kHz (how about dual-rate mode?) when defining can
the PLL be bypassed

if (params_rate(params) == aic3x->sysclk / (128 * pll_q))

---

Probably you forgot to move bypass case in this version after writing the
AIC3X_SAMPLE_RATE_SEL_REG?

Spec is also saying that when NDAC is 1.5, 2.5, ... 5.5, then odd values of
Q are not allowed.

Not the easiest chip... probably worth to ask from TI what's the case e.g.
when FSref is 2*48 kHz and ADC/DAC rate is 64 kHz (NDAC is 1.5).

And of course, over-designing the driver is not the purpose and probably
some special cases can be now covered just with -EINVAL and let the user who
needs them to send a patch :-)


Jarkko