From: Tomasz Lauda tomasz.lauda@linux.intel.com

There is no APL boot via SRAM right now, so let's enable it.

Signed-off-by: Tomasz Lauda tomasz.lauda@linux.intel.com --- Makefile.am | 15 +- configure.ac | 29 +- src/arch/xtensa/Makefile.am | 15 +- src/arch/xtensa/boot_entry.S | 49 +- src/arch/xtensa/boot_loader.c | 16 +- src/arch/xtensa/crt1-boards.S | 616 +++++++++--------- src/arch/xtensa/reset-vector.S | 8 +- src/arch/xtensa/xtos/crt1-boards.S | 9 +- src/arch/xtensa/xtos/crt1-sim.S | 5 +- src/arch/xtensa/xtos/crt1-tiny.S | 6 +- src/include/sof/trace.h | 3 + src/platform/apollolake/Makefile.am | 14 +- src/platform/apollolake/apollolake.x.in | 133 ++-- src/platform/apollolake/boot_ldr.x.in | 236 +++++++ src/platform/apollolake/boot_module.c | 54 ++ src/platform/apollolake/include/Makefile.am | 2 +- .../apollolake/include/arch/Makefile.am | 1 + .../include/{ => arch}/xtensa/Makefile.am | 0 .../{ => arch}/xtensa/config/Makefile.am | 0 .../{ => arch}/xtensa/config/core-isa.h | 60 +- .../include/arch}/xtensa/config/core-matmap.h | 7 + .../include/arch}/xtensa/config/defs.h | 8 + .../include/arch}/xtensa/config/specreg.h | 8 + .../include/{ => arch}/xtensa/config/system.h | 7 + .../{ => arch}/xtensa/config/tie-asm.h | 8 + .../include/arch}/xtensa/config/tie.h | 8 + .../apollolake/include/platform/memory.h | 112 ++-- .../apollolake/include/platform/platcfg.h | 38 ++ .../apollolake/include/platform/platform.h | 1 + .../apollolake/include/platform/shim.h | 22 +- src/platform/baytrail/include/Makefile.am | 2 +- .../baytrail/include/arch/Makefile.am | 1 + .../include/{ => arch}/xtensa/Makefile.am | 0 .../{ => arch}/xtensa/config/Makefile.am | 0 .../{ => arch}/xtensa/config/core-isa-byt.h | 0 .../{ => arch}/xtensa/config/core-isa-cht.h | 0 .../{ => arch}/xtensa/config/core-isa.h | 0 .../{ => arch}/xtensa/config/core-matmap.h | 0 .../include/arch}/xtensa/config/defs.h | 0 .../{ => arch}/xtensa/config/specreg.h | 0 .../include/{ => arch}/xtensa/config/system.h | 0 .../{ => arch}/xtensa/config/tie-asm.h | 0 .../include/{ => arch}/xtensa/config/tie.h | 0 src/platform/cannonlake/boot_ldr.x.in | 224 +------ src/platform/cannonlake/cannonlake.x.in | 81 +-- src/platform/cannonlake/include/Makefile.am | 2 +- .../cannonlake/include/arch/Makefile.am | 1 + .../include/{ => arch}/xtensa/Makefile.am | 0 .../{ => arch}/xtensa/config/Makefile.am | 1 - .../xtensa/config/core-isa.h} | 58 +- .../include/arch}/xtensa/config/core-matmap.h | 7 + .../include/arch}/xtensa/config/defs.h | 8 + .../include/arch}/xtensa/config/specreg.h | 8 + .../include/{ => arch}/xtensa/config/system.h | 7 + .../{ => arch}/xtensa/config/tie-asm.h | 8 + .../include/arch}/xtensa/config/tie.h | 8 + .../cannonlake/include/platform/memory.h | 32 +- .../cannonlake/include/platform/platcfg.h | 36 + .../cannonlake/include/platform/platform.h | 1 + .../cannonlake/include/platform/shim.h | 6 +- .../include/xtensa/config/core-isa.h | 557 ---------------- src/platform/haswell/include/Makefile.am | 2 +- src/platform/haswell/include/arch/Makefile.am | 1 + .../include/{ => arch}/xtensa/Makefile.am | 0 .../{ => arch}/xtensa/config/Makefile.am | 0 .../{ => arch}/xtensa/config/core-isa-bdw.h | 0 .../{ => arch}/xtensa/config/core-isa-hsw.h | 0 .../{ => arch}/xtensa/config/core-isa.h | 0 .../{ => arch}/xtensa/config/core-matmap.h | 0 .../include/arch}/xtensa/config/defs.h | 0 .../{ => arch}/xtensa/config/specreg.h | 0 .../include/{ => arch}/xtensa/config/system.h | 0 .../{ => arch}/xtensa/config/tie-asm.h | 0 .../include/{ => arch}/xtensa/config/tie.h | 0 74 files changed, 1185 insertions(+), 1356 deletions(-) create mode 100644 src/platform/apollolake/boot_ldr.x.in create mode 100644 src/platform/apollolake/boot_module.c create mode 100644 src/platform/apollolake/include/arch/Makefile.am rename src/platform/apollolake/include/{ => arch}/xtensa/Makefile.am (100%) rename src/platform/apollolake/include/{ => arch}/xtensa/config/Makefile.am (100%) rename src/platform/apollolake/include/{ => arch}/xtensa/config/core-isa.h (95%) rename src/platform/{cannonlake/include => apollolake/include/arch}/xtensa/config/core-matmap.h (99%) rename src/platform/{cannonlake/include => apollolake/include/arch}/xtensa/config/defs.h (94%) rename src/platform/{cannonlake/include => apollolake/include/arch}/xtensa/config/specreg.h (96%) rename src/platform/apollolake/include/{ => arch}/xtensa/config/system.h (99%) rename src/platform/apollolake/include/{ => arch}/xtensa/config/tie-asm.h (99%) rename src/platform/{cannonlake/include => apollolake/include/arch}/xtensa/config/tie.h (98%) create mode 100644 src/platform/apollolake/include/platform/platcfg.h create mode 100644 src/platform/baytrail/include/arch/Makefile.am rename src/platform/baytrail/include/{ => arch}/xtensa/Makefile.am (100%) rename src/platform/baytrail/include/{ => arch}/xtensa/config/Makefile.am (100%) rename src/platform/baytrail/include/{ => arch}/xtensa/config/core-isa-byt.h (100%) rename src/platform/baytrail/include/{ => arch}/xtensa/config/core-isa-cht.h (100%) rename src/platform/baytrail/include/{ => arch}/xtensa/config/core-isa.h (100%) rename src/platform/baytrail/include/{ => arch}/xtensa/config/core-matmap.h (100%) rename src/platform/{apollolake/include => baytrail/include/arch}/xtensa/config/defs.h (100%) rename src/platform/baytrail/include/{ => arch}/xtensa/config/specreg.h (100%) rename src/platform/baytrail/include/{ => arch}/xtensa/config/system.h (100%) rename src/platform/baytrail/include/{ => arch}/xtensa/config/tie-asm.h (100%) rename src/platform/baytrail/include/{ => arch}/xtensa/config/tie.h (100%) create mode 100644 src/platform/cannonlake/include/arch/Makefile.am rename src/platform/cannonlake/include/{ => arch}/xtensa/Makefile.am (100%) rename src/platform/cannonlake/include/{ => arch}/xtensa/config/Makefile.am (84%) rename src/platform/cannonlake/include/{xtensa/config/core-isa-boot.h => arch/xtensa/config/core-isa.h} (95%) rename src/platform/{apollolake/include => cannonlake/include/arch}/xtensa/config/core-matmap.h (99%) rename src/platform/{haswell/include => cannonlake/include/arch}/xtensa/config/defs.h (94%) rename src/platform/{apollolake/include => cannonlake/include/arch}/xtensa/config/specreg.h (96%) rename src/platform/cannonlake/include/{ => arch}/xtensa/config/system.h (99%) rename src/platform/cannonlake/include/{ => arch}/xtensa/config/tie-asm.h (99%) rename src/platform/{apollolake/include => cannonlake/include/arch}/xtensa/config/tie.h (98%) create mode 100644 src/platform/cannonlake/include/platform/platcfg.h delete mode 100644 src/platform/cannonlake/include/xtensa/config/core-isa.h create mode 100644 src/platform/haswell/include/arch/Makefile.am rename src/platform/haswell/include/{ => arch}/xtensa/Makefile.am (100%) rename src/platform/haswell/include/{ => arch}/xtensa/config/Makefile.am (100%) rename src/platform/haswell/include/{ => arch}/xtensa/config/core-isa-bdw.h (100%) rename src/platform/haswell/include/{ => arch}/xtensa/config/core-isa-hsw.h (100%) rename src/platform/haswell/include/{ => arch}/xtensa/config/core-isa.h (100%) rename src/platform/haswell/include/{ => arch}/xtensa/config/core-matmap.h (100%) rename src/platform/{baytrail/include => haswell/include/arch}/xtensa/config/defs.h (100%) rename src/platform/haswell/include/{ => arch}/xtensa/config/specreg.h (100%) rename src/platform/haswell/include/{ => arch}/xtensa/config/system.h (100%) rename src/platform/haswell/include/{ => arch}/xtensa/config/tie-asm.h (100%) rename src/platform/haswell/include/{ => arch}/xtensa/config/tie.h (100%)

diff --git a/Makefile.am b/Makefile.am index ee8df72..5eebb33 100644 --- a/Makefile.am +++ b/Makefile.am @@ -30,8 +30,19 @@ export SOF_INCDIR = \ export ARCH_INCDIR = \ -I $(SRC_DIR)/arch/$(ARCH)/include \ -I $(SRC_DIR)/arch/$(ARCH)/xtos -export PLATFORM_INCDIR = \ - -I $(SRC_DIR)/platform/$(PLATFORM)/include + +PLATFORM_INCDIR = -I $(SRC_DIR)/platform/$(PLATFORM)/include + +if XCC +PLATFORM_INCDIR += \ + -I $(ROOT_DIR)/arch/include +else +PLATFORM_INCDIR += \ + -I $(SRC_DIR)/platform/$(PLATFORM)/include/arch +endif + +export PLATFORM_INCDIR + endif

dist-hook: diff --git a/configure.ac b/configure.ac index 3c914a9..0d810b3 100644 --- a/configure.ac +++ b/configure.ac @@ -156,6 +156,7 @@ case "$with_platform" in AC_SUBST(XTENSA_CORE)

AC_DEFINE([CONFIG_APOLLOLAKE], [1], [Configure for Apololake]) + AC_DEFINE([CONFIG_BOOT_LOADER], [1], [Configure Boot Loader]) AC_DEFINE([CONFIG_IRQ_MAP], [1], [Configure IRQ maps]) AC_DEFINE([CONFIG_DMA_GW], [1], [Configure DMA Gateway]) ;; @@ -208,6 +209,7 @@ case "$with_platform" in AC_SUBST(XTENSA_CORE)

AC_DEFINE([CONFIG_CANNONLAKE], [1], [Configure for Cannonlake]) + AC_DEFINE([CONFIG_BOOT_LOADER], [1], [Configure Boot Loader]) AC_DEFINE([CONFIG_IRQ_MAP], [1], [Configure IRQ maps]) AC_DEFINE([CONFIG_DMA_GW], [1], [Configure DMA Gateway]) ;; @@ -229,7 +231,7 @@ AM_CONDITIONAL(BUILD_HASWELL, test "$FW_NAME" = "hsw") AM_CONDITIONAL(BUILD_BROADWELL, test "$FW_NAME" = "bdw") AM_CONDITIONAL(BUILD_APOLLOLAKE, test "$FW_NAME" = "apl") AM_CONDITIONAL(BUILD_CANNONLAKE, test "$FW_NAME" = "cnl") -AM_CONDITIONAL(BUILD_BOOTLOADER, test "$FW_NAME" = "cnl") +AM_CONDITIONAL(BUILD_BOOTLOADER, test "$FW_NAME" = "apl" -o "$FW_NAME" = "cnl") AM_CONDITIONAL(BUILD_MODULE, test "$FW_NAME" = "apl" -o "$FW_NAME" = "cnl") AM_CONDITIONAL(BUILD_APL_SSP, test "$FW_NAME" = "apl" -o "$FW_NAME" = "cnl")

@@ -343,6 +345,9 @@ if test "$have_graphviz" = "false"; then AC_MSG_WARN([Need graphviz to build documentation]) fi

+# Check for compiler type +AM_CONDITIONAL(XCC, test "$CC" = "xt-xcc") + AM_EXTRA_RECURSIVE_TARGETS([bin])

AM_EXTRA_RECURSIVE_TARGETS([vminstall]) @@ -367,7 +372,7 @@ AC_CONFIG_FILES([ src/arch/host/include/Makefile src/arch/host/include/arch/Makefile src/audio/Makefile - src/math/Makefile + src/math/Makefile src/drivers/Makefile src/include/Makefile src/include/sof/Makefile @@ -385,24 +390,28 @@ AC_CONFIG_FILES([ src/platform/Makefile src/platform/baytrail/Makefile src/platform/baytrail/include/Makefile + src/platform/baytrail/include/arch/Makefile + src/platform/baytrail/include/arch/xtensa/Makefile + src/platform/baytrail/include/arch/xtensa/config/Makefile src/platform/baytrail/include/platform/Makefile - src/platform/baytrail/include/xtensa/Makefile - src/platform/baytrail/include/xtensa/config/Makefile src/platform/apollolake/Makefile src/platform/apollolake/include/Makefile + src/platform/apollolake/include/arch/Makefile + src/platform/apollolake/include/arch/xtensa/Makefile + src/platform/apollolake/include/arch/xtensa/config/Makefile src/platform/apollolake/include/platform/Makefile - src/platform/apollolake/include/xtensa/Makefile - src/platform/apollolake/include/xtensa/config/Makefile src/platform/haswell/Makefile src/platform/haswell/include/Makefile + src/platform/haswell/include/arch/Makefile + src/platform/haswell/include/arch/xtensa/Makefile + src/platform/haswell/include/arch/xtensa/config/Makefile src/platform/haswell/include/platform/Makefile - src/platform/haswell/include/xtensa/Makefile - src/platform/haswell/include/xtensa/config/Makefile src/platform/cannonlake/Makefile src/platform/cannonlake/include/Makefile + src/platform/cannonlake/include/arch/Makefile + src/platform/cannonlake/include/arch/xtensa/Makefile + src/platform/cannonlake/include/arch/xtensa/config/Makefile src/platform/cannonlake/include/platform/Makefile - src/platform/cannonlake/include/xtensa/Makefile - src/platform/cannonlake/include/xtensa/config/Makefile ]) AC_OUTPUT

diff --git a/src/arch/xtensa/Makefile.am b/src/arch/xtensa/Makefile.am index d966691..50d3ded 100644 --- a/src/arch/xtensa/Makefile.am +++ b/src/arch/xtensa/Makefile.am @@ -5,9 +5,16 @@ noinst_PROGRAMS = \

# generate linker script from platform headers LINK_SCRIPT = ../../platform/$(PLATFORM)/$(PLATFORM_LDSCRIPT) -LINK_DEPS = \ - ../../platform/$(PLATFORM)/include/platform/memory.h \ - ../../platform/$(PLATFORM)/include/xtensa/config/core-isa* + +LINK_DEPS = ../../platform/$(PLATFORM)/include/platform/memory.h + +if XCC +LINK_DEPS += \ + $(ROOT_DIR)/arch/include/xtensa/config/core-isa* +else +LINK_DEPS += \ + ../../platform/$(PLATFORM)/include/arch/xtensa/config/core-isa* +endif

nodist_sof_SOURCES = $(LINK_SCRIPT).in BUILT_SOURCES = $(LINK_SCRIPT) @@ -35,7 +42,7 @@ sof_SOURCES = \ timer.c \ task.c

-if BUILD_CANNONLAKE +if BUILD_BOOTLOADER sof_SOURCES += \ main-entry.S endif diff --git a/src/arch/xtensa/boot_entry.S b/src/arch/xtensa/boot_entry.S index cf793f5..6f462b6 100644 --- a/src/arch/xtensa/boot_entry.S +++ b/src/arch/xtensa/boot_entry.S @@ -37,8 +37,9 @@

#include <config.h> #include <platform/shim.h> +#include <platform/platcfg.h> #include <xtensa/corebits.h> -#include <xtensa/config/core-isa-boot.h> +#include <xtensa/config/core-isa.h>

.type boot_pri_core, @function .type boot_sec_core, @function @@ -55,18 +56,62 @@ boot_entry:

.align 4 .literal_position +#if defined(PLATFORM_RESET_MHE_AT_BOOT) l2_mecs: .word SHIM_L2_MECS +#endif + +#if defined(PLATFORM_DISABLE_L2CACHE_AT_BOOT) +l2_cache_pref: + .word SHIM_L2_PREF_CFG +#endif + +sof_stack_base: + .word SOF_STACK_BASE + +wnd0_base: + .word DMWBA(0) + +wnd0_size: + .word DMWLO(0) + +wnd0_base_val: + .word HP_SRAM_WIN0_BASE | DMWBA_READONLY | DMWBA_ENABLE + +wnd0_size_val: + .word HP_SRAM_WIN0_SIZE | 0x7

boot_init: .align 4 -#if defined(CONFIG_CANNONLAKE) +#if defined(PLATFORM_DISABLE_L2CACHE_AT_BOOT) + l32r a3, l2_cache_pref + movi a5, 0 + s32i a5, a3, 0 + memw +#endif + +#if defined(PLATFORM_RESET_MHE_AT_BOOT) /* reset memory hole */ l32r a3, l2_mecs movi a5, 0 s32i a5, a3, 0 #endif

+ /* reprogram stack to the area defined by main FW */ + l32r a3, sof_stack_base + mov sp, a3 + + /* realloc memory window0 to + continue reporting boot progress */ + l32r a3, wnd0_size + l32r a5, wnd0_size_val + s32i a5, a3, 0 + memw + l32r a3, wnd0_base + l32r a5, wnd0_base_val + s32i a5, a3, 0 + memw + #if (XCHAL_DCACHE_IS_COHERENT || XCHAL_LOOP_BUFFER_SIZE) && \ XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0 /* Enable zero-overhead loop instr buffer, diff --git a/src/arch/xtensa/boot_loader.c b/src/arch/xtensa/boot_loader.c index ccf8525..297aa36 100644 --- a/src/arch/xtensa/boot_loader.c +++ b/src/arch/xtensa/boot_loader.c @@ -33,6 +33,7 @@ #include <sof/trace.h> #include <sof/io.h> #include <uapi/manifest.h> +#include <platform/platform.h> #include <platform/memory.h>

/* entry point to main firmware */ @@ -41,7 +42,7 @@ extern void _ResetVector(void); void boot_pri_core(void); void boot_sec_core(void);

-#if defined(CONFIG_CANNONLAKE) +#if defined(CONFIG_BOOT_LOADER)

/* memcopy used by boot loader */ static inline void bmemcpy(void *dest, void *src, size_t bytes) @@ -77,6 +78,7 @@ static void parse_module(struct sof_man_fw_header *hdr, /* each module has 3 segments */ for (i = 0; i < 3; i++) {

+ platform_trace_point(TRACE_BOOT_LDR_PARSE_SEGMENT + i); switch (mod->segment[i].flags.r.type) { case SOF_MAN_SEGMENT_TEXT: case SOF_MAN_SEGMENT_DATA: @@ -112,6 +114,7 @@ static void parse_manifest(void) /* copy module to SRAM - skip bootloader module */ for (i = 1; i < hdr->num_module_entries; i++) {

+ platform_trace_point(TRACE_BOOT_LDR_PARSE_MODULE + i); mod = sof_man_get_module(desc, i); parse_module(hdr, mod); } @@ -119,6 +122,7 @@ static void parse_manifest(void) #endif

/* power on HPSRAM */ +#if defined(CONFIG_CANNONLAKE) static int32_t hp_sram_init(void) { int delay_count = 256; @@ -158,6 +162,14 @@ static int32_t hp_sram_init(void)

return 0; } +#endif + +#if defined(CONFIG_APOLLOLAKE) +static int32_t hp_sram_init(void) +{ + return 0; +} +#endif

/* boot secondary core - i.e core ID > 0 */ void boot_sec_core(void) @@ -185,7 +197,7 @@ void boot_pri_core(void) return; }

-#if defined(CONFIG_CANNONLAKE) +#if defined(CONFIG_BOOT_LOADER) /* parse manifest and copy modules */ platform_trace_point(TRACE_BOOT_LDR_MANIFEST); parse_manifest(); diff --git a/src/arch/xtensa/crt1-boards.S b/src/arch/xtensa/crt1-boards.S index ff24bfd..a66fe84 100644 --- a/src/arch/xtensa/crt1-boards.S +++ b/src/arch/xtensa/crt1-boards.S @@ -1,303 +1,313 @@ -// crt1-boards.S -// -// For most hardware / boards, this code sets up the C calling context -// (setting up stack, PS, and clearing BSS) and jumps to __clibrary_start -// which sets up the C library, calls constructors and registers destructors, -// and calls main(). -// -// Control arrives here at _start from the reset vector or from crt0-app.S. - -// Copyright (c) 1998-2010 Tensilica Inc. -// -// Permission is hereby granted, free of charge, to any person obtaining -// a copy of this software and associated documentation files (the -// "Software"), to deal in the Software without restriction, including -// without limitation the rights to use, copy, modify, merge, publish, -// distribute, sublicense, and/or sell copies of the Software, and to -// permit persons to whom the Software is furnished to do so, subject to -// the following conditions: -// -// The above copyright notice and this permission notice shall be included -// in all copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY -// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE -// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -#include <xtensa/coreasm.h> -// DF #include "xtos-internal.h" -//#include <xtensa/../../src/xtos/xtos-internal.h> - -//.global _ResetVector -#if 0 -/* - * Reset vector. - * Only a trampoline to jump to _start - * (Note that we have to mark the section writable as the section contains - * a relocatable literal) - */ - - .section .ResetVector.text, "awx" - .global _ResetVector -_ResetVector: - - j 1f - .align 4 -2: .long _start -1: l32r a2, 2b - jx a2 -#endif - -// Exports -.global _start - -// Imports -// __clibrary_init from C library (eg. newlib or uclibc) -// exit from C library -// main from user application -// board_init board-specific (uart/mingloss/tinygloss.c) -// xthal_dcache_all_writeback from HAL library -// __stack from linker script (see LSP Ref Manual) -// _bss_table_start from linker script (see LSP Ref Manual) -// _bss_table_end from linker script (see LSP Ref Manual) - -.type main, @function - -// Macros to abstract away ABI differences - -#if __XTENSA_CALL0_ABI__ -# define CALL call0 -# define ARG1 a2 /* 1st outgoing call argument */ -# define ARG2 a3 /* 2nd outgoing call argument */ -# define ARG3 a4 /* 3rd outgoing call argument */ -# define ARG4 a5 /* 4th outgoing call argument */ -# define ARG5 a6 /* 5th outgoing call argument */ -#else -# define CALL call4 -# define CALLX callx4 -# define ARG1 a6 /* 1st outgoing call argument */ -# define ARG2 a7 /* 2nd outgoing call argument */ -# define ARG3 a8 /* 3rd outgoing call argument */ -# define ARG4 a9 /* 4th outgoing call argument */ -# define ARG5 a10 /* 5th outgoing call argument */ -#endif - - -/**************************************************************************/ - - .text - .align 4 - .literal_position -_start: - // _start is typically NOT at the beginning of the text segment -- - // it is always called from either the reset vector or other code - // that does equivalent initialization (such as crt0-app.S). - // - // Assumptions on entry to _start: - // - low (level-one) and medium priority interrupts are disabled - // via PS.INTLEVEL and/or INTENABLE (PS.INTLEVEL is expected to - // be zeroed, to potentially enable them, before calling main) - // - C calling context not initialized: - // - PS not initialized - // - SP not initialized - // - the following are initialized: - // - LITBASE, cache attributes, WindowBase, WindowStart, - // CPENABLE, FP's FCR and FSR, EXCSAVE[n] - - // Keep a0 zero. It is used to initialize a few things. - // It is also the return address, where zero indicates - // that the frame used by _start is the bottommost frame. - // -#if !XCHAL_HAVE_HALT || !XCHAL_HAVE_BOOTLOADER // not needed for Xtensa TX - movi a0, 0 // keep this register zero. -#endif - -#if XTOS_RESET_UNNEEDED && !XCHAL_HAVE_HALT -#include "reset-unneeded.S" -#endif - -#if XCHAL_HAVE_BOOTLOADER - .weak _Level2FromVector - .weak _Level3FromVector - .weak _Level4FromVector - .weak _Level5FromVector - - movi a4, _Level2FromVector - wsr a4, EXCSAVE+2 - movi a4, _Level3FromVector - wsr a4, EXCSAVE+3 - movi a4, _Level4FromVector - wsr a4, EXCSAVE+4 - movi a4, _Level5FromVector - wsr a4, EXCSAVE+5 -#endif - - // Initialize the stack pointer. - // See the "ABI and Software Conventions" chapter in the - // Xtensa ISA Reference manual for details. - - // NOTE: Because the _start routine does not use any memory in its - // stack frame, and because all of its CALL instructions use a - // window size of 4 (or zero), the stack frame for _start can be empty. - - movi sp, __stack - - /* - * Now that sp (a1) is set, we can set PS as per the application - * (user vector mode, enable interrupts, enable window exceptions if applicable). - */ -#if XCHAL_HAVE_EXCEPTIONS -# ifdef __XTENSA_CALL0_ABI__ - movi a3, PS_UM // PS.WOE = 0, PS.UM = 1, PS.EXCM = 0, PS.INTLEVEL = 0 -# else - movi a3, PS_UM|PS_WOE // PS.WOE = 1, PS.UM = 1, PS.EXCM = 0, PS.INTLEVEL = 0 -# endif - wsr a3, PS - rsync -#endif - -/* - * Do any initialization that affects the memory map, such as - * setting up TLB entries, that needs to be done before we can - * successfully clear BSS (e.g. if some BSS segments are in - * remapped areas). - * - * NOTE: This hook works where the reset vector does not unpack - * segments (see "ROM packing" in the LSP manual), or where - * unpacking of segments is not affected by memory remapping. - * If ROM unpacking is affected, TLB setup must be done in - * assembler from the reset vector. - * - * The __memmap_init() routine can be a C function, however it - * does not have BSS initialized! In particular, __memmap_init() - * cannot set BSS variables, i.e. uninitialized global variables - * (they'll be wiped out by the following BSS clear), nor can it - * assume they are yet initialized to zero. - * - * The __memmap_init() function is optional. It is marked as a - * weak symbol, so that it gets valued zero if not defined. - */ - - .weak __memmap_init - movi a4, __memmap_init - beqz a4, 1f - CALLX a4 -1: - -#if !XCHAL_HAVE_BOOTLOADER /* boot loader takes care of zeroing BSS */ - /* - * Clear the BSS (uninitialized data) segments. - * This code supports multiple zeroed sections (*.bss). - * - * Register allocation: - * a0 = 0 - * a6 = pointer to start of table, and through table - * a7 = pointer to end of table - * a8 = start address of bytes to be zeroed - * a9 = end address of bytes to be zeroed - * a10 = length of bytes to be zeroed - */ - movi a0, 0 - movi a6, _bss_table_start - movi a7, _bss_table_end - bgeu a6, a7, .L3zte - -.L0zte: l32i a8, a6, 0 // get start address, assumed multiple of 4 - l32i a9, a6, 4 // get end address, assumed multiple of 4 - addi a6, a6, 8 // next entry - sub a10, a9, a8 // a10 = length, assumed a multiple of 4 - bbci.l a10, 2, .L1zte - s32i a0, a8, 0 // clear 4 bytes to make length multiple of 8 - addi a8, a8, 4 -.L1zte: bbci.l a10, 3, .L2zte - s32i a0, a8, 0 // clear 8 bytes to make length multiple of 16 - s32i a0, a8, 4 - addi a8, a8, 8 -.L2zte: srli a10, a10, 4 // length is now multiple of 16, divide by 16 - floopnez a10, clearzte - s32i a0, a8, 0 // clear 16 bytes at a time... - s32i a0, a8, 4 - s32i a0, a8, 8 - s32i a0, a8, 12 - addi a8, a8, 16 - floopend a10, clearzte - - bltu a6, a7, .L0zte // loop until end of table of *.bss sections -.L3zte: -#endif - - - // We can now call C code, the C calling environment has been initialized. - // - // From this point on, we use ABI-specific macros to refer to registers a0 .. a15 - // (ARG#). - - -#if XCHAL_HAVE_HALT - // Assume minimalist environment for memory-constrained TX cores. - // No C library or board initialization, no parameters passed to main - // (assume declared as "void main(void)") and no call to exit(). - - CALL main - halt - -#else /* !HALT */ - - .type board_init, @function - .type __clibrary_init, @function - .type exit, @function - - - // Initialize the board (eg. the UART on the XT2000). - //CALL board_init - - /* - * Call __clibrary_init to initialize the C library: - * - * void __clibrary_init(int argc, char ** argv, char ** environ, - * void(*init_func)(void), void(*fini_func)(void)); - */ - - // Pass an empty argv array, with an empty string as the program name. -#if 0 - movi ARG1, _start_argc // argc address - movi ARG2, _start_argv // argv = ["", 0] - movi ARG3, _start_envp // envp = [0] -// movi ARG4, _init // function that calls constructors -// movi ARG5, _fini // function that calls destructors - l32i ARG1, ARG1, 0 // argc = 1 - CALL __clibrary_init -#endif - // Call: int main(int argc, char ** argv, char ** environ); - movi ARG1, _start_argc // argc address - movi ARG2, _start_argv // argv = ["", 0] - movi ARG3, _start_envp // envp = [0] - l32i ARG1, ARG1, 0 // argc = 1 - CALL main - // The return value is the same register as the first outgoing argument. -// CALL exit // exit with main's return value - // Does not return here. - - .data - // Mark argc/argv/envp parameters as weak so that an external - // object file can override them. - .weak _start_argc, _start_argv, _start_envp - .align 4 -_start_argv: - .word _start_null // empty program name -_start_null: -_start_envp: - .word 0 // end of argv array, empty string, empty environ -_start_argc: - .word 1 // one argument (program name) - .text - -#endif /* !HALT */ - - .size _start, . - _start - -//#endif +// crt1-boards.S +// +// For most hardware / boards, this code sets up the C calling context +// (setting up stack, PS, and clearing BSS) and jumps to __clibrary_start +// which sets up the C library, calls constructors and registers destructors, +// and calls main(). +// +// Control arrives here at _start from the reset vector or from crt0-app.S. + +// Copyright (c) 1998-2010 Tensilica Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +#include <xtensa/coreasm.h> +#include <config.h> +// DF #include "xtos-internal.h" +//#include <xtensa/../../src/xtos/xtos-internal.h> + +//.global _ResetVector +#if 0 +/* + * Reset vector. + * Only a trampoline to jump to _start + * (Note that we have to mark the section writable as the section contains + * a relocatable literal) + */ + + .section .ResetVector.text, "awx" + .global _ResetVector +_ResetVector: + + j 1f + .align 4 +2: .long _start +1: l32r a2, 2b + jx a2 +#endif + +// Exports +.global _start + +// Imports +// __clibrary_init from C library (eg. newlib or uclibc) +// exit from C library +// main from user application +// board_init board-specific (uart/mingloss/tinygloss.c) +// xthal_dcache_all_writeback from HAL library +// __stack from linker script (see LSP Ref Manual) +// _bss_table_start from linker script (see LSP Ref Manual) +// _bss_table_end from linker script (see LSP Ref Manual) + +.type main, @function + +// Macros to abstract away ABI differences + +#if __XTENSA_CALL0_ABI__ +# define CALL call0 +# define ARG1 a2 /* 1st outgoing call argument */ +# define ARG2 a3 /* 2nd outgoing call argument */ +# define ARG3 a4 /* 3rd outgoing call argument */ +# define ARG4 a5 /* 4th outgoing call argument */ +# define ARG5 a6 /* 5th outgoing call argument */ +#else +# define CALL call4 +# define CALLX callx4 +# define ARG1 a6 /* 1st outgoing call argument */ +# define ARG2 a7 /* 2nd outgoing call argument */ +# define ARG3 a8 /* 3rd outgoing call argument */ +# define ARG4 a9 /* 4th outgoing call argument */ +# define ARG5 a10 /* 5th outgoing call argument */ +#endif + + +/**************************************************************************/ + + .text + .align 4 + .literal_position +_start: + // _start is typically NOT at the beginning of the text segment -- + // it is always called from either the reset vector or other code + // that does equivalent initialization (such as crt0-app.S). + // + // Assumptions on entry to _start: + // - low (level-one) and medium priority interrupts are disabled + // via PS.INTLEVEL and/or INTENABLE (PS.INTLEVEL is expected to + // be zeroed, to potentially enable them, before calling main) + // - C calling context not initialized: + // - PS not initialized + // - SP not initialized + // - the following are initialized: + // - LITBASE, cache attributes, WindowBase, WindowStart, + // CPENABLE, FP's FCR and FSR, EXCSAVE[n] + + // Keep a0 zero. It is used to initialize a few things. + // It is also the return address, where zero indicates + // that the frame used by _start is the bottommost frame. + // + +// not needed for Xtensa TX +#if !XCHAL_HAVE_HALT || !defined(CONFIG_BOOT_LOADER) + movi a0, 0 // keep this register zero. +#endif + +#if XTOS_RESET_UNNEEDED && !XCHAL_HAVE_HALT +#include "reset-unneeded.S" +#endif + +#if defined(CONFIG_BOOT_LOADER) + .weak _Level2FromVector + .weak _Level3FromVector + .weak _Level4FromVector + .weak _Level5FromVector + + movi a4, _Level2FromVector + wsr a4, EXCSAVE+2 + movi a4, _Level3FromVector + wsr a4, EXCSAVE+3 + movi a4, _Level4FromVector + wsr a4, EXCSAVE+4 + movi a4, _Level5FromVector + wsr a4, EXCSAVE+5 +#endif + + // Initialize the stack pointer. + // See the "ABI and Software Conventions" chapter in the + // Xtensa ISA Reference manual for details. + + // NOTE: Because the _start routine does not use any memory in its + // stack frame, and because all of its CALL instructions use a + // window size of 4 (or zero), the stack frame for _start can be empty. + + movi sp, __stack + + /* + * Now that sp (a1) is set, we can set PS as per the application + * (user vector mode, enable interrupts, + * enable window exceptions if applicable). + */ +#if XCHAL_HAVE_EXCEPTIONS +# ifdef __XTENSA_CALL0_ABI__ + // PS.WOE = 0, PS.UM = 1, PS.EXCM = 0, PS.INTLEVEL = 0 + movi a3, PS_UM +# else + // PS.WOE = 1, PS.UM = 1, PS.EXCM = 0, PS.INTLEVEL = 0 + movi a3, PS_UM|PS_WOE +# endif + wsr a3, PS + rsync +#endif + +/* + * Do any initialization that affects the memory map, such as + * setting up TLB entries, that needs to be done before we can + * successfully clear BSS (e.g. if some BSS segments are in + * remapped areas). + * + * NOTE: This hook works where the reset vector does not unpack + * segments (see "ROM packing" in the LSP manual), or where + * unpacking of segments is not affected by memory remapping. + * If ROM unpacking is affected, TLB setup must be done in + * assembler from the reset vector. + * + * The __memmap_init() routine can be a C function, however it + * does not have BSS initialized! In particular, __memmap_init() + * cannot set BSS variables, i.e. uninitialized global variables + * (they'll be wiped out by the following BSS clear), nor can it + * assume they are yet initialized to zero. + * + * The __memmap_init() function is optional. It is marked as a + * weak symbol, so that it gets valued zero if not defined. + */ + + .weak __memmap_init + movi a4, __memmap_init + beqz a4, 1f + CALLX a4 +1: + +/* boot loader takes care of zeroing BSS */ +#if !defined(CONFIG_BOOT_LOADER) + /* + * Clear the BSS (uninitialized data) segments. + * This code supports multiple zeroed sections (*.bss). + * + * Register allocation: + * a0 = 0 + * a6 = pointer to start of table, and through table + * a7 = pointer to end of table + * a8 = start address of bytes to be zeroed + * a9 = end address of bytes to be zeroed + * a10 = length of bytes to be zeroed + */ + movi a0, 0 + movi a6, _bss_table_start + movi a7, _bss_table_end + bgeu a6, a7, .L3zte + +.L0zte: l32i a8, a6, 0 // get start address, assumed multiple of 4 + l32i a9, a6, 4 // get end address, assumed multiple of 4 + addi a6, a6, 8 // next entry + sub a10, a9, a8 // a10 = length, assumed a multiple of 4 + bbci.l a10, 2, .L1zte + s32i a0, a8, 0 // clear 4 bytes to make length multiple of 8 + addi a8, a8, 4 +.L1zte: bbci.l a10, 3, .L2zte + s32i a0, a8, 0 // clear 8 bytes to make length multiple of 16 + s32i a0, a8, 4 + addi a8, a8, 8 +.L2zte: srli a10, a10, 4 // length is now multiple of 16, divide by 16 + floopnez a10, clearzte + s32i a0, a8, 0 // clear 16 bytes at a time... + s32i a0, a8, 4 + s32i a0, a8, 8 + s32i a0, a8, 12 + addi a8, a8, 16 + floopend a10, clearzte + + bltu a6, a7, .L0zte // loop until end of table of *.bss sections +.L3zte: +#endif + + + // We can now call C code, + // the C calling environment has been initialized. + // + // From this point on, we use ABI-specific macros to refer + // to registers a0 .. a15 + // (ARG#). + + +#if XCHAL_HAVE_HALT + // Assume minimalist environment for memory-constrained TX cores. + // No C library or board initialization, no parameters passed to main + // (assume declared as "void main(void)") and no call to exit(). + + CALL main + halt + +#else /* !HALT */ + + .type board_init, @function + .type __clibrary_init, @function + .type exit, @function + + + // Initialize the board (eg. the UART on the XT2000). + //CALL board_init + + /* + * Call __clibrary_init to initialize the C library: + * + * void __clibrary_init(int argc, char ** argv, char ** environ, + * void(*init_func)(void), void(*fini_func)(void)); + */ + + // Pass an empty argv array, with an empty string as the program name. +#if 0 + movi ARG1, _start_argc // argc address + movi ARG2, _start_argv // argv = ["", 0] + movi ARG3, _start_envp // envp = [0] +// movi ARG4, _init // function that calls constructors +// movi ARG5, _fini // function that calls destructors + l32i ARG1, ARG1, 0 // argc = 1 + CALL __clibrary_init +#endif + // Call: int main(int argc, char ** argv, char ** environ); + movi ARG1, _start_argc // argc address + movi ARG2, _start_argv // argv = ["", 0] + movi ARG3, _start_envp // envp = [0] + l32i ARG1, ARG1, 0 // argc = 1 + CALL main + // The return value is the same register + // as the first outgoing argument. +// CALL exit // exit with main's return value + // Does not return here. + + .data + // Mark argc/argv/envp parameters as weak so that an external + // object file can override them. + .weak _start_argc, _start_argv, _start_envp + .align 4 +_start_argv: + .word _start_null // empty program name +_start_null: +_start_envp: + .word 0 // end of argv array, empty string, empty environ +_start_argc: + .word 1 // one argument (program name) + .text + +#endif /* !HALT */ + + .size _start, . - _start + +//#endif diff --git a/src/arch/xtensa/reset-vector.S b/src/arch/xtensa/reset-vector.S index 397dbe2..099a578 100644 --- a/src/arch/xtensa/reset-vector.S +++ b/src/arch/xtensa/reset-vector.S @@ -35,7 +35,7 @@ #include "xtos-internal.h" #include <config.h>

-#if XCHAL_HAVE_BOOTLOADER +#if CONFIG_BOOT_LOADER #include <platform/memory.h> #endif

@@ -119,7 +119,7 @@ _reset_sram: # endif # endif

-#if defined(CONFIG_APOLLOLAKE) || defined(CONFIG_CANNONLAKE) +#if defined(CONFIG_BOOT_LOADER) .section .ResetHandler.text, "ax" j _ResetHandler #endif @@ -525,7 +525,7 @@ unpackdone: */ #if HAVE_XSR

-#if !XCHAL_HAVE_BOOTLOADER +#if !defined(CONFIG_BOOT_LOADER) /* For asm macros; works for positive a,b smaller than 1000: */ # define GREATERTHAN(a,b) (((b)-(a)) & ~0xFFF)

@@ -579,7 +579,7 @@ unpackdone: * Note: This needs to be call0 regardless of the selected ABI. */

-#if XCHAL_HAVE_BOOTLOADER +#if CONFIG_BOOT_LOADER /*ToDo refine the _start*/ movi a0, SOF_TEXT_START callx0 a0 diff --git a/src/arch/xtensa/xtos/crt1-boards.S b/src/arch/xtensa/xtos/crt1-boards.S index 7df5a4b..5704826 100644 --- a/src/arch/xtensa/xtos/crt1-boards.S +++ b/src/arch/xtensa/xtos/crt1-boards.S @@ -30,6 +30,7 @@

#include <xtensa/coreasm.h> #include "xtos-internal.h" +#include <config.h>

// Exports @@ -92,7 +93,9 @@ _start: // It is also the return address, where zero indicates // that the frame used by _start is the bottommost frame. // -#if !XCHAL_HAVE_HALT || !XCHAL_HAVE_BOOTLOADER // not needed for Xtensa TX + +// not needed for Xtensa TX +#if !XCHAL_HAVE_HALT || !defined(CONFIG_BOOT_LOADER) movi a0, 0 // keep this register zero. #endif

@@ -152,8 +155,8 @@ _start: CALLX a4 1:

- -#if !XCHAL_HAVE_BOOTLOADER /* boot loader takes care of zeroing BSS */ +/* boot loader takes care of zeroing BSS */ +#if !defined(CONFIG_BOOT_LOADER)

# ifdef __XTENSA_CALL0_ABI__ // Clear a0 again as possible CALLX to __memmap_init changed it. diff --git a/src/arch/xtensa/xtos/crt1-sim.S b/src/arch/xtensa/xtos/crt1-sim.S index 6d4a5f1..19f7f7d 100644 --- a/src/arch/xtensa/xtos/crt1-sim.S +++ b/src/arch/xtensa/xtos/crt1-sim.S @@ -28,6 +28,7 @@ #include <xtensa/simcall.h> #include <xtensa/coreasm.h> #include "xtos-internal.h" +#include <config.h>

// Exports @@ -184,7 +185,9 @@ _start:

/* The new ISS simcall only appeared after RB-2007.2: */ -#if !XCHAL_HAVE_BOOTLOADER && (XCHAL_HW_MAX_VERSION > XTENSA_HWVERSION_RB_2007_2) /* pre-LX2 cores only */ +#if !defined(CONFIG_BOOT_LOADER) && + /* pre-LX2 cores only */ + (XCHAL_HW_MAX_VERSION > XTENSA_HWVERSION_RB_2007_2) /* * Clear the BSS (uninitialized data) segments. * This code supports multiple zeroed sections (*.bss). diff --git a/src/arch/xtensa/xtos/crt1-tiny.S b/src/arch/xtensa/xtos/crt1-tiny.S index c798ad0..bc6360f 100644 --- a/src/arch/xtensa/xtos/crt1-tiny.S +++ b/src/arch/xtensa/xtos/crt1-tiny.S @@ -34,6 +34,7 @@ #include <xtensa/coreasm.h> #include <xtensa/xtensa-versions.h> #include <xtensa/simcall.h> +#include <config.h>

// Imports @@ -63,7 +64,8 @@ _start: // See crt1-boards.S for assumptions on entry to _start , // and for comments on what is being done in this file.

-#if !XCHAL_HAVE_HALT || !XCHAL_HAVE_BOOTLOADER // not needed for Xtensa TX +// not needed for Xtensa TX +#if !XCHAL_HAVE_HALT || !defined(CONFIG_BOOT_LOADER) movi a0, 0 // mark base of call stack #endif

@@ -85,7 +87,7 @@ _start: // This code only supports .bss, not multiple *.bss sections. // Corresponding code in crt1-boards.S does, and is faster but bigger.

-#if !XCHAL_HAVE_BOOTLOADER +#if !defined(CONFIG_BOOT_LOADER) movi a6, _bss_start movi a7, _bss_end bgeu a6, a7, 2f diff --git a/src/include/sof/trace.h b/src/include/sof/trace.h index 2fd77fe..0e339b5 100644 --- a/src/include/sof/trace.h +++ b/src/include/sof/trace.h @@ -47,6 +47,9 @@ #define TRACE_BOOT_LDR_MANIFEST 0x120 #define TRACE_BOOT_LDR_JUMP 0x150

+#define TRACE_BOOT_LDR_PARSE_MODULE 0x210 +#define TRACE_BOOT_LDR_PARSE_SEGMENT 0x220 + /* general trace init codes - only used at boot when main trace is not available */ #define TRACE_BOOT_START 0x1000 #define TRACE_BOOT_ARCH 0x2000 diff --git a/src/platform/apollolake/Makefile.am b/src/platform/apollolake/Makefile.am index fcf321e..09f43df 100644 --- a/src/platform/apollolake/Makefile.am +++ b/src/platform/apollolake/Makefile.am @@ -1,6 +1,8 @@ SUBDIRS = include

-EXTRA_DIST = apollolake.x.in +EXTRA_DIST = \ + apollolake.x.in \ + boot_ldr.x.in

noinst_LIBRARIES = libplatform.a

@@ -19,7 +21,7 @@ libplatform_a_CFLAGS = \ $(SOF_INCDIR) \ $(PLATFORM_INCDIR)

-noinst_PROGRAMS = module +noinst_PROGRAMS = module boot_module

module_SOURCES = \ base_module.c @@ -28,3 +30,11 @@ module_CFLAGS = \ $(ARCH_INCDIR) \ $(SOF_INCDIR) \ $(PLATFORM_INCDIR) + +boot_module_SOURCES = \ + boot_module.c + +boot_module_CFLAGS = \ + $(ARCH_INCDIR) \ + $(SOF_INCDIR) \ + $(PLATFORM_INCDIR) \ No newline at end of file diff --git a/src/platform/apollolake/apollolake.x.in b/src/platform/apollolake/apollolake.x.in index 76fbeb7..5802cc5 100644 --- a/src/platform/apollolake/apollolake.x.in +++ b/src/platform/apollolake/apollolake.x.in @@ -14,12 +14,6 @@ OUTPUT_ARCH(xtensa)

MEMORY { - vector_reset_text : - org = XCHAL_RESET_VECTOR0_PADDR, - len = SOF_MEM_RESET_TEXT_SIZE - vector_reset_lit : - org = XCHAL_RESET_VECTOR0_PADDR + SOF_MEM_RESET_TEXT_SIZE, - len = SOF_MEM_RESET_LIT_SIZE vector_memory_lit : org = XCHAL_MEMERROR_VECTOR_PADDR + SOF_MEM_ERROR_LIT_SIZE, len = SOF_MEM_ERROR_LIT_SIZE @@ -27,65 +21,62 @@ MEMORY org = XCHAL_MEMERROR_VECTOR_PADDR, len = SOF_MEM_ERROR_TEXT_SIZE vector_base_text : - org = XCHAL_VECBASE_RESET_PADDR, + org = SOF_MEM_VECBASE, len = SOF_MEM_VECBASE_LIT_SIZE vector_int2_lit : - org = XCHAL_INTLEVEL2_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE, + org = SOF_MEM_VECBASE + XCHAL_INTLEVEL2_VECOFS - SOF_MEM_VECT_LIT_SIZE, len = SOF_MEM_VECT_LIT_SIZE vector_int2_text : - org = XCHAL_INTLEVEL2_VECTOR_PADDR, + org = SOF_MEM_VECBASE + XCHAL_INTLEVEL2_VECOFS, len = SOF_MEM_VECT_TEXT_SIZE vector_int3_lit : - org = XCHAL_INTLEVEL3_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE, + org = SOF_MEM_VECBASE + XCHAL_INTLEVEL3_VECOFS - SOF_MEM_VECT_LIT_SIZE, len = SOF_MEM_VECT_LIT_SIZE vector_int3_text : - org = XCHAL_INTLEVEL3_VECTOR_PADDR, + org = SOF_MEM_VECBASE + XCHAL_INTLEVEL3_VECOFS, len = SOF_MEM_VECT_TEXT_SIZE vector_int4_lit : - org = XCHAL_INTLEVEL4_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE, + org = SOF_MEM_VECBASE + XCHAL_INTLEVEL4_VECOFS - SOF_MEM_VECT_LIT_SIZE, len = SOF_MEM_VECT_LIT_SIZE vector_int4_text : - org = XCHAL_INTLEVEL4_VECTOR_PADDR, + org = SOF_MEM_VECBASE + XCHAL_INTLEVEL4_VECOFS, len = SOF_MEM_VECT_TEXT_SIZE vector_int5_lit : - org = XCHAL_INTLEVEL5_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE, + org = SOF_MEM_VECBASE + XCHAL_INTLEVEL5_VECOFS - SOF_MEM_VECT_LIT_SIZE, len = SOF_MEM_VECT_LIT_SIZE vector_int5_text : - org = XCHAL_INTLEVEL5_VECTOR_PADDR, + org = SOF_MEM_VECBASE + XCHAL_INTLEVEL5_VECOFS, len = SOF_MEM_VECT_TEXT_SIZE vector_int6_lit : - org = XCHAL_INTLEVEL6_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE, + org = SOF_MEM_VECBASE + XCHAL_INTLEVEL6_VECOFS - SOF_MEM_VECT_LIT_SIZE, len = SOF_MEM_VECT_LIT_SIZE vector_int6_text : - org = XCHAL_INTLEVEL6_VECTOR_PADDR, + org = SOF_MEM_VECBASE + XCHAL_INTLEVEL6_VECOFS, len = SOF_MEM_VECT_TEXT_SIZE vector_int7_lit : - org = XCHAL_INTLEVEL7_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE, + org = SOF_MEM_VECBASE + XCHAL_INTLEVEL7_VECOFS - SOF_MEM_VECT_LIT_SIZE, len = SOF_MEM_VECT_LIT_SIZE vector_int7_text : - org = XCHAL_INTLEVEL7_VECTOR_PADDR, + org = SOF_MEM_VECBASE + XCHAL_INTLEVEL7_VECOFS, len = SOF_MEM_VECT_TEXT_SIZE vector_kernel_lit : - org = XCHAL_KERNEL_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE, + org = SOF_MEM_VECBASE + XCHAL_KERNEL_VECOFS - SOF_MEM_VECT_LIT_SIZE, len = SOF_MEM_VECT_LIT_SIZE vector_kernel_text : - org = XCHAL_KERNEL_VECTOR_PADDR, + org = SOF_MEM_VECBASE + XCHAL_KERNEL_VECOFS, len = SOF_MEM_VECT_TEXT_SIZE vector_user_lit : - org = XCHAL_USER_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE, + org = SOF_MEM_VECBASE + XCHAL_USER_VECOFS - SOF_MEM_VECT_LIT_SIZE, len = SOF_MEM_VECT_LIT_SIZE vector_user_text : - org = XCHAL_USER_VECTOR_PADDR, + org = SOF_MEM_VECBASE + XCHAL_USER_VECOFS, len = SOF_MEM_VECT_TEXT_SIZE vector_double_lit : - org = XCHAL_DOUBLEEXC_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE, + org = SOF_MEM_VECBASE + XCHAL_DOUBLEEXC_VECOFS - SOF_MEM_VECT_LIT_SIZE, len = SOF_MEM_VECT_LIT_SIZE vector_double_text : - org = XCHAL_DOUBLEEXC_VECTOR_PADDR, + org = SOF_MEM_VECBASE + XCHAL_DOUBLEEXC_VECOFS, len = SOF_MEM_VECT_TEXT_SIZE - sof_text_start : - org = SOF_TEXT_START, - len = SOF_TEXT_START_SIZE, sof_text : org = SOF_TEXT_BASE, len = SOF_TEXT_SIZE, @@ -107,6 +98,21 @@ MEMORY sof_stack : org = SOF_STACK_END, len = SOF_STACK_BASE - SOF_STACK_END + buffer_hp_heap : + org = HEAP_HP_BUFFER_BASE, + len = HEAP_HP_BUFFER_SIZE + wnd0 : + org = HP_SRAM_WIN0_BASE, + len = HP_SRAM_WIN0_SIZE + wnd1 : + org = HP_SRAM_WIN1_BASE, + len = HP_SRAM_WIN1_SIZE + wnd2 : + org = HP_SRAM_WIN2_BASE, + len = HP_SRAM_WIN2_SIZE + wnd3 : + org = HP_SRAM_WIN3_BASE, + len = HP_SRAM_WIN3_SIZE }

PHDRS @@ -134,7 +140,6 @@ PHDRS vector_user_text_phdr PT_LOAD; vector_double_lit_phdr PT_LOAD; vector_double_text_phdr PT_LOAD; - sof_text_start_phdr PT_LOAD; sof_text_phdr PT_LOAD; sof_data_phdr PT_LOAD; sof_bss_data_phdr PT_LOAD; @@ -142,10 +147,15 @@ PHDRS runtime_heap_phdr PT_LOAD; buffer_heap_phdr PT_LOAD; sof_stack_phdr PT_LOAD; + buffer_hp_heap_phdr PT_LOAD; + wnd0_phdr PT_LOAD; + wnd1_phdr PT_LOAD; + wnd2_phdr PT_LOAD; + wnd3_phdr PT_LOAD; }

/* Default entry point: */ -ENTRY(_ResetVector) +ENTRY(_MainEntry) _rom_store_table = 0;

/* ABI0 does not use Window base */ @@ -171,20 +181,6 @@ PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wbna_trapnull);

SECTIONS { - .ResetVector.text : ALIGN(4) - { - _ResetVector_text_start = ABSOLUTE(.); - KEEP (*(.ResetVector.text)) - _ResetVector_text_end = ABSOLUTE(.); - } >vector_reset_text :vector_reset_text_phdr - - .ResetVector.literal : ALIGN(4) - { - _ResetVector_literal_start = ABSOLUTE(.); - *(.ResetVector.literal) - _ResetVector_literal_end = ABSOLUTE(.); - } >vector_reset_lit :vector_reset_lit_phdr - .MemoryExceptionVector.literal : ALIGN(4) { _MemoryExceptionVector_literal_start = ABSOLUTE(.); @@ -199,6 +195,46 @@ SECTIONS _MemoryExceptionVector_text_end = ABSOLUTE(.); } >vector_memory_text :vector_memory_text_phdr

+ .buffer_hp_heap (NOLOAD) : ALIGN(8) + { + . = ALIGN (32); + _buffer_hp_heap_start = ABSOLUTE(.); + . = . + HEAP_HP_BUFFER_SIZE; + _buffer_hp_heap_end = ABSOLUTE(.); + } >buffer_hp_heap :buffer_hp_heap_phdr + + .wnd0 (NOLOAD) : ALIGN(8) + { + . = ALIGN (32); + _wnd0_start = ABSOLUTE(.); + . = . + HP_SRAM_WIN0_SIZE; + _wnd0_end = ABSOLUTE(.); + } >wnd0 :wnd0_phdr + + .wnd1 (NOLOAD) : ALIGN(8) + { + . = ALIGN (32); + _wnd1_start = ABSOLUTE(.); + . = . + HP_SRAM_WIN1_SIZE; + _wnd1_end = ABSOLUTE(.); + } >wnd1 :wnd1_phdr + + .wnd2 (NOLOAD) : ALIGN(8) + { + . = ALIGN (32); + _wnd2_start = ABSOLUTE(.); + . = . + HP_SRAM_WIN2_SIZE; + _wnd2_end = ABSOLUTE(.); + } >wnd2 :wnd2_phdr + + .wnd3 (NOLOAD) : ALIGN(8) + { + . = ALIGN (32); + _wnd3_start = ABSOLUTE(.); + . = . + HP_SRAM_WIN3_SIZE; + _wnd3_end = ABSOLUTE(.); + } >wnd3 :wnd3_phdr + .WindowVectors.text : ALIGN(4) { _WindowVectors_text_start = ABSOLUTE(.); @@ -332,17 +368,11 @@ SECTIONS _DoubleExceptionVector_text_end = ABSOLUTE(.); } >vector_double_text :vector_double_text_phdr

- .ResetHandler.text : ALIGN(4) - { - _ResetHandler_text_start = ABSOLUTE(.); - KEEP (*(.ResetHandler.text)) - _ResetHandler_text_end = ABSOLUTE(.); - } >sof_text_start :sof_text_start_phdr - .text : ALIGN(4) { _stext = .; _text_start = ABSOLUTE(.); + KEEP (*(.MainEntry.text)) *(.entry.text) *(.init.literal) KEEP(*(.init)) @@ -539,4 +569,5 @@ SECTIONS . = . + SOF_STACK_SIZE; _sof_stack_end = ABSOLUTE(.); } >sof_stack :sof_stack_phdr + } diff --git a/src/platform/apollolake/boot_ldr.x.in b/src/platform/apollolake/boot_ldr.x.in new file mode 100644 index 0000000..7465f9f --- /dev/null +++ b/src/platform/apollolake/boot_ldr.x.in @@ -0,0 +1,236 @@ +/* + * Linker Script for Apollolake Bootloader. + * + * This script is run through the GNU C preprocessor to align the memory + * offsets with headers. + * + * Use spaces for formatting as cpp ignore tab sizes. + */ + +#include <platform/memory.h> +#include <xtensa/config/core-isa.h> + +OUTPUT_ARCH(xtensa) + +MEMORY +{ + boot_entry_text : + org = IMR_BOOT_LDR_TEXT_ENTRY_BASE, + len = IMR_BOOT_LDR_TEXT_ENTRY_SIZE + boot_entry_lit : + org = IMR_BOOT_LDR_LIT_BASE, + len = IMR_BOOT_LDR_LIT_SIZE + sof_text : + org = IMR_BOOT_LDR_TEXT_BASE, + len = IMR_BOOT_LDR_TEXT_SIZE, + sof_data : + org = IMR_BOOT_LDR_DATA_BASE, + len = IMR_BOOT_LDR_DATA_SIZE + sof_bss_data : + org = IMR_BOOT_LDR_BSS_BASE, + len = IMR_BOOT_LDR_BSS_SIZE + sof_stack : + org = SOF_STACK_END, + len = SOF_STACK_BASE - SOF_STACK_END + wnd0 : + org = HP_SRAM_WIN0_BASE, + len = HP_SRAM_WIN0_SIZE +} + +PHDRS +{ + boot_entry_text_phdr PT_LOAD; + boot_entry_lit_phdr PT_LOAD; + sof_text_phdr PT_LOAD; + sof_data_phdr PT_LOAD; + sof_bss_data_phdr PT_LOAD; + sof_stack_phdr PT_LOAD; + wnd0_phdr PT_LOAD; +} + +/* Default entry point: */ +ENTRY(boot_entry) +EXTERN(reset_vector) + +SECTIONS +{ + .boot_entry.text : ALIGN(4) + { + _boot_entry_text_start = ABSOLUTE(.); + KEEP (*(.boot_entry.text)) + _boot_entry_text_end = ABSOLUTE(.); + } >boot_entry_text :boot_entry_text_phdr + + .boot_entry.literal : ALIGN(4) + { + _boot_entry_literal_start = ABSOLUTE(.); + *(.boot_entry.literal) + *(.literal .literal.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + _boot_entry_literal_end = ABSOLUTE(.); + } >boot_entry_lit :boot_entry_lit_phdr + + .text : ALIGN(4) + { + _stext = .; + _text_start = ABSOLUTE(.); + *(.entry.text) + *(.init.literal) + KEEP(*(.init)) + *( .text .text.*) + *(.fini.literal) + KEEP(*(.fini)) + *(.gnu.version) + KEEP (*(.ResetVector.text)) + KEEP (*(.ResetHandler.text)) + _text_end = ABSOLUTE(.); + _etext = .; + } >sof_text :sof_text_phdr + + .rodata : ALIGN(4) + { + _rodata_start = ABSOLUTE(.); + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r.*) + *(.rodata1) + __XT_EXCEPTION_TABLE__ = ABSOLUTE(.); + KEEP (*(.xt_except_table)) + KEEP (*(.gcc_except_table)) + *(.gnu.linkonce.e.*) + *(.gnu.version_r) + KEEP (*(.eh_frame)) + /* C++ constructor and destructor tables, properly ordered: */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + /* C++ exception handlers table: */ + __XT_EXCEPTION_DESCS__ = ABSOLUTE(.); + *(.xt_except_desc) + *(.gnu.linkonce.h.*) + __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); + *(.xt_except_desc_end) + *(.dynamic) + *(.gnu.version_d) + . = ALIGN(4); /* this table MUST be 4-byte aligned */ + _bss_table_start = ABSOLUTE(.); + LONG(_bss_start) + LONG(_bss_end) + _bss_table_end = ABSOLUTE(.); + _rodata_end = ABSOLUTE(.); + } >sof_data :sof_data_phdr + + .data : ALIGN(4) + { + _data_start = ABSOLUTE(.); + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + KEEP(*(.gnu.linkonce.d.*personality*)) + *(.data1) + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + KEEP(*(.jcr)) + _data_end = ABSOLUTE(.); + } >sof_data :sof_data_phdr + + .lit4 : ALIGN(4) + { + _lit4_start = ABSOLUTE(.); + *(*.lit4) + *(.lit4.*) + *(.gnu.linkonce.lit4.*) + _lit4_end = ABSOLUTE(.); + } >sof_data :sof_data_phdr + + .bss (NOLOAD) : ALIGN(8) + { + . = ALIGN (8); + _bss_start = ABSOLUTE(.); + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN (8); + _bss_end = ABSOLUTE(.); + } >sof_bss_data :sof_bss_data_phdr + + _man = 0x1234567; + + PROVIDE(_memmap_vecbase_reset = HP_SRAM_VECBASE_RESET); + + _memmap_cacheattr_wbna_trapnull = 0xFF42FFF2; + PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wbna_trapnull); + + __stack = SOF_STACK_BASE; + __wnd0 = HP_SRAM_WIN0_BASE; + __wnd0_size = HP_SRAM_WIN0_SIZE; + + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_info 0 : { *(.debug_info) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + .xt.insn 0 : + { + KEEP (*(.xt.insn)) + KEEP (*(.gnu.linkonce.x.*)) + } + .xt.prop 0 : + { + KEEP (*(.xt.prop)) + KEEP (*(.xt.prop.*)) + KEEP (*(.gnu.linkonce.prop.*)) + } + .xt.lit 0 : + { + KEEP (*(.xt.lit)) + KEEP (*(.xt.lit.*)) + KEEP (*(.gnu.linkonce.p.*)) + } + .xt.profile_range 0 : + { + KEEP (*(.xt.profile_range)) + KEEP (*(.gnu.linkonce.profile_range.*)) + } + .xt.profile_ranges 0 : + { + KEEP (*(.xt.profile_ranges)) + KEEP (*(.gnu.linkonce.xt.profile_ranges.*)) + } + .xt.profile_files 0 : + { + KEEP (*(.xt.profile_files)) + KEEP (*(.gnu.linkonce.xt.profile_files.*)) + } +} diff --git a/src/platform/apollolake/boot_module.c b/src/platform/apollolake/boot_module.c new file mode 100644 index 0000000..a4dfe1e --- /dev/null +++ b/src/platform/apollolake/boot_module.c @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2018, Intel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Intel Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Author: Marcin Maka marcin.maka@linux.intel.com + */ + +#include <uapi/manifest.h> +#include <platform/memory.h> + +/* + * Each module has an entry in the FW manifest header. This is NOT part of + * the SOF executable image but is inserted by object copy as a ELF section + * for parsing by rimage (to generate the manifest). + */ +struct sof_man_module_manifest apl_bootldr_manifest = { + .module = { + .name = "BRNGUP", + .uuid = {0xcc, 0x48, 0x7b, 0x0d, 0xa9, 0x1e, 0x0a, 0x47, + 0xa8, 0xc1, 0x53, 0x34, 0x24, 0x52, 0x8a, 0x17}, + .entry_point = IMR_BOOT_LDR_TEXT_ENTRY_BASE, + .type = { + .load_type = SOF_MAN_MOD_TYPE_MODULE, + .domain_ll = 1, + }, + .affinity_mask = 3, + }, +}; + +/* not used, but stops linker complaining */ +int _start; diff --git a/src/platform/apollolake/include/Makefile.am b/src/platform/apollolake/include/Makefile.am index 19f40eb..c5113a4 100644 --- a/src/platform/apollolake/include/Makefile.am +++ b/src/platform/apollolake/include/Makefile.am @@ -1 +1 @@ -SUBDIRS = platform xtensa +SUBDIRS = arch platform diff --git a/src/platform/apollolake/include/arch/Makefile.am b/src/platform/apollolake/include/arch/Makefile.am new file mode 100644 index 0000000..63616bf --- /dev/null +++ b/src/platform/apollolake/include/arch/Makefile.am @@ -0,0 +1 @@ +SUBDIRS = xtensa diff --git a/src/platform/apollolake/include/xtensa/Makefile.am b/src/platform/apollolake/include/arch/xtensa/Makefile.am similarity index 100% rename from src/platform/apollolake/include/xtensa/Makefile.am rename to src/platform/apollolake/include/arch/xtensa/Makefile.am diff --git a/src/platform/apollolake/include/xtensa/config/Makefile.am b/src/platform/apollolake/include/arch/xtensa/config/Makefile.am similarity index 100% rename from src/platform/apollolake/include/xtensa/config/Makefile.am rename to src/platform/apollolake/include/arch/xtensa/config/Makefile.am diff --git a/src/platform/apollolake/include/xtensa/config/core-isa.h b/src/platform/apollolake/include/arch/xtensa/config/core-isa.h similarity index 95% rename from src/platform/apollolake/include/xtensa/config/core-isa.h rename to src/platform/apollolake/include/arch/xtensa/config/core-isa.h index 5768437..eedbd1c 100644 --- a/src/platform/apollolake/include/xtensa/config/core-isa.h +++ b/src/platform/apollolake/include/arch/xtensa/config/core-isa.h @@ -28,6 +28,8 @@ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */

+#if !defined __XCC__ + #ifndef _XTENSA_CORE_CONFIGURATION_H #define _XTENSA_CORE_CONFIGURATION_H

@@ -488,8 +490,8 @@ #define XCHAL_HAVE_MEM_ECC_PARITY 1 /* local memory ECC/parity */ #define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */ #define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */ -#define XCHAL_VECBASE_RESET_VADDR 0xa000a400 /* VECBASE reset value */ -#define XCHAL_VECBASE_RESET_PADDR 0xa000a400 +#define XCHAL_VECBASE_RESET_VADDR 0xBEFE0800 /* VECBASE reset value */ +#define XCHAL_VECBASE_RESET_PADDR 0xBEFE0800 #define XCHAL_RESET_VECBASE_OVERLAP 0

#define XCHAL_RESET_VECTOR0_VADDR 0xBEFE0000 @@ -498,50 +500,50 @@ #define XCHAL_RESET_VECTOR1_PADDR 0xBE800000 #define XCHAL_RESET_VECTOR_VADDR 0xBEFE0000 #define XCHAL_RESET_VECTOR_PADDR 0xBEFE0000 -#define XCHAL_MEMERROR_VECTOR0_VADDR 0xbefe0270 -#define XCHAL_MEMERROR_VECTOR0_PADDR 0xbefe0270 +#define XCHAL_MEMERROR_VECTOR0_VADDR 0xBEFE0400 +#define XCHAL_MEMERROR_VECTOR0_PADDR 0xBEFE0400 #define XCHAL_MEMERROR_VECTOR1_VADDR 0xBE800400 #define XCHAL_MEMERROR_VECTOR1_PADDR 0xBE800400 -#define XCHAL_MEMERROR_VECTOR_VADDR 0xbefe0270 -#define XCHAL_MEMERROR_VECTOR_PADDR 0xbefe0270 +#define XCHAL_MEMERROR_VECTOR_VADDR 0xBEFE0400 +#define XCHAL_MEMERROR_VECTOR_PADDR 0xBEFE0400 #define XCHAL_USER_VECOFS 0x00000340 -#define XCHAL_USER_VECTOR_VADDR 0xa000a740 -#define XCHAL_USER_VECTOR_PADDR 0xa000a740 +#define XCHAL_USER_VECTOR_VADDR 0xBEFE0B40 +#define XCHAL_USER_VECTOR_PADDR 0xBEFE0B40 #define XCHAL_KERNEL_VECOFS 0x00000300 -#define XCHAL_KERNEL_VECTOR_VADDR 0xa000a700 -#define XCHAL_KERNEL_VECTOR_PADDR 0xa000a700 +#define XCHAL_KERNEL_VECTOR_VADDR 0xBEFE0B00 +#define XCHAL_KERNEL_VECTOR_PADDR 0xBEFE0B00 #define XCHAL_DOUBLEEXC_VECOFS 0x000003C0 -#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0xa000a7c0 -#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0xa000a7c0 +#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0xBEFE0BC0 +#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0xBEFE0BC0 #define XCHAL_WINDOW_OF4_VECOFS 0x00000000 #define XCHAL_WINDOW_UF4_VECOFS 0x00000040 #define XCHAL_WINDOW_OF8_VECOFS 0x00000080 #define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 #define XCHAL_WINDOW_OF12_VECOFS 0x00000100 #define XCHAL_WINDOW_UF12_VECOFS 0x00000140 -#define XCHAL_WINDOW_VECTORS_VADDR 0xa000a400 -#define XCHAL_WINDOW_VECTORS_PADDR 0xa000a400 +#define XCHAL_WINDOW_VECTORS_VADDR 0xBEFE0800 +#define XCHAL_WINDOW_VECTORS_PADDR 0xBEFE0800 #define XCHAL_INTLEVEL2_VECOFS 0x00000180 -#define XCHAL_INTLEVEL2_VECTOR_VADDR 0xa000a580 -#define XCHAL_INTLEVEL2_VECTOR_PADDR 0xa000a580 +#define XCHAL_INTLEVEL2_VECTOR_VADDR 0xBEFE0980 +#define XCHAL_INTLEVEL2_VECTOR_PADDR 0xBEFE0980 #define XCHAL_INTLEVEL3_VECOFS 0x000001C0 -#define XCHAL_INTLEVEL3_VECTOR_VADDR 0xa000a5c0 -#define XCHAL_INTLEVEL3_VECTOR_PADDR 0xa000a5c0 +#define XCHAL_INTLEVEL3_VECTOR_VADDR 0xBEFE09C0 +#define XCHAL_INTLEVEL3_VECTOR_PADDR 0xBEFE09C0 #define XCHAL_INTLEVEL4_VECOFS 0x00000200 -#define XCHAL_INTLEVEL4_VECTOR_VADDR 0xa000a600 -#define XCHAL_INTLEVEL4_VECTOR_PADDR 0xa000a600 +#define XCHAL_INTLEVEL4_VECTOR_VADDR 0xBEFE0A00 +#define XCHAL_INTLEVEL4_VECTOR_PADDR 0xBEFE0A00 #define XCHAL_INTLEVEL5_VECOFS 0x00000240 -#define XCHAL_INTLEVEL5_VECTOR_VADDR 0xa000a640 -#define XCHAL_INTLEVEL5_VECTOR_PADDR 0xa000a640 +#define XCHAL_INTLEVEL5_VECTOR_VADDR 0xBEFE0A40 +#define XCHAL_INTLEVEL5_VECTOR_PADDR 0xBEFE0A40 #define XCHAL_INTLEVEL6_VECOFS 0x00000280 -#define XCHAL_INTLEVEL6_VECTOR_VADDR 0xa000a680 -#define XCHAL_INTLEVEL6_VECTOR_PADDR 0xa000a680 +#define XCHAL_INTLEVEL6_VECTOR_VADDR 0xBEFE0A80 +#define XCHAL_INTLEVEL6_VECTOR_PADDR 0xBEFE0A80 #define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS #define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR #define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR #define XCHAL_NMI_VECOFS 0x000002C0 -#define XCHAL_NMI_VECTOR_VADDR 0xa000a6c0 -#define XCHAL_NMI_VECTOR_PADDR 0xa000a6c0 +#define XCHAL_NMI_VECTOR_VADDR 0xBEFE0AC0 +#define XCHAL_NMI_VECTOR_PADDR 0xBEFE0AC0 #define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS #define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR #define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR @@ -600,3 +602,9 @@

#endif /* _XTENSA_CORE_CONFIGURATION_H */ + +#else + +#error "xcc should not use this header" + +#endif /* __XCC__ */ diff --git a/src/platform/cannonlake/include/xtensa/config/core-matmap.h b/src/platform/apollolake/include/arch/xtensa/config/core-matmap.h similarity index 99% rename from src/platform/cannonlake/include/xtensa/config/core-matmap.h rename to src/platform/apollolake/include/arch/xtensa/config/core-matmap.h index c4f479a..ad0f0d7 100644 --- a/src/platform/cannonlake/include/xtensa/config/core-matmap.h +++ b/src/platform/apollolake/include/arch/xtensa/config/core-matmap.h @@ -43,6 +43,7 @@ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */

+#if !defined __XCC__

#ifndef XTENSA_CONFIG_CORE_MATMAP_H #define XTENSA_CONFIG_CORE_MATMAP_H @@ -311,3 +312,9 @@

#endif /*XTENSA_CONFIG_CORE_MATMAP_H*/ + +#else + +#error "xcc should not use this header" + +#endif /* __XCC__ */ diff --git a/src/platform/cannonlake/include/xtensa/config/defs.h b/src/platform/apollolake/include/arch/xtensa/config/defs.h similarity index 94% rename from src/platform/cannonlake/include/xtensa/config/defs.h rename to src/platform/apollolake/include/arch/xtensa/config/defs.h index b695e59..c2ef1d9 100644 --- a/src/platform/cannonlake/include/xtensa/config/defs.h +++ b/src/platform/apollolake/include/arch/xtensa/config/defs.h @@ -25,6 +25,8 @@ and earlier Xtensa releases. It includes only a subset of the available header files. */

+#if !defined __XCC__ + #ifndef _XTENSA_BASE_HEADER #define _XTENSA_BASE_HEADER

@@ -36,3 +38,9 @@

#endif /* __XTENSA__ */ #endif /* !_XTENSA_BASE_HEADER */ + +#else + +#error "xcc should not use this header" + +#endif /* __XCC__ */ diff --git a/src/platform/cannonlake/include/xtensa/config/specreg.h b/src/platform/apollolake/include/arch/xtensa/config/specreg.h similarity index 96% rename from src/platform/cannonlake/include/xtensa/config/specreg.h rename to src/platform/apollolake/include/arch/xtensa/config/specreg.h index 96bfa94..c99cda6 100644 --- a/src/platform/cannonlake/include/xtensa/config/specreg.h +++ b/src/platform/apollolake/include/arch/xtensa/config/specreg.h @@ -25,6 +25,8 @@ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */

+#if !defined __XCC__ + #ifndef XTENSA_SPECREG_H #define XTENSA_SPECREG_H

@@ -104,3 +106,9 @@ #define INTCLEAR 227

#endif /* XTENSA_SPECREG_H */ + +#else + +#error "xcc should not use this header" + +#endif /* __XCC__ */ diff --git a/src/platform/apollolake/include/xtensa/config/system.h b/src/platform/apollolake/include/arch/xtensa/config/system.h similarity index 99% rename from src/platform/apollolake/include/xtensa/config/system.h rename to src/platform/apollolake/include/arch/xtensa/config/system.h index aad1d8c..f1fd8a0 100644 --- a/src/platform/apollolake/include/xtensa/config/system.h +++ b/src/platform/apollolake/include/arch/xtensa/config/system.h @@ -31,6 +31,7 @@ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */

+#if !defined __XCC__

#ifndef XTENSA_CONFIG_SYSTEM_H #define XTENSA_CONFIG_SYSTEM_H @@ -269,3 +270,9 @@

#endif /*XTENSA_CONFIG_SYSTEM_H*/ + +#else + +#error "xcc should not use this header" + +#endif /* __XCC__ */ diff --git a/src/platform/apollolake/include/xtensa/config/tie-asm.h b/src/platform/apollolake/include/arch/xtensa/config/tie-asm.h similarity index 99% rename from src/platform/apollolake/include/xtensa/config/tie-asm.h rename to src/platform/apollolake/include/arch/xtensa/config/tie-asm.h index 15f6e89..706545a 100644 --- a/src/platform/apollolake/include/xtensa/config/tie-asm.h +++ b/src/platform/apollolake/include/arch/xtensa/config/tie-asm.h @@ -29,6 +29,8 @@ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */

+#if !defined __XCC__ + #ifndef _XTENSA_CORE_TIE_ASM_H #define _XTENSA_CORE_TIE_ASM_H

@@ -237,3 +239,9 @@ .macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm

#endif /*_XTENSA_CORE_TIE_ASM_H*/ + +#else + +#error "xcc should not use this header" + +#endif /* __XCC__ */ diff --git a/src/platform/cannonlake/include/xtensa/config/tie.h b/src/platform/apollolake/include/arch/xtensa/config/tie.h similarity index 98% rename from src/platform/cannonlake/include/xtensa/config/tie.h rename to src/platform/apollolake/include/arch/xtensa/config/tie.h index d47e427..b5fd4c9 100644 --- a/src/platform/cannonlake/include/xtensa/config/tie.h +++ b/src/platform/apollolake/include/arch/xtensa/config/tie.h @@ -29,6 +29,8 @@ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */

+#if !defined __XCC__ + #ifndef _XTENSA_CORE_TIE_H #define _XTENSA_CORE_TIE_H

@@ -167,3 +169,9 @@ 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8

#endif /*_XTENSA_CORE_TIE_H*/ + +#else + +#error "xcc should not use this header" + +#endif /* __XCC__ */ diff --git a/src/platform/apollolake/include/platform/memory.h b/src/platform/apollolake/include/platform/memory.h index e7f3ee3..1825f34 100644 --- a/src/platform/apollolake/include/platform/memory.h +++ b/src/platform/apollolake/include/platform/memory.h @@ -1,4 +1,3 @@ - /* * Copyright (c) 2016, Intel Corporation * All rights reserved. @@ -127,29 +126,7 @@ #define ROM_BASE 0xBEFE0000 #define ROM_SIZE 0x00002000

-/* - * The L2 SRAM Heap and Stack on Apololake are organised like this :- - * - * +--------------------------------------------------------------------------+ - * | Offset | Region | Size | - * +---------------------+----------------+-----------------------------------+ - * | L2_SRAM_BASE | RO Data | SOF_DATA_SIZE | - * | | Data | | - * | | BSS | | - * +---------------------+----------------+-----------------------------------+ - * | HEAP_SYSTEM_BASE | System Heap | HEAP_SYSTEM_SIZE | - * +---------------------+----------------+-----------------------------------+ - * | HEAP_RUNTIME_BASE | Runtime Heap | HEAP_RUNTIME_SIZE | - * +---------------------+----------------+-----------------------------------+ - * | HEAP_BUFFER_BASE | Module Buffers | HEAP_BUFFER_SIZE | - * +---------------------+----------------+-----------------------------------+ - * | SOF_STACK_END | Stack | SOF_STACK_SIZE | - * +---------------------+----------------+-----------------------------------+ - * | SOF_STACK_BASE | | | - * +---------------------+----------------+-----------------------------------+ - */ - -/* L2 SRAM */ +/* IMR accessible via L2$ */ #define L2_SRAM_BASE 0xA000A000 #define L2_SRAM_SIZE 0x00056000

@@ -163,29 +140,13 @@ #define HEAP_RT_COUNT512 8 #define HEAP_RT_COUNT1024 4

-/* text and data share the same L2 SRAM on Broxton */ -#define SOF_TEXT_START L2_SRAM_BASE -#define SOF_TEXT_START_SIZE 0x400 #define L2_VECTOR_SIZE 0x1000

-#define SOF_TEXT_BASE (L2_SRAM_BASE + L2_VECTOR_SIZE) -#define SOF_TEXT_SIZE 0x19000 - -/* initialized data */ -#if defined CONFIG_DMIC -#define SOF_DATA_SIZE 0x1a000 -#else -#define SOF_DATA_SIZE 0x19000 -#endif - -/* bss data */ -#define SOF_BSS_DATA_SIZE 0x2800 - /* Heap configuration */ #define HEAP_SYSTEM_BASE \ (SOF_TEXT_BASE + SOF_TEXT_SIZE +\ SOF_DATA_SIZE + SOF_BSS_DATA_SIZE) -#define HEAP_SYSTEM_SIZE 0x5000 +#define HEAP_SYSTEM_SIZE 0x3200

#define HEAP_RUNTIME_BASE (HEAP_SYSTEM_BASE + HEAP_SYSTEM_SIZE) #define HEAP_RUNTIME_SIZE \ @@ -203,11 +164,6 @@ #define HEAP_BUFFER_COUNT (HEAP_BUFFER_SIZE / HEAP_BUFFER_BLOCK_SIZE)

-/* Stack configuration */ -#define SOF_STACK_SIZE 0x1000 -#define SOF_STACK_BASE (L2_SRAM_BASE + L2_SRAM_SIZE) -#define SOF_STACK_END (SOF_STACK_BASE - SOF_STACK_SIZE) - /* * The HP SRAM Region Apololake is organised like this :- * +--------------------------------------------------------------------------+ @@ -232,8 +188,17 @@ */

/* HP SRAM */ +#define SRAM_ALIAS_OFFSET 0x20000000 #define HP_SRAM_BASE 0xBE000000 -#define HP_SRAM_SIZE 0x00020000 +#define HP_SRAM_SIZE 0x00080000 + +/* HP SRAM Heap */ +#define HEAP_HP_BUFFER_BASE HP_SRAM_BASE +#define HEAP_HP_BUFFER_SIZE 0x8000 + +#define HEAP_HP_BUFFER_BLOCK_SIZE 0x180 +#define HEAP_HP_BUFFER_COUNT \ + (HEAP_HP_BUFFER_SIZE / HEAP_HP_BUFFER_BLOCK_SIZE)

/* HP SRAM windows */

@@ -278,21 +243,22 @@ #define HP_SRAM_WIN3_BASE SRAM_TRACE_BASE #define HP_SRAM_WIN3_SIZE SRAM_TRACE_SIZE

-/* HP SRAM Heap */ -#define HEAP_HP_BUFFER_BASE HP_SRAM_BASE -#define HEAP_HP_BUFFER_SIZE \ - (HP_SRAM_SIZE - \ - SRAM_TRACE_SIZE - \ - SRAM_DEBUG_SIZE - \ - SRAM_EXCEPT_SIZE - \ - SRAM_STREAM_SIZE - \ - SRAM_INBOX_SIZE - \ - SRAM_OUTBOX_SIZE - \ - SRAM_SW_REG_SIZE) +#define HP_SRAM_VECBASE_RESET (HP_SRAM_WIN0_BASE + HP_SRAM_WIN0_SIZE)

-#define HEAP_HP_BUFFER_BLOCK_SIZE 0x180 -#define HEAP_HP_BUFFER_COUNT \ - (HEAP_HP_BUFFER_SIZE / HEAP_HP_BUFFER_BLOCK_SIZE) +#define SOF_TEXT_START (HP_SRAM_VECBASE_RESET + 0x400) +#define SOF_TEXT_BASE (SOF_TEXT_START) +#define SOF_TEXT_SIZE (0x19000 - 0x400) + +/* initialized data */ +#define SOF_DATA_SIZE 0x18000 + +/* bss data */ +#define SOF_BSS_DATA_SIZE 0x2800 + +/* Stack configuration */ +#define SOF_STACK_SIZE 0x1000 +#define SOF_STACK_BASE (HP_SRAM_BASE + HP_SRAM_SIZE) +#define SOF_STACK_END (SOF_STACK_BASE - SOF_STACK_SIZE)

/* * The LP SRAM Heap and Stack on Apollolake are organised like this :- @@ -369,9 +335,29 @@ #define SOF_MEM_ERROR_TEXT_SIZE 0x180 #define SOF_MEM_ERROR_LIT_SIZE 0x8

-#define SOF_MEM_RESET_TEXT_SIZE 0x268 -#define SOF_MEM_RESET_LIT_SIZE 0x8 +#define SOF_MEM_VECBASE HP_SRAM_VECBASE_RESET #define SOF_MEM_VECBASE_LIT_SIZE 0x178

#define SOF_MEM_RO_SIZE 0x8 + +/* boot loader in IMR */ +#define IMR_BOOT_LDR_TEXT_ENTRY_BASE 0xB000A000 +#define IMR_BOOT_LDR_TEXT_ENTRY_SIZE 0x66 +#define IMR_BOOT_LDR_LIT_BASE (IMR_BOOT_LDR_TEXT_ENTRY_BASE + \ + IMR_BOOT_LDR_TEXT_ENTRY_SIZE) +#define IMR_BOOT_LDR_LIT_SIZE 0x70 +#define IMR_BOOT_LDR_TEXT_BASE (IMR_BOOT_LDR_LIT_BASE + \ + IMR_BOOT_LDR_LIT_SIZE) +#define IMR_BOOT_LDR_TEXT_SIZE 0x1C00 +#define IMR_BOOT_LDR_DATA_BASE 0xB0002000 +#define IMR_BOOT_LDR_DATA_SIZE 0x1000 +#define IMR_BOOT_LDR_BSS_BASE 0xB0100000 +#define IMR_BOOT_LDR_BSS_SIZE 0x10000 + +/** \brief Manifest base address in IMR - used by boot loader copy procedure. */ +#define IMR_BOOT_LDR_MANIFEST_BASE 0xB0004000 + +/** \brief Manifest size (seems unused). */ +#define IMR_BOOT_LDR_MANIFEST_SIZE 0x6000 + #endif diff --git a/src/platform/apollolake/include/platform/platcfg.h b/src/platform/apollolake/include/platform/platcfg.h new file mode 100644 index 0000000..0875db3 --- /dev/null +++ b/src/platform/apollolake/include/platform/platcfg.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2018, Intel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Intel Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Author: Marcin Maka marcin.maka@linux.intel.com + */ + +#ifndef __PLATFORM_PLATCFG_H__ +#define __PLATFORM_PLATCFG_H__ + +#define PLATFORM_RESET_MHE_AT_BOOT 1 + +#define PLATFORM_DISABLE_L2CACHE_AT_BOOT 1 + +#endif diff --git a/src/platform/apollolake/include/platform/platform.h b/src/platform/apollolake/include/platform/platform.h index aefa9b2..6d51752 100644 --- a/src/platform/apollolake/include/platform/platform.h +++ b/src/platform/apollolake/include/platform/platform.h @@ -33,6 +33,7 @@ #ifndef __PLATFORM_PLATFORM_H__ #define __PLATFORM_PLATFORM_H__

+#include <platform/platcfg.h> #include <platform/shim.h> #include <platform/interrupt.h> #include <uapi/ipc.h> diff --git a/src/platform/apollolake/include/platform/shim.h b/src/platform/apollolake/include/platform/shim.h index daff826..2dbfb4a 100644 --- a/src/platform/apollolake/include/platform/shim.h +++ b/src/platform/apollolake/include/platform/shim.h @@ -33,7 +33,10 @@ #define __PLATFORM_SHIM_H__

#include <platform/memory.h> + +#ifndef ASSEMBLY #include <stdint.h> +#endif

/* DSP IPC for Host Registers */ #define IPC_DIPCT 0x00 @@ -146,9 +149,19 @@ #define SHIM_PWRSTS 0x92 #define SHIM_LPSCTL 0x94

+/* HP SRAM Power Gating */ +#define SHIM_HSPGCTL 0x80 +#define SHIM_HPGISTS 0xb0 + #define SHIM_LPSCTL_FDSPRUN (0X1 << 9) #define SHIM_LPSCTL_FDMARUN (0X1 << 8)

+#define SHIM_L2_MECS (SHIM_BASE + 0xd0) + +#define SHIM_L2_CACHE_CTRL (SHIM_BASE + 0x500) +#define SHIM_L2_PREF_CFG (SHIM_BASE + 0x508) +#define SHIM_L2_CACHE_PREF (SHIM_BASE + 0x510) +

/* host windows */ #define DMWBA(x) (HOST_WIN_BASE(x) + 0x0) @@ -157,6 +170,8 @@ #define DMWBA_ENABLE (1 << 0) #define DMWBA_READONLY (1 << 1)

+#ifndef ASSEMBLY + static inline uint32_t shim_read(uint32_t reg) { return *((volatile uint32_t*)(SHIM_BASE + reg)); @@ -179,12 +194,14 @@ static inline void shim_write64(uint32_t reg, uint64_t val)

static inline uint32_t sw_reg_read(uint32_t reg) { - return *((volatile uint32_t*)(SRAM_SW_REG_BASE + reg)); + return *((volatile uint32_t*)((SRAM_SW_REG_BASE - + SRAM_ALIAS_OFFSET) + reg)); }

static inline void sw_reg_write(uint32_t reg, uint32_t val) { - *((volatile uint32_t*)(SRAM_SW_REG_BASE + reg)) = val; + *((volatile uint32_t*)((SRAM_SW_REG_BASE - + SRAM_ALIAS_OFFSET) + reg)) = val; }

static inline uint32_t mn_reg_read(uint32_t reg) @@ -216,5 +233,6 @@ static inline void ipc_write(uint32_t reg, uint32_t val) { *((volatile uint32_t*)(IPC_HOST_BASE + reg)) = val; } +#endif

#endif diff --git a/src/platform/baytrail/include/Makefile.am b/src/platform/baytrail/include/Makefile.am index 19f40eb..c5113a4 100644 --- a/src/platform/baytrail/include/Makefile.am +++ b/src/platform/baytrail/include/Makefile.am @@ -1 +1 @@ -SUBDIRS = platform xtensa +SUBDIRS = arch platform diff --git a/src/platform/baytrail/include/arch/Makefile.am b/src/platform/baytrail/include/arch/Makefile.am new file mode 100644 index 0000000..63616bf --- /dev/null +++ b/src/platform/baytrail/include/arch/Makefile.am @@ -0,0 +1 @@ +SUBDIRS = xtensa diff --git a/src/platform/baytrail/include/xtensa/Makefile.am b/src/platform/baytrail/include/arch/xtensa/Makefile.am similarity index 100% rename from src/platform/baytrail/include/xtensa/Makefile.am rename to src/platform/baytrail/include/arch/xtensa/Makefile.am diff --git a/src/platform/baytrail/include/xtensa/config/Makefile.am b/src/platform/baytrail/include/arch/xtensa/config/Makefile.am similarity index 100% rename from src/platform/baytrail/include/xtensa/config/Makefile.am rename to src/platform/baytrail/include/arch/xtensa/config/Makefile.am diff --git a/src/platform/baytrail/include/xtensa/config/core-isa-byt.h b/src/platform/baytrail/include/arch/xtensa/config/core-isa-byt.h similarity index 100% rename from src/platform/baytrail/include/xtensa/config/core-isa-byt.h rename to src/platform/baytrail/include/arch/xtensa/config/core-isa-byt.h diff --git a/src/platform/baytrail/include/xtensa/config/core-isa-cht.h b/src/platform/baytrail/include/arch/xtensa/config/core-isa-cht.h similarity index 100% rename from src/platform/baytrail/include/xtensa/config/core-isa-cht.h rename to src/platform/baytrail/include/arch/xtensa/config/core-isa-cht.h diff --git a/src/platform/baytrail/include/xtensa/config/core-isa.h b/src/platform/baytrail/include/arch/xtensa/config/core-isa.h similarity index 100% rename from src/platform/baytrail/include/xtensa/config/core-isa.h rename to src/platform/baytrail/include/arch/xtensa/config/core-isa.h diff --git a/src/platform/baytrail/include/xtensa/config/core-matmap.h b/src/platform/baytrail/include/arch/xtensa/config/core-matmap.h similarity index 100% rename from src/platform/baytrail/include/xtensa/config/core-matmap.h rename to src/platform/baytrail/include/arch/xtensa/config/core-matmap.h diff --git a/src/platform/apollolake/include/xtensa/config/defs.h b/src/platform/baytrail/include/arch/xtensa/config/defs.h similarity index 100% rename from src/platform/apollolake/include/xtensa/config/defs.h rename to src/platform/baytrail/include/arch/xtensa/config/defs.h diff --git a/src/platform/baytrail/include/xtensa/config/specreg.h b/src/platform/baytrail/include/arch/xtensa/config/specreg.h similarity index 100% rename from src/platform/baytrail/include/xtensa/config/specreg.h rename to src/platform/baytrail/include/arch/xtensa/config/specreg.h diff --git a/src/platform/baytrail/include/xtensa/config/system.h b/src/platform/baytrail/include/arch/xtensa/config/system.h similarity index 100% rename from src/platform/baytrail/include/xtensa/config/system.h rename to src/platform/baytrail/include/arch/xtensa/config/system.h diff --git a/src/platform/baytrail/include/xtensa/config/tie-asm.h b/src/platform/baytrail/include/arch/xtensa/config/tie-asm.h similarity index 100% rename from src/platform/baytrail/include/xtensa/config/tie-asm.h rename to src/platform/baytrail/include/arch/xtensa/config/tie-asm.h diff --git a/src/platform/baytrail/include/xtensa/config/tie.h b/src/platform/baytrail/include/arch/xtensa/config/tie.h similarity index 100% rename from src/platform/baytrail/include/xtensa/config/tie.h rename to src/platform/baytrail/include/arch/xtensa/config/tie.h diff --git a/src/platform/cannonlake/boot_ldr.x.in b/src/platform/cannonlake/boot_ldr.x.in index e15e631..a023f2e 100644 --- a/src/platform/cannonlake/boot_ldr.x.in +++ b/src/platform/cannonlake/boot_ldr.x.in @@ -8,7 +8,7 @@ */

#include <platform/memory.h> -#include <xtensa/config/core-isa-boot.h> +#include <xtensa/config/core-isa.h>

OUTPUT_ARCH(xtensa)

@@ -23,69 +23,18 @@ MEMORY sof_text : org = IMR_BOOT_LDR_TEXT_BASE, len = IMR_BOOT_LDR_TEXT_SIZE, - vector_base_text : - org = XCHAL_VECBASE_RESET_PADDR, - len = SOF_MEM_VECBASE_LIT_SIZE - vector_int2_lit : - org = XCHAL_INTLEVEL2_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE, - len = SOF_MEM_VECT_LIT_SIZE - vector_int2_text : - org = XCHAL_INTLEVEL2_VECTOR_PADDR, - len = SOF_MEM_VECT_TEXT_SIZE - vector_int3_lit : - org = XCHAL_INTLEVEL3_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE, - len = SOF_MEM_VECT_LIT_SIZE - vector_int3_text : - org = XCHAL_INTLEVEL3_VECTOR_PADDR, - len = SOF_MEM_VECT_TEXT_SIZE - vector_int4_lit : - org = XCHAL_INTLEVEL4_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE, - len = SOF_MEM_VECT_LIT_SIZE - vector_int4_text : - org = XCHAL_INTLEVEL4_VECTOR_PADDR, - len = SOF_MEM_VECT_TEXT_SIZE - vector_int5_lit : - org = XCHAL_INTLEVEL5_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE, - len = SOF_MEM_VECT_LIT_SIZE - vector_int5_text : - org = XCHAL_INTLEVEL5_VECTOR_PADDR, - len = SOF_MEM_VECT_TEXT_SIZE - vector_int6_lit : - org = XCHAL_INTLEVEL6_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE, - len = SOF_MEM_VECT_LIT_SIZE - vector_int6_text : - org = XCHAL_INTLEVEL6_VECTOR_PADDR, - len = SOF_MEM_VECT_TEXT_SIZE - vector_int7_lit : - org = XCHAL_INTLEVEL7_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE, - len = SOF_MEM_VECT_LIT_SIZE - vector_int7_text : - org = XCHAL_INTLEVEL7_VECTOR_PADDR, - len = SOF_MEM_VECT_TEXT_SIZE - vector_kernel_lit : - org = XCHAL_KERNEL_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE, - len = SOF_MEM_VECT_LIT_SIZE - vector_kernel_text : - org = XCHAL_KERNEL_VECTOR_PADDR, - len = SOF_MEM_VECT_TEXT_SIZE - vector_user_lit : - org = XCHAL_USER_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE, - len = SOF_MEM_VECT_LIT_SIZE - vector_user_text : - org = XCHAL_USER_VECTOR_PADDR, - len = SOF_MEM_VECT_TEXT_SIZE - vector_double_lit : - org = XCHAL_DOUBLEEXC_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE, - len = SOF_MEM_VECT_LIT_SIZE - vector_double_text : - org = XCHAL_DOUBLEEXC_VECTOR_PADDR, - len = SOF_MEM_VECT_TEXT_SIZE sof_data : org = IMR_BOOT_LDR_DATA_BASE, len = IMR_BOOT_LDR_DATA_SIZE sof_bss_data : org = IMR_BOOT_LDR_BSS_BASE, len = IMR_BOOT_LDR_BSS_SIZE + sof_stack : + org = SOF_STACK_END, + len = SOF_STACK_BASE - SOF_STACK_END + wnd0 : + org = HP_SRAM_WIN0_BASE, + len = HP_SRAM_WIN0_SIZE }

PHDRS @@ -93,27 +42,10 @@ PHDRS boot_entry_text_phdr PT_LOAD; boot_entry_lit_phdr PT_LOAD; sof_text_phdr PT_LOAD; - vector_base_text_phdr PT_LOAD; - vector_int2_lit_phdr PT_LOAD; - vector_int2_text_phdr PT_LOAD; - vector_int3_lit_phdr PT_LOAD; - vector_int3_text_phdr PT_LOAD; - vector_int4_lit_phdr PT_LOAD; - vector_int4_text_phdr PT_LOAD; - vector_int5_lit_phdr PT_LOAD; - vector_int5_text_phdr PT_LOAD; - vector_int6_lit_phdr PT_LOAD; - vector_int6_text_phdr PT_LOAD; - vector_int7_lit_phdr PT_LOAD; - vector_int7_text_phdr PT_LOAD; - vector_kernel_lit_phdr PT_LOAD; - vector_kernel_text_phdr PT_LOAD; - vector_user_lit_phdr PT_LOAD; - vector_user_text_phdr PT_LOAD; - vector_double_lit_phdr PT_LOAD; - vector_double_text_phdr PT_LOAD; sof_data_phdr PT_LOAD; sof_bss_data_phdr PT_LOAD; + sof_stack_phdr PT_LOAD; + wnd0_phdr PT_LOAD; }

/* Default entry point: */ @@ -150,144 +82,10 @@ SECTIONS *(.gnu.version) KEEP (*(.ResetVector.text)) KEEP (*(.ResetHandler.text)) - KEEP (*(.MemoryExceptionVector.text)) _text_end = ABSOLUTE(.); _etext = .; } >sof_text :sof_text_phdr

- .WindowVectors.text : ALIGN(4) - { - _WindowVectors_text_start = ABSOLUTE(.); - KEEP (*(.WindowVectors.text)) - _WindowVectors_text_end = ABSOLUTE(.); - } >vector_base_text :vector_base_text_phdr - - .Level2InterruptVector.literal : ALIGN(4) - { - _Level2InterruptVector_literal_start = ABSOLUTE(.); - *(.Level2InterruptVector.literal) - _Level2InterruptVector_literal_end = ABSOLUTE(.); - } >vector_int2_lit :vector_int2_lit_phdr - - .Level2InterruptVector.text : ALIGN(4) - { - _Level2InterruptVector_text_start = ABSOLUTE(.); - KEEP (*(.Level2InterruptVector.text)) - _Level2InterruptVector_text_end = ABSOLUTE(.); - } >vector_int2_text :vector_int2_text_phdr - - .Level3InterruptVector.literal : ALIGN(4) - { - _Level3InterruptVector_literal_start = ABSOLUTE(.); - *(.Level3InterruptVector.literal) - _Level3InterruptVector_literal_end = ABSOLUTE(.); - } >vector_int3_lit :vector_int3_lit_phdr - - .Level3InterruptVector.text : ALIGN(4) - { - _Level3InterruptVector_text_start = ABSOLUTE(.); - KEEP (*(.Level3InterruptVector.text)) - _Level3InterruptVector_text_end = ABSOLUTE(.); - } >vector_int3_text :vector_int3_text_phdr - - .Level4InterruptVector.literal : ALIGN(4) - { - _Level4InterruptVector_literal_start = ABSOLUTE(.); - *(.Level4InterruptVector.literal) - _Level4InterruptVector_literal_end = ABSOLUTE(.); - } >vector_int4_lit :vector_int4_lit_phdr - - .Level4InterruptVector.text : ALIGN(4) - { - _Level4InterruptVector_text_start = ABSOLUTE(.); - KEEP (*(.Level4InterruptVector.text)) - _Level4InterruptVector_text_end = ABSOLUTE(.); - } >vector_int4_text :vector_int4_text_phdr - - .Level5InterruptVector.literal : ALIGN(4) - { - _Level5InterruptVector_literal_start = ABSOLUTE(.); - *(.Level5InterruptVector.literal) - _Level5InterruptVector_literal_end = ABSOLUTE(.); - } >vector_int5_lit :vector_int5_lit_phdr - - .Level5InterruptVector.text : ALIGN(4) - { - _Level5InterruptVector_text_start = ABSOLUTE(.); - KEEP (*(.Level5InterruptVector.text)) - _Level5InterruptVector_text_end = ABSOLUTE(.); - } >vector_int5_text :vector_int5_text_phdr - - .DebugExceptionVector.literal : ALIGN(4) - { - _DebugExceptionVector_literal_start = ABSOLUTE(.); - *(.DebugExceptionVector.literal) - _DebugExceptionVector_literal_end = ABSOLUTE(.); - } >vector_int6_lit :vector_int6_lit_phdr - - .DebugExceptionVector.text : ALIGN(4) - { - _DebugExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.DebugExceptionVector.text)) - _DebugExceptionVector_text_end = ABSOLUTE(.); - } >vector_int6_text :vector_int6_text_phdr - - .NMIExceptionVector.literal : ALIGN(4) - { - _NMIExceptionVector_literal_start = ABSOLUTE(.); - *(.NMIExceptionVector.literal) - _NMIExceptionVector_literal_end = ABSOLUTE(.); - } >vector_int7_lit :vector_int7_lit_phdr - - .NMIExceptionVector.text : ALIGN(4) - { - _NMIExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.NMIExceptionVector.text)) - _NMIExceptionVector_text_end = ABSOLUTE(.); - } >vector_int7_text :vector_int7_text_phdr - - .KernelExceptionVector.literal : ALIGN(4) - { - _KernelExceptionVector_literal_start = ABSOLUTE(.); - *(.KernelExceptionVector.literal) - _KernelExceptionVector_literal_end = ABSOLUTE(.); - } >vector_kernel_lit :vector_kernel_lit_phdr - - .KernelExceptionVector.text : ALIGN(4) - { - _KernelExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.KernelExceptionVector.text)) - _KernelExceptionVector_text_end = ABSOLUTE(.); - } >vector_kernel_text :vector_kernel_text_phdr - - .UserExceptionVector.literal : ALIGN(4) - { - _UserExceptionVector_literal_start = ABSOLUTE(.); - *(.UserExceptionVector.literal) - _UserExceptionVector_literal_end = ABSOLUTE(.); - } >vector_user_lit :vector_user_lit_phdr - - .UserExceptionVector.text : ALIGN(4) - { - _UserExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.UserExceptionVector.text)) - _UserExceptionVector_text_end = ABSOLUTE(.); - } >vector_user_text :vector_user_text_phdr - - .DoubleExceptionVector.literal : ALIGN(4) - { - _DoubleExceptionVector_literal_start = ABSOLUTE(.); - *(.DoubleExceptionVector.literal) - _DoubleExceptionVector_literal_end = ABSOLUTE(.); - } >vector_double_lit :vector_double_lit_phdr - - .DoubleExceptionVector.text : ALIGN(4) - { - _DoubleExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.DoubleExceptionVector.text)) - _DoubleExceptionVector_text_end = ABSOLUTE(.); - } >vector_double_text :vector_double_text_phdr - .rodata : ALIGN(4) { _rodata_start = ABSOLUTE(.); @@ -381,6 +179,10 @@ SECTIONS _memmap_cacheattr_wbna_trapnull = 0xFF42FFF2; PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wbna_trapnull);

+ __stack = SOF_STACK_BASE; + __wnd0 = HP_SRAM_WIN0_BASE; + __wnd0_size = HP_SRAM_WIN0_SIZE; + .debug 0 : { *(.debug) } .line 0 : { *(.line) } .debug_srcinfo 0 : { *(.debug_srcinfo) } diff --git a/src/platform/cannonlake/cannonlake.x.in b/src/platform/cannonlake/cannonlake.x.in index 052d637..06f745b 100644 --- a/src/platform/cannonlake/cannonlake.x.in +++ b/src/platform/cannonlake/cannonlake.x.in @@ -14,12 +14,6 @@ OUTPUT_ARCH(xtensa)

MEMORY { - vector_reset_text : - org = XCHAL_RESET_VECTOR0_PADDR, - len = SOF_MEM_RESET_TEXT_SIZE - vector_reset_lit : - org = XCHAL_RESET_VECTOR0_PADDR + SOF_MEM_RESET_TEXT_SIZE, - len = SOF_MEM_RESET_LIT_SIZE vector_memory_lit : org = XCHAL_MEMERROR_VECTOR_PADDR + SOF_MEM_ERROR_LIT_SIZE, len = SOF_MEM_ERROR_LIT_SIZE @@ -27,65 +21,62 @@ MEMORY org = XCHAL_MEMERROR_VECTOR_PADDR, len = SOF_MEM_ERROR_TEXT_SIZE vector_base_text : - org = XCHAL_VECBASE_RESET_PADDR, + org = SOF_MEM_VECBASE, len = SOF_MEM_VECBASE_LIT_SIZE vector_int2_lit : - org = XCHAL_INTLEVEL2_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE, + org = SOF_MEM_VECBASE + XCHAL_INTLEVEL2_VECOFS - SOF_MEM_VECT_LIT_SIZE, len = SOF_MEM_VECT_LIT_SIZE vector_int2_text : - org = XCHAL_INTLEVEL2_VECTOR_PADDR, + org = SOF_MEM_VECBASE + XCHAL_INTLEVEL2_VECOFS, len = SOF_MEM_VECT_TEXT_SIZE vector_int3_lit : - org = XCHAL_INTLEVEL3_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE, + org = SOF_MEM_VECBASE + XCHAL_INTLEVEL3_VECOFS - SOF_MEM_VECT_LIT_SIZE, len = SOF_MEM_VECT_LIT_SIZE vector_int3_text : - org = XCHAL_INTLEVEL3_VECTOR_PADDR, + org = SOF_MEM_VECBASE + XCHAL_INTLEVEL3_VECOFS, len = SOF_MEM_VECT_TEXT_SIZE vector_int4_lit : - org = XCHAL_INTLEVEL4_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE, + org = SOF_MEM_VECBASE + XCHAL_INTLEVEL4_VECOFS - SOF_MEM_VECT_LIT_SIZE, len = SOF_MEM_VECT_LIT_SIZE vector_int4_text : - org = XCHAL_INTLEVEL4_VECTOR_PADDR, + org = SOF_MEM_VECBASE + XCHAL_INTLEVEL4_VECOFS, len = SOF_MEM_VECT_TEXT_SIZE vector_int5_lit : - org = XCHAL_INTLEVEL5_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE, + org = SOF_MEM_VECBASE + XCHAL_INTLEVEL5_VECOFS - SOF_MEM_VECT_LIT_SIZE, len = SOF_MEM_VECT_LIT_SIZE vector_int5_text : - org = XCHAL_INTLEVEL5_VECTOR_PADDR, + org = SOF_MEM_VECBASE + XCHAL_INTLEVEL5_VECOFS, len = SOF_MEM_VECT_TEXT_SIZE vector_int6_lit : - org = XCHAL_INTLEVEL6_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE, + org = SOF_MEM_VECBASE + XCHAL_INTLEVEL6_VECOFS - SOF_MEM_VECT_LIT_SIZE, len = SOF_MEM_VECT_LIT_SIZE vector_int6_text : - org = XCHAL_INTLEVEL6_VECTOR_PADDR, + org = SOF_MEM_VECBASE + XCHAL_INTLEVEL6_VECOFS, len = SOF_MEM_VECT_TEXT_SIZE vector_int7_lit : - org = XCHAL_INTLEVEL7_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE, + org = SOF_MEM_VECBASE + XCHAL_INTLEVEL7_VECOFS - SOF_MEM_VECT_LIT_SIZE, len = SOF_MEM_VECT_LIT_SIZE vector_int7_text : - org = XCHAL_INTLEVEL7_VECTOR_PADDR, + org = SOF_MEM_VECBASE + XCHAL_INTLEVEL7_VECOFS, len = SOF_MEM_VECT_TEXT_SIZE vector_kernel_lit : - org = XCHAL_KERNEL_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE, + org = SOF_MEM_VECBASE + XCHAL_KERNEL_VECOFS - SOF_MEM_VECT_LIT_SIZE, len = SOF_MEM_VECT_LIT_SIZE vector_kernel_text : - org = XCHAL_KERNEL_VECTOR_PADDR, + org = SOF_MEM_VECBASE + XCHAL_KERNEL_VECOFS, len = SOF_MEM_VECT_TEXT_SIZE vector_user_lit : - org = XCHAL_USER_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE, + org = SOF_MEM_VECBASE + XCHAL_USER_VECOFS - SOF_MEM_VECT_LIT_SIZE, len = SOF_MEM_VECT_LIT_SIZE vector_user_text : - org = XCHAL_USER_VECTOR_PADDR, + org = SOF_MEM_VECBASE + XCHAL_USER_VECOFS, len = SOF_MEM_VECT_TEXT_SIZE vector_double_lit : - org = XCHAL_DOUBLEEXC_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE, + org = SOF_MEM_VECBASE + XCHAL_DOUBLEEXC_VECOFS - SOF_MEM_VECT_LIT_SIZE, len = SOF_MEM_VECT_LIT_SIZE vector_double_text : - org = XCHAL_DOUBLEEXC_VECTOR_PADDR, + org = SOF_MEM_VECBASE + XCHAL_DOUBLEEXC_VECOFS, len = SOF_MEM_VECT_TEXT_SIZE - sof_text_start : - org = SOF_TEXT_START, - len = SOF_TEXT_START_SIZE, sof_text : org = SOF_TEXT_BASE, len = SOF_TEXT_SIZE, @@ -111,8 +102,6 @@ MEMORY

PHDRS { - vector_reset_text_phdr PT_LOAD; - vector_reset_lit_phdr PT_LOAD; vector_memory_lit_phdr PT_LOAD; vector_memory_text_phdr PT_LOAD; vector_base_text_phdr PT_LOAD; @@ -134,7 +123,6 @@ PHDRS vector_user_text_phdr PT_LOAD; vector_double_lit_phdr PT_LOAD; vector_double_text_phdr PT_LOAD; - sof_text_start_phdr PT_LOAD; sof_text_phdr PT_LOAD; sof_data_phdr PT_LOAD; sof_bss_data_phdr PT_LOAD; @@ -171,27 +159,6 @@ PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wbna_trapnull);

SECTIONS { - .ResetVector.text : ALIGN(4) - { - _ResetVector_text_start = ABSOLUTE(.); - KEEP (*(.ResetVector.text)) - _ResetVector_text_end = ABSOLUTE(.); - } >vector_reset_text :vector_reset_text_phdr - - .ResetVector.literal : ALIGN(4) - { - _ResetVector_literal_start = ABSOLUTE(.); - *(.ResetVector.literal) - _ResetVector_literal_end = ABSOLUTE(.); - } >vector_reset_lit :vector_reset_lit_phdr - - .MemoryExceptionVector.literal : ALIGN(4) - { - _MemoryExceptionVector_literal_start = ABSOLUTE(.); - KEEP (*(.MemoryExceptionVector.literal)) - _MemoryExceptionVector_literal_end = ABSOLUTE(.); - } >vector_memory_lit :vector_memory_lit_phdr - .MemoryExceptionVector.text : ALIGN(4) { _MemoryExceptionVector_text_start = ABSOLUTE(.); @@ -199,7 +166,7 @@ SECTIONS _MemoryExceptionVector_text_end = ABSOLUTE(.); } >vector_memory_text :vector_memory_text_phdr

- .WindowVectors.text : ALIGN(4) + .WindowVectors.text : ALIGN(4) { _WindowVectors_text_start = ABSOLUTE(.); KEEP (*(.WindowVectors.text)) @@ -332,17 +299,11 @@ SECTIONS _DoubleExceptionVector_text_end = ABSOLUTE(.); } >vector_double_text :vector_double_text_phdr

- .MainEntry.text : ALIGN(4) - { - _MainEntry_text_start = ABSOLUTE(.); - KEEP (*(.MainEntry.text)) - _MainEntry_text_end = ABSOLUTE(.); - } >sof_text_start :sof_text_start_phdr - .text : ALIGN(4) { _stext = .; _text_start = ABSOLUTE(.); + KEEP (*(.MainEntry.text)) *(.entry.text) *(.init.literal) KEEP(*(.init)) diff --git a/src/platform/cannonlake/include/Makefile.am b/src/platform/cannonlake/include/Makefile.am index 19f40eb..c5113a4 100644 --- a/src/platform/cannonlake/include/Makefile.am +++ b/src/platform/cannonlake/include/Makefile.am @@ -1 +1 @@ -SUBDIRS = platform xtensa +SUBDIRS = arch platform diff --git a/src/platform/cannonlake/include/arch/Makefile.am b/src/platform/cannonlake/include/arch/Makefile.am new file mode 100644 index 0000000..63616bf --- /dev/null +++ b/src/platform/cannonlake/include/arch/Makefile.am @@ -0,0 +1 @@ +SUBDIRS = xtensa diff --git a/src/platform/cannonlake/include/xtensa/Makefile.am b/src/platform/cannonlake/include/arch/xtensa/Makefile.am similarity index 100% rename from src/platform/cannonlake/include/xtensa/Makefile.am rename to src/platform/cannonlake/include/arch/xtensa/Makefile.am diff --git a/src/platform/cannonlake/include/xtensa/config/Makefile.am b/src/platform/cannonlake/include/arch/xtensa/config/Makefile.am similarity index 84% rename from src/platform/cannonlake/include/xtensa/config/Makefile.am rename to src/platform/cannonlake/include/arch/xtensa/config/Makefile.am index bfca58b..99c21a5 100644 --- a/src/platform/cannonlake/include/xtensa/config/Makefile.am +++ b/src/platform/cannonlake/include/arch/xtensa/config/Makefile.am @@ -5,5 +5,4 @@ noinst_HEADERS = \ specreg.h \ system.h \ tie.h \ - core-isa-boot.h \ tie-asm.h diff --git a/src/platform/cannonlake/include/xtensa/config/core-isa-boot.h b/src/platform/cannonlake/include/arch/xtensa/config/core-isa.h similarity index 95% rename from src/platform/cannonlake/include/xtensa/config/core-isa-boot.h rename to src/platform/cannonlake/include/arch/xtensa/config/core-isa.h index 186643b..8a02768 100644 --- a/src/platform/cannonlake/include/xtensa/config/core-isa-boot.h +++ b/src/platform/cannonlake/include/arch/xtensa/config/core-isa.h @@ -28,8 +28,10 @@ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */

-#ifndef _XTENSA_CORE_BOOT_CONFIGURATION_H -#define _XTENSA_CORE_BOOT_CONFIGURATION_H +#if !defined __XCC__ + +#ifndef _XTENSA_CORE_CONFIGURATION_H +#define _XTENSA_CORE_CONFIGURATION_H

/**************************************************************************** @@ -439,12 +441,12 @@ #define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */ #define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */ #define XCHAL_HAVE_HALT 0 /* halt architecture option */ -#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */ +#define XCHAL_HAVE_BOOTLOADER 1 /* boot loader (for TX) */ #define XCHAL_HAVE_MEM_ECC_PARITY 1 /* local memory ECC/parity */ #define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */ #define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */ -#define XCHAL_VECBASE_RESET_VADDR 0xB003A000 /* VECBASE reset value */ -#define XCHAL_VECBASE_RESET_PADDR 0xB003A000 +#define XCHAL_VECBASE_RESET_VADDR 0xBEFE0800 /* VECBASE reset value */ +#define XCHAL_VECBASE_RESET_PADDR 0xBEFE0800 #define XCHAL_RESET_VECBASE_OVERLAP 0

#define XCHAL_RESET_VECTOR0_VADDR 0xBEFE0000 @@ -460,43 +462,43 @@ #define XCHAL_MEMERROR_VECTOR_VADDR 0xBEFE0400 #define XCHAL_MEMERROR_VECTOR_PADDR 0xBEFE0400 #define XCHAL_USER_VECOFS 0x00000340 -#define XCHAL_USER_VECTOR_VADDR 0xB003A340 -#define XCHAL_USER_VECTOR_PADDR 0xB003A340 +#define XCHAL_USER_VECTOR_VADDR 0xBEFE0B40 +#define XCHAL_USER_VECTOR_PADDR 0xBEFE0B40 #define XCHAL_KERNEL_VECOFS 0x00000300 -#define XCHAL_KERNEL_VECTOR_VADDR 0xB003A300 -#define XCHAL_KERNEL_VECTOR_PADDR 0xB003A300 +#define XCHAL_KERNEL_VECTOR_VADDR 0xBEFE0B00 +#define XCHAL_KERNEL_VECTOR_PADDR 0xBEFE0B00 #define XCHAL_DOUBLEEXC_VECOFS 0x000003C0 -#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0xB003A3C0 -#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0xB003A3C0 +#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0xBEFE0BC0 +#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0xBEFE0BC0 #define XCHAL_WINDOW_OF4_VECOFS 0x00000000 #define XCHAL_WINDOW_UF4_VECOFS 0x00000040 #define XCHAL_WINDOW_OF8_VECOFS 0x00000080 #define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 #define XCHAL_WINDOW_OF12_VECOFS 0x00000100 #define XCHAL_WINDOW_UF12_VECOFS 0x00000140 -#define XCHAL_WINDOW_VECTORS_VADDR 0xB003A000 -#define XCHAL_WINDOW_VECTORS_PADDR 0xB003A000 +#define XCHAL_WINDOW_VECTORS_VADDR 0xBEFE0800 +#define XCHAL_WINDOW_VECTORS_PADDR 0xBEFE0800 #define XCHAL_INTLEVEL2_VECOFS 0x00000180 -#define XCHAL_INTLEVEL2_VECTOR_VADDR 0xB003A180 -#define XCHAL_INTLEVEL2_VECTOR_PADDR 0xB003A180 +#define XCHAL_INTLEVEL2_VECTOR_VADDR 0xBEFE0980 +#define XCHAL_INTLEVEL2_VECTOR_PADDR 0xBEFE0980 #define XCHAL_INTLEVEL3_VECOFS 0x000001C0 -#define XCHAL_INTLEVEL3_VECTOR_VADDR 0xB003A1C0 -#define XCHAL_INTLEVEL3_VECTOR_PADDR 0xB003A1C0 +#define XCHAL_INTLEVEL3_VECTOR_VADDR 0xBEFE09C0 +#define XCHAL_INTLEVEL3_VECTOR_PADDR 0xBEFE09C0 #define XCHAL_INTLEVEL4_VECOFS 0x00000200 -#define XCHAL_INTLEVEL4_VECTOR_VADDR 0xB003A200 -#define XCHAL_INTLEVEL4_VECTOR_PADDR 0xB003A200 +#define XCHAL_INTLEVEL4_VECTOR_VADDR 0xBEFE0A00 +#define XCHAL_INTLEVEL4_VECTOR_PADDR 0xBEFE0A00 #define XCHAL_INTLEVEL5_VECOFS 0x00000240 -#define XCHAL_INTLEVEL5_VECTOR_VADDR 0xB003A240 -#define XCHAL_INTLEVEL5_VECTOR_PADDR 0xB003A240 +#define XCHAL_INTLEVEL5_VECTOR_VADDR 0xBEFE0A40 +#define XCHAL_INTLEVEL5_VECTOR_PADDR 0xBEFE0A40 #define XCHAL_INTLEVEL6_VECOFS 0x00000280 -#define XCHAL_INTLEVEL6_VECTOR_VADDR 0xB003A280 -#define XCHAL_INTLEVEL6_VECTOR_PADDR 0xB003A280 +#define XCHAL_INTLEVEL6_VECTOR_VADDR 0xBEFE0A80 +#define XCHAL_INTLEVEL6_VECTOR_PADDR 0xBEFE0A80 #define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS #define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR #define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR #define XCHAL_NMI_VECOFS 0x000002C0 -#define XCHAL_NMI_VECTOR_VADDR 0xB003A2C0 -#define XCHAL_NMI_VECTOR_PADDR 0xB003A2C0 +#define XCHAL_NMI_VECTOR_VADDR 0xBEFE0AC0 +#define XCHAL_NMI_VECTOR_PADDR 0xBEFE0AC0 #define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS #define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR #define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR @@ -555,3 +557,9 @@

#endif /* _XTENSA_CORE_CONFIGURATION_H */ + +#else + +#error "xcc should not use this header" + +#endif /* __XCC__ */ diff --git a/src/platform/apollolake/include/xtensa/config/core-matmap.h b/src/platform/cannonlake/include/arch/xtensa/config/core-matmap.h similarity index 99% rename from src/platform/apollolake/include/xtensa/config/core-matmap.h rename to src/platform/cannonlake/include/arch/xtensa/config/core-matmap.h index c4f479a..ad0f0d7 100644 --- a/src/platform/apollolake/include/xtensa/config/core-matmap.h +++ b/src/platform/cannonlake/include/arch/xtensa/config/core-matmap.h @@ -43,6 +43,7 @@ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */

+#if !defined __XCC__

#ifndef XTENSA_CONFIG_CORE_MATMAP_H #define XTENSA_CONFIG_CORE_MATMAP_H @@ -311,3 +312,9 @@

#endif /*XTENSA_CONFIG_CORE_MATMAP_H*/ + +#else + +#error "xcc should not use this header" + +#endif /* __XCC__ */ diff --git a/src/platform/haswell/include/xtensa/config/defs.h b/src/platform/cannonlake/include/arch/xtensa/config/defs.h similarity index 94% rename from src/platform/haswell/include/xtensa/config/defs.h rename to src/platform/cannonlake/include/arch/xtensa/config/defs.h index b695e59..c2ef1d9 100644 --- a/src/platform/haswell/include/xtensa/config/defs.h +++ b/src/platform/cannonlake/include/arch/xtensa/config/defs.h @@ -25,6 +25,8 @@ and earlier Xtensa releases. It includes only a subset of the available header files. */

+#if !defined __XCC__ + #ifndef _XTENSA_BASE_HEADER #define _XTENSA_BASE_HEADER

@@ -36,3 +38,9 @@

#endif /* __XTENSA__ */ #endif /* !_XTENSA_BASE_HEADER */ + +#else + +#error "xcc should not use this header" + +#endif /* __XCC__ */ diff --git a/src/platform/apollolake/include/xtensa/config/specreg.h b/src/platform/cannonlake/include/arch/xtensa/config/specreg.h similarity index 96% rename from src/platform/apollolake/include/xtensa/config/specreg.h rename to src/platform/cannonlake/include/arch/xtensa/config/specreg.h index 96bfa94..c99cda6 100644 --- a/src/platform/apollolake/include/xtensa/config/specreg.h +++ b/src/platform/cannonlake/include/arch/xtensa/config/specreg.h @@ -25,6 +25,8 @@ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */

+#if !defined __XCC__ + #ifndef XTENSA_SPECREG_H #define XTENSA_SPECREG_H

@@ -104,3 +106,9 @@ #define INTCLEAR 227

#endif /* XTENSA_SPECREG_H */ + +#else + +#error "xcc should not use this header" + +#endif /* __XCC__ */ diff --git a/src/platform/cannonlake/include/xtensa/config/system.h b/src/platform/cannonlake/include/arch/xtensa/config/system.h similarity index 99% rename from src/platform/cannonlake/include/xtensa/config/system.h rename to src/platform/cannonlake/include/arch/xtensa/config/system.h index aad1d8c..f1fd8a0 100644 --- a/src/platform/cannonlake/include/xtensa/config/system.h +++ b/src/platform/cannonlake/include/arch/xtensa/config/system.h @@ -31,6 +31,7 @@ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */

+#if !defined __XCC__

#ifndef XTENSA_CONFIG_SYSTEM_H #define XTENSA_CONFIG_SYSTEM_H @@ -269,3 +270,9 @@

#endif /*XTENSA_CONFIG_SYSTEM_H*/ + +#else + +#error "xcc should not use this header" + +#endif /* __XCC__ */ diff --git a/src/platform/cannonlake/include/xtensa/config/tie-asm.h b/src/platform/cannonlake/include/arch/xtensa/config/tie-asm.h similarity index 99% rename from src/platform/cannonlake/include/xtensa/config/tie-asm.h rename to src/platform/cannonlake/include/arch/xtensa/config/tie-asm.h index 15f6e89..706545a 100644 --- a/src/platform/cannonlake/include/xtensa/config/tie-asm.h +++ b/src/platform/cannonlake/include/arch/xtensa/config/tie-asm.h @@ -29,6 +29,8 @@ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */

+#if !defined __XCC__ + #ifndef _XTENSA_CORE_TIE_ASM_H #define _XTENSA_CORE_TIE_ASM_H

@@ -237,3 +239,9 @@ .macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm

#endif /*_XTENSA_CORE_TIE_ASM_H*/ + +#else + +#error "xcc should not use this header" + +#endif /* __XCC__ */ diff --git a/src/platform/apollolake/include/xtensa/config/tie.h b/src/platform/cannonlake/include/arch/xtensa/config/tie.h similarity index 98% rename from src/platform/apollolake/include/xtensa/config/tie.h rename to src/platform/cannonlake/include/arch/xtensa/config/tie.h index d47e427..b5fd4c9 100644 --- a/src/platform/apollolake/include/xtensa/config/tie.h +++ b/src/platform/cannonlake/include/arch/xtensa/config/tie.h @@ -29,6 +29,8 @@ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */

+#if !defined __XCC__ + #ifndef _XTENSA_CORE_TIE_H #define _XTENSA_CORE_TIE_H

@@ -167,3 +169,9 @@ 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8

#endif /*_XTENSA_CORE_TIE_H*/ + +#else + +#error "xcc should not use this header" + +#endif /* __XCC__ */ diff --git a/src/platform/cannonlake/include/platform/memory.h b/src/platform/cannonlake/include/platform/memory.h index 244dd25..85e7996 100644 --- a/src/platform/cannonlake/include/platform/memory.h +++ b/src/platform/cannonlake/include/platform/memory.h @@ -127,12 +127,6 @@ #define ROM_BASE 0xBEFE0000 #define ROM_SIZE 0x00002000

-#define TEXT_BASE 0xb0039000 -#define TEXT_LENGTH 0xB000 -#define DATA_BASE 0xb0044000 -#define DATA_LENGTH 0x4000 - - /* * The HP SRAM Region on Cannonlake is organised like this :- * +--------------------------------------------------------------------------+ @@ -167,6 +161,7 @@ */

/* HP SRAM */ +#define SRAM_ALIAS_OFFSET 0x20000000 #define HP_SRAM_BASE 0xBE000000 #define HP_SRAM_SIZE 0x002F0000

@@ -183,9 +178,6 @@ #define HEAP_RT_COUNT512 8 #define HEAP_RT_COUNT1024 4

-/* text and data share the same L2 SRAM on Cannonlake */ -#define SOF_TEXT_START 0xBE040400 -#define SOF_TEXT_START_SIZE 0x40 #define L2_VECTOR_SIZE 0x1000

/* HP SRAM windows */ @@ -236,8 +228,10 @@ #define HEAP_HP_BUFFER_COUNT \ (HEAP_HP_BUFFER_SIZE / HEAP_HP_BUFFER_BLOCK_SIZE)

-#define SOF_TEXT_BASE (SOF_TEXT_START + SOF_TEXT_START_SIZE) -#define SOF_TEXT_SIZE 0x18000 +/* text and data share the same HP L2 SRAM on Cannonlake */ +#define SOF_TEXT_START 0xBE040400 +#define SOF_TEXT_BASE (SOF_TEXT_START) +#define SOF_TEXT_SIZE (0x18000 - 0x400)

/* initialized data */ #if defined CONFIG_DMIC @@ -339,7 +333,8 @@ #define SOF_LP_STACK_END (SOF_LP_STACK_BASE - SOF_LP_STACK_SIZE)

-/* Vector and literal sizes - not in core-isa.h */ +/* Vector and literal sizes - do not use core-isa.h */ +#define SOF_MEM_VECBASE HP_SRAM_VECBASE_RESET #define SOF_MEM_VECT_LIT_SIZE 0x8 #define SOF_MEM_VECT_TEXT_SIZE 0x38 #define SOF_MEM_VECT_SIZE (SOF_MEM_VECT_TEXT_SIZE + SOF_MEM_VECT_LIT_SIZE) @@ -354,19 +349,18 @@ #define SOF_MEM_RO_SIZE 0x8

/* boot loader in IMR */ +#define IMR_BOOT_LDR_MANIFEST_BASE 0xB0032000 +#define IMR_BOOT_LDR_MANIFEST_SIZE 0x6000 + #define IMR_BOOT_LDR_TEXT_ENTRY_BASE 0xB0038000 -#define IMR_BOOT_LDR_TEXT_ENTRY_SIZE 0x40 +#define IMR_BOOT_LDR_TEXT_ENTRY_SIZE 0x66 #define IMR_BOOT_LDR_LIT_BASE (IMR_BOOT_LDR_TEXT_ENTRY_BASE + IMR_BOOT_LDR_TEXT_ENTRY_SIZE) -#define IMR_BOOT_LDR_LIT_SIZE 0x70 +#define IMR_BOOT_LDR_LIT_SIZE 0x20 #define IMR_BOOT_LDR_TEXT_BASE (IMR_BOOT_LDR_LIT_BASE + IMR_BOOT_LDR_LIT_SIZE) #define IMR_BOOT_LDR_TEXT_SIZE 0x1C00 -#define IMR_BOOT_LDR_TEXT1_BASE (IMR_BOOT_LDR_TEXT_BASE + IMR_BOOT_LDR_TEXT_SIZE) -#define IMR_BOOT_LDR_TEXT1_SIZE 0x2000 -#define IMR_BOOT_LDR_DATA_BASE 0xB0002000 +#define IMR_BOOT_LDR_DATA_BASE 0xB0039000 #define IMR_BOOT_LDR_DATA_SIZE 0x1000 #define IMR_BOOT_LDR_BSS_BASE 0xB0100000 #define IMR_BOOT_LDR_BSS_SIZE 0x10000 -#define IMR_BOOT_LDR_MANIFEST_BASE 0xB0032000 -#define IMR_BOOT_LDR_MANIFEST_SIZE 0x6000

#endif diff --git a/src/platform/cannonlake/include/platform/platcfg.h b/src/platform/cannonlake/include/platform/platcfg.h new file mode 100644 index 0000000..f51ee4f --- /dev/null +++ b/src/platform/cannonlake/include/platform/platcfg.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2018, Intel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Intel Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Author: Liam Girdwood liam.r.girdwood@linux.intel.com + */ + +#ifndef __PLATFORM_PLATCFG_H__ +#define __PLATFORM_PLATCFG_H__ + +#define PLATFORM_RESET_MHE_AT_BOOT 1 + +#endif diff --git a/src/platform/cannonlake/include/platform/platform.h b/src/platform/cannonlake/include/platform/platform.h index 35219d7..88614ab 100644 --- a/src/platform/cannonlake/include/platform/platform.h +++ b/src/platform/cannonlake/include/platform/platform.h @@ -34,6 +34,7 @@ #ifndef __PLATFORM_PLATFORM_H__ #define __PLATFORM_PLATFORM_H__

+#include <platform/platcfg.h> #include <platform/shim.h> #include <platform/interrupt.h> #include <uapi/ipc.h> diff --git a/src/platform/cannonlake/include/platform/shim.h b/src/platform/cannonlake/include/platform/shim.h index 6654335..4b17316 100644 --- a/src/platform/cannonlake/include/platform/shim.h +++ b/src/platform/cannonlake/include/platform/shim.h @@ -232,12 +232,14 @@ static inline void shim_write64(uint32_t reg, uint64_t val)

static inline uint32_t sw_reg_read(uint32_t reg) { - return *((volatile uint32_t*)(SRAM_SW_REG_BASE + reg)); + return *((volatile uint32_t*)((SRAM_SW_REG_BASE - + SRAM_ALIAS_OFFSET) + reg)); }

static inline void sw_reg_write(uint32_t reg, uint32_t val) { - *((volatile uint32_t*)(SRAM_SW_REG_BASE + reg)) = val; + *((volatile uint32_t*)((SRAM_SW_REG_BASE - + SRAM_ALIAS_OFFSET) + reg)) = val; }

static inline uint32_t mn_reg_read(uint32_t reg) diff --git a/src/platform/cannonlake/include/xtensa/config/core-isa.h b/src/platform/cannonlake/include/xtensa/config/core-isa.h deleted file mode 100644 index bfad40c..0000000 --- a/src/platform/cannonlake/include/xtensa/config/core-isa.h +++ /dev/null @@ -1,557 +0,0 @@ -/* - * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa - * processor CORE configuration - * - * See <xtensa/config/core.h>, which includes this file, for more details. - */ - -/* Xtensa processor core configuration information. - - Customer ID=10631; Build=0x60f88; Copyright (c) 1999-2016 Tensilica Inc. - - Permission is hereby granted, free of charge, to any person obtaining - a copy of this software and associated documentation files (the - "Software"), to deal in the Software without restriction, including - without limitation the rights to use, copy, modify, merge, publish, - distribute, sublicense, and/or sell copies of the Software, and to - permit persons to whom the Software is furnished to do so, subject to - the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY - CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ - -#ifndef _XTENSA_CORE_CONFIGURATION_H -#define _XTENSA_CORE_CONFIGURATION_H - - -/**************************************************************************** - Parameters Useful for Any Code, USER or PRIVILEGED - ****************************************************************************/ - -/* - * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is - * configured, and a value of 0 otherwise. These macros are always defined. - */ - - -/*---------------------------------------------------------------------- - ISA - ----------------------------------------------------------------------*/ - -#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ -#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ -#define XCHAL_NUM_AREGS 64 /* num of physical addr regs */ -#define XCHAL_NUM_AREGS_LOG2 6 /* log2(XCHAL_NUM_AREGS) */ -#define XCHAL_MAX_INSTRUCTION_SIZE 8 /* max instr bytes (3..8) */ -#define XCHAL_HAVE_DEBUG 1 /* debug option */ -#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ -#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */ -#define XCHAL_LOOP_BUFFER_SIZE 64 /* zero-ov. loop instr buffer size */ -#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */ -#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */ -#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */ -#define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */ -#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */ -#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */ -#define XCHAL_HAVE_MUL32 1 /* MULL instruction */ -#define XCHAL_HAVE_MUL32_HIGH 1 /* MULUH/MULSH instructions */ -#define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */ -#define XCHAL_HAVE_L32R 1 /* L32R instruction */ -#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */ -#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */ -#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */ -#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */ -#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */ -#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */ -#define XCHAL_HAVE_ABS 1 /* ABS instruction */ -/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */ -/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */ -#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */ -#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */ -#define XCHAL_HAVE_SPECULATION 0 /* speculation */ -#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */ -#define XCHAL_NUM_CONTEXTS 1 /* */ -#define XCHAL_NUM_MISC_REGS 0 /* num of scratch regs (0..4) */ -#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */ -#define XCHAL_HAVE_PRID 1 /* processor ID register */ -#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */ -#define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */ -#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */ -#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */ -#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */ -#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */ -#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */ -#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */ -#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */ -/* TODO: CP is 1 - need assembler support */ -#define XCHAL_HAVE_CP 0 /* CPENABLE reg (coprocessor) */ -#define XCHAL_CP_MAXCFG 2 /* max allowed cp id plus one */ -#define XCHAL_HAVE_MAC16 0 /* MAC16 package */ - -#define XCHAL_HAVE_FUSION 0 /* Fusion*/ -#define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */ -#define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */ -#define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */ -#define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */ -#define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */ -#define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */ -#define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */ -#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */ -#define XCHAL_HAVE_FUSION_VITERBI 0 /* Fusion Viterbi option */ -#define XCHAL_HAVE_FUSION_SOFTDEMAP 0 /* Fusion Soft Bit Demap option */ -#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */ -#define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */ -#define XCHAL_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */ -#define XCHAL_HAVE_HIFI3 1 /* HiFi3 Audio Engine pkg */ -#define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */ -#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */ -#define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */ -#define XCHAL_HAVE_HIFI_MINI 0 - - -#define XCHAL_HAVE_VECTORFPU2005 0 /* vector or user floating-point pkg */ -#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */ -#define XCHAL_HAVE_USER_SPFPU 0 /* user DP floating-point pkg */ -#define XCHAL_HAVE_FP 1 /* single prec floating point */ -#define XCHAL_HAVE_FP_DIV 1 /* FP with DIV instructions */ -#define XCHAL_HAVE_FP_RECIP 1 /* FP with RECIP instructions */ -#define XCHAL_HAVE_FP_SQRT 1 /* FP with SQRT instructions */ -#define XCHAL_HAVE_FP_RSQRT 1 /* FP with RSQRT instructions */ -#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */ -#define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */ -#define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/ -#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */ -#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/ -#define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */ -#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */ - -#define XCHAL_HAVE_DFPU_SINGLE_ONLY 1 /* DFPU Coprocessor, single precision only */ -#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */ -#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */ -#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */ -#define XCHAL_HAVE_PDX4 0 /* PDX4 */ -#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */ -#define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */ -#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */ -#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */ -#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */ -#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */ -#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */ -#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */ -#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */ -#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */ -#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */ -#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */ -#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */ -#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */ -#define XCHAL_HAVE_GRIVPEP 0 /* GRIVPEP is General Release of IVPEP */ -#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */ - - -/*---------------------------------------------------------------------- - MISC - ----------------------------------------------------------------------*/ - -#define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */ -#define XCHAL_NUM_WRITEBUFFER_ENTRIES 16 /* size of write buffer */ -#define XCHAL_INST_FETCH_WIDTH 8 /* instr-fetch width in bytes */ -#define XCHAL_DATA_WIDTH 8 /* data width in bytes */ -#define XCHAL_DATA_PIPE_DELAY 2 /* d-side pipeline delay - (1 = 5-stage, 2 = 7-stage) */ -#define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */ -#define XCHAL_CLOCK_GATING_FUNCUNIT 1 /* funct. unit clock gating */ -/* In T1050, applies to selected core load and store instructions (see ISA): */ -#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */ -#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/ -#define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */ -#define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/ - -#define XCHAL_SW_VERSION 1100003 /* sw version of this header */ - -#define XCHAL_CORE_ID "cavs21_LX6HiFi3_RF3_WB16" /* alphanum core name - (CoreID) set in the Xtensa - Processor Generator */ - -#define XCHAL_BUILD_UNIQUE_ID 0x00060F88 /* 22-bit sw build ID */ - -/* - * These definitions describe the hardware targeted by this software. - */ -#define XCHAL_HW_CONFIGID0 0xC2F3FBFE /* ConfigID hi 32 bits*/ -#define XCHAL_HW_CONFIGID1 0x1CC60F88 /* ConfigID lo 32 bits*/ -#define XCHAL_HW_VERSION_NAME "LX6.0.3" /* full version name */ -#define XCHAL_HW_VERSION_MAJOR 2600 /* major ver# of targeted hw */ -#define XCHAL_HW_VERSION_MINOR 3 /* minor ver# of targeted hw */ -#define XCHAL_HW_VERSION 260003 /* major*100+minor */ -#define XCHAL_HW_REL_LX6 1 -#define XCHAL_HW_REL_LX6_0 1 -#define XCHAL_HW_REL_LX6_0_3 1 -#define XCHAL_HW_CONFIGID_RELIABLE 1 -/* If software targets a *range* of hardware versions, these are the bounds: */ -#define XCHAL_HW_MIN_VERSION_MAJOR 2600 /* major v of earliest tgt hw */ -#define XCHAL_HW_MIN_VERSION_MINOR 3 /* minor v of earliest tgt hw */ -#define XCHAL_HW_MIN_VERSION 260003 /* earliest targeted hw */ -#define XCHAL_HW_MAX_VERSION_MAJOR 2600 /* major v of latest tgt hw */ -#define XCHAL_HW_MAX_VERSION_MINOR 3 /* minor v of latest tgt hw */ -#define XCHAL_HW_MAX_VERSION 260003 /* latest targeted hw */ - - -/*---------------------------------------------------------------------- - CACHE - ----------------------------------------------------------------------*/ - -#define XCHAL_ICACHE_LINESIZE 64 /* I-cache line size in bytes */ -#define XCHAL_DCACHE_LINESIZE 64 /* D-cache line size in bytes */ -#define XCHAL_ICACHE_LINEWIDTH 6 /* log2(I line size in bytes) */ -#define XCHAL_DCACHE_LINEWIDTH 6 /* log2(D line size in bytes) */ - -#define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */ -#define XCHAL_DCACHE_SIZE 49152 /* D-cache size in bytes or 0 */ - -#define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */ -#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ - -#define XCHAL_HAVE_PREFETCH 1 /* PREFCTL register */ -#define XCHAL_HAVE_PREFETCH_L1 1 /* prefetch to L1 dcache */ -#define XCHAL_PREFETCH_CASTOUT_LINES 2 /* dcache pref. castout bufsz */ -#define XCHAL_PREFETCH_ENTRIES 8 /* cache prefetch entries */ -#define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */ -#define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */ -#define XCHAL_HAVE_ICACHE_TEST 1 /* Icache test instructions */ -#define XCHAL_HAVE_DCACHE_TEST 1 /* Dcache test instructions */ -#define XCHAL_HAVE_ICACHE_DYN_WAYS 1 /* Icache dynamic way support */ -#define XCHAL_HAVE_DCACHE_DYN_WAYS 1 /* Dcache dynamic way support */ - - - - -/**************************************************************************** - Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code - ****************************************************************************/ - - -#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY - -/*---------------------------------------------------------------------- - CACHE - ----------------------------------------------------------------------*/ - -#define XCHAL_HAVE_PIF 1 /* any outbound PIF present */ -#define XCHAL_HAVE_AXI 0 /* AXI bus */ - -#define XCHAL_HAVE_PIF_WR_RESP 0 /* pif write response */ -#define XCHAL_HAVE_PIF_REQ_ATTR 1 /* pif attribute */ - -/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */ - -/* Number of cache sets in log2(lines per way): */ -#define XCHAL_ICACHE_SETWIDTH 6 -#define XCHAL_DCACHE_SETWIDTH 8 - -/* Cache set associativity (number of ways): */ -#define XCHAL_ICACHE_WAYS 4 -#define XCHAL_DCACHE_WAYS 3 - -/* Cache features: */ -#define XCHAL_ICACHE_LINE_LOCKABLE 1 -#define XCHAL_DCACHE_LINE_LOCKABLE 1 -#define XCHAL_ICACHE_ECC_PARITY XTHAL_MEMEP_ECC -#define XCHAL_DCACHE_ECC_PARITY XTHAL_MEMEP_ECC - -/* Cache access size in bytes (affects operation of SICW instruction): */ -#define XCHAL_ICACHE_ACCESS_SIZE 8 -#define XCHAL_DCACHE_ACCESS_SIZE 8 - -#define XCHAL_DCACHE_BANKS 1 /* number of banks */ - -/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */ -#define XCHAL_CA_BITS 4 - - -/*---------------------------------------------------------------------- - INTERNAL I/D RAM/ROMs and XLMI - ----------------------------------------------------------------------*/ - -#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */ -#define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */ -#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */ -#define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */ -#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/ -#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */ - -#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/ - - -/*---------------------------------------------------------------------- - INTERRUPTS and TIMERS - ----------------------------------------------------------------------*/ - -#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ -#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */ -#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ -#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ -#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */ -#define XCHAL_NUM_INTERRUPTS 21 /* number of interrupts */ -#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */ -#define XCHAL_NUM_EXTINTERRUPTS 8 /* num of external interrupts */ -#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels - (not including level zero) */ -#define XCHAL_EXCM_LEVEL 5 /* level masked by PS.EXCM */ - /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */ - -/* Masks of interrupts at each interrupt level: */ -#define XCHAL_INTLEVEL1_MASK 0x0000000F -#define XCHAL_INTLEVEL2_MASK 0x000000F0 -#define XCHAL_INTLEVEL3_MASK 0x00000F00 -#define XCHAL_INTLEVEL4_MASK 0x00007000 -#define XCHAL_INTLEVEL5_MASK 0x000F8000 -#define XCHAL_INTLEVEL6_MASK 0x00000000 -#define XCHAL_INTLEVEL7_MASK 0x00100000 - -/* Masks of interrupts at each range 1..n of interrupt levels: */ -#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x0000000F -#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x000000FF -#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x00000FFF -#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x00007FFF -#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x000FFFFF -#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x000FFFFF -#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x001FFFFF - -/* Level of each interrupt: */ -#define XCHAL_INT0_LEVEL 1 -#define XCHAL_INT1_LEVEL 1 -#define XCHAL_INT2_LEVEL 1 -#define XCHAL_INT3_LEVEL 1 -#define XCHAL_INT4_LEVEL 2 -#define XCHAL_INT5_LEVEL 2 -#define XCHAL_INT6_LEVEL 2 -#define XCHAL_INT7_LEVEL 2 -#define XCHAL_INT8_LEVEL 3 -#define XCHAL_INT9_LEVEL 3 -#define XCHAL_INT10_LEVEL 3 -#define XCHAL_INT11_LEVEL 3 -#define XCHAL_INT12_LEVEL 4 -#define XCHAL_INT13_LEVEL 4 -#define XCHAL_INT14_LEVEL 4 -#define XCHAL_INT15_LEVEL 5 -#define XCHAL_INT16_LEVEL 5 -#define XCHAL_INT17_LEVEL 5 -#define XCHAL_INT18_LEVEL 5 -#define XCHAL_INT19_LEVEL 5 -#define XCHAL_INT20_LEVEL 7 -#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */ -#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */ -#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with - EXCSAVE/EPS/EPC_n, RFI n) */ - -/* Type of each interrupt: */ -#define XCHAL_INT0_TYPE XTHAL_INTTYPE_SOFTWARE -#define XCHAL_INT1_TYPE XTHAL_INTTYPE_TIMER -#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT3_TYPE XTHAL_INTTYPE_SOFTWARE -#define XCHAL_INT4_TYPE XTHAL_INTTYPE_SOFTWARE -#define XCHAL_INT5_TYPE XTHAL_INTTYPE_TIMER -#define XCHAL_INT6_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE -#define XCHAL_INT8_TYPE XTHAL_INTTYPE_SOFTWARE -#define XCHAL_INT9_TYPE XTHAL_INTTYPE_TIMER -#define XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE -#define XCHAL_INT12_TYPE XTHAL_INTTYPE_SOFTWARE -#define XCHAL_INT13_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT14_TYPE XTHAL_INTTYPE_SOFTWARE -#define XCHAL_INT15_TYPE XTHAL_INTTYPE_SOFTWARE -#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT19_TYPE XTHAL_INTTYPE_SOFTWARE -#define XCHAL_INT20_TYPE XTHAL_INTTYPE_NMI - -/* Masks of interrupts for each type of interrupt: */ -#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFE00000 -#define XCHAL_INTTYPE_MASK_SOFTWARE 0x0008D999 -#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x00000000 -#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x00072444 -#define XCHAL_INTTYPE_MASK_TIMER 0x00000222 -#define XCHAL_INTTYPE_MASK_NMI 0x00100000 -#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000 -#define XCHAL_INTTYPE_MASK_PROFILING 0x00000000 - -/* Interrupt numbers assigned to specific interrupt sources: */ -#define XCHAL_TIMER0_INTERRUPT 1 /* CCOMPARE0 */ -#define XCHAL_TIMER1_INTERRUPT 5 /* CCOMPARE1 */ -#define XCHAL_TIMER2_INTERRUPT 9 /* CCOMPARE2 */ -#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED -#define XCHAL_NMI_INTERRUPT 20 /* non-maskable interrupt */ - -/* Interrupt numbers for levels at which only one interrupt is configured: */ -#define XCHAL_INTLEVEL7_NUM 20 -/* (There are many interrupts each at level(s) 1, 2, 3, 4, 5.) */ - - -/* - * External interrupt mapping. - * These macros describe how Xtensa processor interrupt numbers - * (as numbered internally, eg. in INTERRUPT and INTENABLE registers) - * map to external BInterrupt<n> pins, for those interrupts - * configured as external (level-triggered, edge-triggered, or NMI). - * See the Xtensa processor databook for more details. - */ - -/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */ -#define XCHAL_EXTINT0_NUM 2 /* (intlevel 1) */ -#define XCHAL_EXTINT1_NUM 6 /* (intlevel 2) */ -#define XCHAL_EXTINT2_NUM 10 /* (intlevel 3) */ -#define XCHAL_EXTINT3_NUM 13 /* (intlevel 4) */ -#define XCHAL_EXTINT4_NUM 16 /* (intlevel 5) */ -#define XCHAL_EXTINT5_NUM 17 /* (intlevel 5) */ -#define XCHAL_EXTINT6_NUM 18 /* (intlevel 5) */ -#define XCHAL_EXTINT7_NUM 20 /* (intlevel 7) */ -/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */ -#define XCHAL_INT2_EXTNUM 0 /* (intlevel 1) */ -#define XCHAL_INT6_EXTNUM 1 /* (intlevel 2) */ -#define XCHAL_INT10_EXTNUM 2 /* (intlevel 3) */ -#define XCHAL_INT13_EXTNUM 3 /* (intlevel 4) */ -#define XCHAL_INT16_EXTNUM 4 /* (intlevel 5) */ -#define XCHAL_INT17_EXTNUM 5 /* (intlevel 5) */ -#define XCHAL_INT18_EXTNUM 6 /* (intlevel 5) */ -#define XCHAL_INT20_EXTNUM 7 /* (intlevel 7) */ - - -/*---------------------------------------------------------------------- - EXCEPTIONS and VECTORS - ----------------------------------------------------------------------*/ - -#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture - number: 1 == XEA1 (old) - 2 == XEA2 (new) - 0 == XEAX (extern) or TX */ -#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ -#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */ -#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */ -#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */ -#define XCHAL_HAVE_HALT 0 /* halt architecture option */ -#define XCHAL_HAVE_BOOTLOADER 1 /* boot loader (for TX) */ -#define XCHAL_HAVE_MEM_ECC_PARITY 1 /* local memory ECC/parity */ -#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */ -#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */ -#define XCHAL_VECBASE_RESET_VADDR 0xBE040000 /* VECBASE reset value */ -#define XCHAL_VECBASE_RESET_PADDR 0xBE040000 -#define XCHAL_RESET_VECBASE_OVERLAP 0 - -#define XCHAL_RESET_VECTOR0_VADDR 0xBEFE0000 -#define XCHAL_RESET_VECTOR0_PADDR 0xBEFE0000 -#define XCHAL_RESET_VECTOR1_VADDR 0xBE800000 -#define XCHAL_RESET_VECTOR1_PADDR 0xBE800000 -#define XCHAL_RESET_VECTOR_VADDR 0xBEFE0000 -#define XCHAL_RESET_VECTOR_PADDR 0xBEFE0000 -#define XCHAL_MEMERROR_VECTOR0_VADDR 0xBEFE0500 -#define XCHAL_MEMERROR_VECTOR0_PADDR 0xBEFE0500 -#define XCHAL_MEMERROR_VECTOR1_VADDR 0xBEFE0500 -#define XCHAL_MEMERROR_VECTOR1_PADDR 0xBEFE0500 -#define XCHAL_MEMERROR_VECTOR_VADDR 0xBEFE0500 -#define XCHAL_MEMERROR_VECTOR_PADDR 0xBEFE0500 -#define XCHAL_USER_VECOFS 0x00000340 -#define XCHAL_USER_VECTOR_VADDR 0xBE040340 -#define XCHAL_USER_VECTOR_PADDR 0xBE040340 -#define XCHAL_KERNEL_VECOFS 0x00000300 -#define XCHAL_KERNEL_VECTOR_VADDR 0xBE040300 -#define XCHAL_KERNEL_VECTOR_PADDR 0xBE040300 -#define XCHAL_DOUBLEEXC_VECOFS 0x000003C0 -#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0xBE0403C0 -#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0xBE0403C0 -#define XCHAL_WINDOW_OF4_VECOFS 0x00000000 -#define XCHAL_WINDOW_UF4_VECOFS 0x00000040 -#define XCHAL_WINDOW_OF8_VECOFS 0x00000080 -#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 -#define XCHAL_WINDOW_OF12_VECOFS 0x00000100 -#define XCHAL_WINDOW_UF12_VECOFS 0x00000140 -#define XCHAL_WINDOW_VECTORS_VADDR 0xBE040400 -#define XCHAL_WINDOW_VECTORS_PADDR 0xBE040400 -#define XCHAL_INTLEVEL2_VECOFS 0x00000180 -#define XCHAL_INTLEVEL2_VECTOR_VADDR 0xBE040180 -#define XCHAL_INTLEVEL2_VECTOR_PADDR 0xBE040180 -#define XCHAL_INTLEVEL3_VECOFS 0x000001C0 -#define XCHAL_INTLEVEL3_VECTOR_VADDR 0xBE0401C0 -#define XCHAL_INTLEVEL3_VECTOR_PADDR 0xBE0401C0 -#define XCHAL_INTLEVEL4_VECOFS 0x00000200 -#define XCHAL_INTLEVEL4_VECTOR_VADDR 0xBE040200 -#define XCHAL_INTLEVEL4_VECTOR_PADDR 0xBE040200 -#define XCHAL_INTLEVEL5_VECOFS 0x00000240 -#define XCHAL_INTLEVEL5_VECTOR_VADDR 0xBE040240 -#define XCHAL_INTLEVEL5_VECTOR_PADDR 0xBE040240 -#define XCHAL_INTLEVEL6_VECOFS 0x00000280 -#define XCHAL_INTLEVEL6_VECTOR_VADDR 0xBE040280 -#define XCHAL_INTLEVEL6_VECTOR_PADDR 0xBE040280 -#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS -#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR -#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR -#define XCHAL_NMI_VECOFS 0x000002C0 -#define XCHAL_NMI_VECTOR_VADDR 0xBE0402C0 -#define XCHAL_NMI_VECTOR_PADDR 0xBE0402C0 -#define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS -#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR -#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR - - -/*---------------------------------------------------------------------- - DEBUG MODULE - ----------------------------------------------------------------------*/ - -/* Misc */ -#define XCHAL_HAVE_DEBUG_ERI 0 /* ERI to debug module */ -#define XCHAL_HAVE_DEBUG_APB 0 /* APB to debug module */ -#define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */ - -/* On-Chip Debug (OCD) */ -#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ -#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */ -#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ -#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */ -#define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */ - -/* TRAX (in core) */ -#define XCHAL_HAVE_TRAX 0 /* TRAX in debug module */ -#define XCHAL_TRAX_MEM_SIZE 0 /* TRAX memory size in bytes */ -#define XCHAL_TRAX_MEM_SHAREABLE 0 /* start/end regs; ready sig. */ -#define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */ -#define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */ - -/* Perf counters */ -#define XCHAL_NUM_PERF_COUNTERS 0 /* performance counters */ - - -/*---------------------------------------------------------------------- - MMU - ----------------------------------------------------------------------*/ - -/* See core-matmap.h header file for more details. */ - -#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ -#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */ -#define XCHAL_SPANNING_WAY 0 /* TLB spanning way number */ -#define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */ -#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ -#define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */ -#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ -#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table - [autorefill] and protection) - usable for an MMU-based OS */ -/* If none of the above last 4 are set, it's a custom TLB configuration. */ - -#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */ -#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */ -#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */ - -#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ - - -#endif /* _XTENSA_CORE_CONFIGURATION_H */ diff --git a/src/platform/haswell/include/Makefile.am b/src/platform/haswell/include/Makefile.am index 19f40eb..c5113a4 100644 --- a/src/platform/haswell/include/Makefile.am +++ b/src/platform/haswell/include/Makefile.am @@ -1 +1 @@ -SUBDIRS = platform xtensa +SUBDIRS = arch platform diff --git a/src/platform/haswell/include/arch/Makefile.am b/src/platform/haswell/include/arch/Makefile.am new file mode 100644 index 0000000..63616bf --- /dev/null +++ b/src/platform/haswell/include/arch/Makefile.am @@ -0,0 +1 @@ +SUBDIRS = xtensa diff --git a/src/platform/haswell/include/xtensa/Makefile.am b/src/platform/haswell/include/arch/xtensa/Makefile.am similarity index 100% rename from src/platform/haswell/include/xtensa/Makefile.am rename to src/platform/haswell/include/arch/xtensa/Makefile.am diff --git a/src/platform/haswell/include/xtensa/config/Makefile.am b/src/platform/haswell/include/arch/xtensa/config/Makefile.am similarity index 100% rename from src/platform/haswell/include/xtensa/config/Makefile.am rename to src/platform/haswell/include/arch/xtensa/config/Makefile.am diff --git a/src/platform/haswell/include/xtensa/config/core-isa-bdw.h b/src/platform/haswell/include/arch/xtensa/config/core-isa-bdw.h similarity index 100% rename from src/platform/haswell/include/xtensa/config/core-isa-bdw.h rename to src/platform/haswell/include/arch/xtensa/config/core-isa-bdw.h diff --git a/src/platform/haswell/include/xtensa/config/core-isa-hsw.h b/src/platform/haswell/include/arch/xtensa/config/core-isa-hsw.h similarity index 100% rename from src/platform/haswell/include/xtensa/config/core-isa-hsw.h rename to src/platform/haswell/include/arch/xtensa/config/core-isa-hsw.h diff --git a/src/platform/haswell/include/xtensa/config/core-isa.h b/src/platform/haswell/include/arch/xtensa/config/core-isa.h similarity index 100% rename from src/platform/haswell/include/xtensa/config/core-isa.h rename to src/platform/haswell/include/arch/xtensa/config/core-isa.h diff --git a/src/platform/haswell/include/xtensa/config/core-matmap.h b/src/platform/haswell/include/arch/xtensa/config/core-matmap.h similarity index 100% rename from src/platform/haswell/include/xtensa/config/core-matmap.h rename to src/platform/haswell/include/arch/xtensa/config/core-matmap.h diff --git a/src/platform/baytrail/include/xtensa/config/defs.h b/src/platform/haswell/include/arch/xtensa/config/defs.h similarity index 100% rename from src/platform/baytrail/include/xtensa/config/defs.h rename to src/platform/haswell/include/arch/xtensa/config/defs.h diff --git a/src/platform/haswell/include/xtensa/config/specreg.h b/src/platform/haswell/include/arch/xtensa/config/specreg.h similarity index 100% rename from src/platform/haswell/include/xtensa/config/specreg.h rename to src/platform/haswell/include/arch/xtensa/config/specreg.h diff --git a/src/platform/haswell/include/xtensa/config/system.h b/src/platform/haswell/include/arch/xtensa/config/system.h similarity index 100% rename from src/platform/haswell/include/xtensa/config/system.h rename to src/platform/haswell/include/arch/xtensa/config/system.h diff --git a/src/platform/haswell/include/xtensa/config/tie-asm.h b/src/platform/haswell/include/arch/xtensa/config/tie-asm.h similarity index 100% rename from src/platform/haswell/include/xtensa/config/tie-asm.h rename to src/platform/haswell/include/arch/xtensa/config/tie-asm.h diff --git a/src/platform/haswell/include/xtensa/config/tie.h b/src/platform/haswell/include/arch/xtensa/config/tie.h similarity index 100% rename from src/platform/haswell/include/xtensa/config/tie.h rename to src/platform/haswell/include/arch/xtensa/config/tie.h

From: Tomasz Lauda tomasz.lauda@linux.intel.com

Now correct FW version is included into binary.

Signed-off-by: Tomasz Lauda tomasz.lauda@linux.intel.com --- Makefile.am | 2 ++ rimage/man_apl.c | 24 ++++++++++-------------- rimage/man_cnl.c | 24 ++++++++++-------------- 3 files changed, 22 insertions(+), 28 deletions(-)

diff --git a/Makefile.am b/Makefile.am index 5eebb33..d2c4956 100644 --- a/Makefile.am +++ b/Makefile.am @@ -55,5 +55,7 @@ doc-dummy: doc: doc-dummy $(MAKE) -C doc doc

+if !BUILD_RIMAGE all-local: rm -f $(top_srcdir)/src/include/version.h +endif diff --git a/rimage/man_apl.c b/rimage/man_apl.c index 7b32ea1..efe8583 100644 --- a/rimage/man_apl.c +++ b/rimage/man_apl.c @@ -15,12 +15,8 @@ #include "cse.h" #include "plat_auth.h" #include "manifest.h" - -/* hard coded atm - will pass this in from cmd line and git */ -#define MAN_FW_HDR_VERSION_MAJOR 9 -#define MAN_FW_HDR_VERSION_MINOR 22 -#define MAN_FW_HDR_VERSION_HOTFIX 1 -#define MAN_FW_HDR_VERSION_BUILD 0x7da +#include <config.h> +#include <version.h>

/* manifest template */ struct fw_image_manifest apl_manifest = { @@ -65,10 +61,10 @@ struct fw_image_manifest apl_manifest = { .header_id = MAN_CSS_HDR_ID, .padding = 0, .version = { - .major_version = MAN_FW_HDR_VERSION_MAJOR, - .minor_version = MAN_FW_HDR_VERSION_MINOR, - .hotfix_version = MAN_FW_HDR_VERSION_HOTFIX, - .build_version = MAN_FW_HDR_VERSION_BUILD, + .major_version = SOF_MAJOR, + .minor_version = SOF_MINOR, + .hotfix_version = 0, + .build_version = SOF_BUILD, }, .modulus_size = MAN_CSS_MOD_SIZE, .exponent_size = MAN_CSS_EXP_SIZE, @@ -134,10 +130,10 @@ struct fw_image_manifest apl_manifest = { .preload_page_count = 0, /* size in pages from $CPD */ .fw_image_flags = SOF_MAN_FW_HDR_FLAGS, .feature_mask = SOF_MAN_FW_HDR_FEATURES, - .major_version = MAN_FW_HDR_VERSION_MAJOR, - .minor_version = MAN_FW_HDR_VERSION_MINOR, - .hotfix_version = MAN_FW_HDR_VERSION_HOTFIX, - .build_version = MAN_FW_HDR_VERSION_BUILD, + .major_version = SOF_MAJOR, + .minor_version = SOF_MINOR, + .hotfix_version = 0, + .build_version = SOF_BUILD, .load_offset = MAN_DESC_OFFSET, }, }, diff --git a/rimage/man_cnl.c b/rimage/man_cnl.c index 2aec2a7..5ce8c9d 100644 --- a/rimage/man_cnl.c +++ b/rimage/man_cnl.c @@ -15,12 +15,8 @@ #include "cse.h" #include "plat_auth.h" #include "manifest.h" - -/* hard coded atm - will pass this in from cmd line and git */ -#define MAN_FW_HDR_VERSION_MAJOR 10 -#define MAN_FW_HDR_VERSION_MINOR 23 -#define MAN_FW_HDR_VERSION_HOTFIX 0 -#define MAN_FW_HDR_VERSION_BUILD 0x2a4 +#include <config.h> +#include <version.h>

/* manifest template */ struct fw_image_manifest cnl_manifest = { @@ -64,10 +60,10 @@ struct fw_image_manifest cnl_manifest = { .header_id = MAN_CSS_HDR_ID, .padding = 0, .version = { - .major_version = MAN_FW_HDR_VERSION_MAJOR, - .minor_version = MAN_FW_HDR_VERSION_MINOR, - .hotfix_version = MAN_FW_HDR_VERSION_HOTFIX, - .build_version = MAN_FW_HDR_VERSION_BUILD, + .major_version = SOF_MAJOR, + .minor_version = SOF_MINOR, + .hotfix_version = 0, + .build_version = SOF_BUILD, }, .modulus_size = MAN_CSS_MOD_SIZE, .exponent_size = MAN_CSS_EXP_SIZE, @@ -133,10 +129,10 @@ struct fw_image_manifest cnl_manifest = { .preload_page_count = 0, /* size in pages from $CPD */ .fw_image_flags = SOF_MAN_FW_HDR_FLAGS, .feature_mask = SOF_MAN_FW_HDR_FEATURES, - .major_version = MAN_FW_HDR_VERSION_MAJOR, - .minor_version = MAN_FW_HDR_VERSION_MINOR, - .hotfix_version = MAN_FW_HDR_VERSION_HOTFIX, - .build_version = MAN_FW_HDR_VERSION_BUILD, + .major_version = SOF_MAJOR, + .minor_version = SOF_MINOR, + .hotfix_version = 0, + .build_version = SOF_BUILD, .load_offset = 0x30000, }, },

From: Tomasz Lauda tomasz.lauda@linux.intel.com

This patch adds atomic_read and atomic_set methods. Also includes xtensa implementation of those methods.

Signed-off-by: Tomasz Lauda tomasz.lauda@linux.intel.com --- src/arch/xtensa/include/arch/atomic.h | 12 +++++++++++- src/include/sof/atomic.h | 10 ++++++++++ 2 files changed, 21 insertions(+), 1 deletion(-)

diff --git a/src/arch/xtensa/include/arch/atomic.h b/src/arch/xtensa/include/arch/atomic.h index 80c4522..aadc6db 100644 --- a/src/arch/xtensa/include/arch/atomic.h +++ b/src/arch/xtensa/include/arch/atomic.h @@ -39,11 +39,21 @@ typedef struct { volatile int32_t value; } atomic_t;

-static inline void arch_atomic_init(atomic_t *a, int32_t value) +static inline int32_t arch_atomic_read(const atomic_t *a) +{ + return (*(volatile int32_t *)&a->value); +} + +static inline void arch_atomic_set(atomic_t *a, int32_t value) { a->value = value; }

+static inline void arch_atomic_init(atomic_t *a, int32_t value) +{ + arch_atomic_set(a, value); +} + static inline void arch_atomic_add(atomic_t *a, int32_t value) { int32_t result, current; diff --git a/src/include/sof/atomic.h b/src/include/sof/atomic.h index b26b701..6561215 100644 --- a/src/include/sof/atomic.h +++ b/src/include/sof/atomic.h @@ -40,6 +40,16 @@ static inline void atomic_init(atomic_t *a, int32_t value) arch_atomic_init(a, value); }

+static inline int32_t atomic_read(const atomic_t *a) +{ + return arch_atomic_read(a); +} + +static inline void atomic_set(atomic_t *a, int32_t value) +{ + arch_atomic_set(a, value); +} + static inline void atomic_add(atomic_t *a, int32_t value) { arch_atomic_add(a, value);