Cherrytrail SSP settings were the same as Baytrail but the SSP root clock is different. To use 19.2MHz the Xtal source needs to be selected Also add definition for SSP @ 25 MHz - even if it's unlikely to ever be used Tested on Up board and Cyan Chromebook. Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> --- src/platform/baytrail/clk.c | 1 + src/platform/baytrail/include/platform/pmc.h | 14 ++++++++++++-- 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/src/platform/baytrail/clk.c b/src/platform/baytrail/clk.c index b972aed..99e1bfd 100644 --- a/src/platform/baytrail/clk.c +++ b/src/platform/baytrail/clk.c @@ -101,6 +101,7 @@ static const struct freq_table cpu_freq[] = { static const struct freq_table ssp_freq[] = { {19200000, 19, PMC_SET_SSP_19M2}, /* default */ + {25000000, 25, PMC_SET_SSP_25M}, }; #define CPU_DEFAULT_IDX 3 diff --git a/src/platform/baytrail/include/platform/pmc.h b/src/platform/baytrail/include/platform/pmc.h index 8cbda37..c174f19 100644 --- a/src/platform/baytrail/include/platform/pmc.h +++ b/src/platform/baytrail/include/platform/pmc.h @@ -32,13 +32,23 @@ #define __PLATFORM_PMC_H__ #include <stdint.h> +#include <config.h> /* messages */ #define PMC_DDR_LINK_UP 0xc0 /* LPE req path to DRAM is up */ #define PMC_DDR_LINK_DOWN 0xc1 /* LPE req path to DRAM is down */ #define PMC_SET_LPECLK 0xc2 /* LPE req clock change to FR_LAT_REQ */ -#define PMC_SET_SSP_19M2 0xc5 /* LPE req SSP clock to 19.2MHz */ -#define PMC_SET_SSP_25M 0xc6 /* LPE req SSP clock to 25MHz */ + +#ifdef CONFIG_BAYTRAIL + +#define PMC_SET_SSP_19M2 0xc5 /* LPE req SSP clock to 19.2MHz w/ PLL*/ +#define PMC_SET_SSP_25M 0xc6 /* LPE req SSP clock to 25MHz w/ XTAL */ + +#elif CONFIG_CHERRYTRAIL + +#define PMC_SET_SSP_25M 0xc5 /* LPE req SSP clock to 25MHz w/ PLL */ +#define PMC_SET_SSP_19M2 0xc6 /* LPE req SSP clock to 19.2MHz w/ XTAL*/ +#endif int platform_ipc_pmc_init(void); int ipc_pmc_send_msg(uint32_t message); -- 2.14.1