[Sound-open-firmware] [PATCH] bvt: clk: Fix clock lookup table
Baytrail clock lookup has wrong ticks per MHz values for 19.2M. Fix.
Signed-off-by: Liam Girdwood liam.r.girdwood@linux.intel.com --- src/platform/baytrail/clk.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/platform/baytrail/clk.c b/src/platform/baytrail/clk.c index eac64c3..b616eff 100644 --- a/src/platform/baytrail/clk.c +++ b/src/platform/baytrail/clk.c @@ -67,8 +67,8 @@ static struct clk_pdata *clk_pdata; #if defined CONFIG_BAYTRAIL /* increasing frequency order */ static const struct freq_table cpu_freq[] = { - {19200000, 25, 0x0}, - {19200000, 25, 0x1}, + {19200000, 19, 0x0}, + {19200000, 19, 0x1}, {38400000, 50, 0x2}, {50000000, 50, 0x3}, /* default */ {100000000, 100, 0x4},
BYT and CHT have EP Hifi2 extension so enable it.
Signed-off-by: Liam Girdwood liam.r.girdwood@linux.intel.com --- configure.ac | 4 ++-- src/platform/baytrail/include/xtensa/config/core-isa-byt.h | 2 +- src/platform/baytrail/include/xtensa/config/core-isa-cht.h | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/configure.ac b/configure.ac index 091cc69..8946c36 100644 --- a/configure.ac +++ b/configure.ac @@ -77,7 +77,7 @@ case "$with_platform" in FW_NAME="byt" AC_SUBST(FW_NAME)
- XTENSA_CORE="hifi2_std" + XTENSA_CORE="hifiep_bd5" AC_SUBST(XTENSA_CORE)
AC_DEFINE([CONFIG_BAYTRAIL], [1], [Configure for Baytrail]) @@ -93,7 +93,7 @@ case "$with_platform" in FW_NAME="cht" AC_SUBST(FW_NAME)
- XTENSA_CORE="hifi2_std" + XTENSA_CORE="hifiep_bd5" AC_SUBST(XTENSA_CORE)
AC_DEFINE([CONFIG_CHERRYTRAIL], [1], [Configure for Cherrytrail]) diff --git a/src/platform/baytrail/include/xtensa/config/core-isa-byt.h b/src/platform/baytrail/include/xtensa/config/core-isa-byt.h index 5ee2a2d..4fbc4fe 100644 --- a/src/platform/baytrail/include/xtensa/config/core-isa-byt.h +++ b/src/platform/baytrail/include/xtensa/config/core-isa-byt.h @@ -176,7 +176,7 @@
#define XCHAL_SW_VERSION 1100002 /* sw version of this header */
-#define XCHAL_CORE_ID "hifi2ep" /* alphanum core name +#define XCHAL_CORE_ID "hifiep_bd5" /* alphanum core name (CoreID) set in the Xtensa Processor Generator */
diff --git a/src/platform/baytrail/include/xtensa/config/core-isa-cht.h b/src/platform/baytrail/include/xtensa/config/core-isa-cht.h index 5ee2a2d..4fbc4fe 100644 --- a/src/platform/baytrail/include/xtensa/config/core-isa-cht.h +++ b/src/platform/baytrail/include/xtensa/config/core-isa-cht.h @@ -176,7 +176,7 @@
#define XCHAL_SW_VERSION 1100002 /* sw version of this header */
-#define XCHAL_CORE_ID "hifi2ep" /* alphanum core name +#define XCHAL_CORE_ID "hifiep_bd5" /* alphanum core name (CoreID) set in the Xtensa Processor Generator */
We must build the Makefile before we can clean old object files.
Signed-off-by: Liam Girdwood liam.r.girdwood@linux.intel.com --- build-all.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/build-all.sh b/build-all.sh index 83b0aa8..2e015f6 100755 --- a/build-all.sh +++ b/build-all.sh @@ -10,8 +10,8 @@ pwd=`pwd` rm -fr src/arch/xtensa/*.ri
# Build for Baytrail -make clean ./configure --with-arch=xtensa --with-platform=baytrail --with-root-dir=$pwd/../xtensa-root/xtensa-byt-elf --host=xtensa-byt-elf +make clean make make bin
On 12/04/2017 02:16 PM, Liam Girdwood wrote:
Baytrail clock lookup has wrong ticks per MHz values for 19.2M. Fix.
Signed-off-by: Liam Girdwood liam.r.girdwood@linux.intel.com
src/platform/baytrail/clk.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/platform/baytrail/clk.c b/src/platform/baytrail/clk.c index eac64c3..b616eff 100644 --- a/src/platform/baytrail/clk.c +++ b/src/platform/baytrail/clk.c @@ -67,8 +67,8 @@ static struct clk_pdata *clk_pdata; #if defined CONFIG_BAYTRAIL /* increasing frequency order */ static const struct freq_table cpu_freq[] = {
- {19200000, 25, 0x0},
- {19200000, 25, 0x1},
- {19200000, 19, 0x0},
- {19200000, 19, 0x1}, {38400000, 50, 0x2},
are you sure about this? I double-checked in the HAS and the only thing which is related to 19.2 is the SSP clock, this is unrelated to the cpu_frequency.
this table should be
diff --git a/src/platform/baytrail/clk.c b/src/platform/baytrail/clk.c index eac64c3..b972aed 100644 --- a/src/platform/baytrail/clk.c +++ b/src/platform/baytrail/clk.c @@ -67,9 +67,9 @@ static struct clk_pdata *clk_pdata; #if defined CONFIG_BAYTRAIL /* increasing frequency order */ static const struct freq_table cpu_freq[] = { - {19200000, 25, 0x0}, - {19200000, 25, 0x1}, - {38400000, 50, 0x2}, + {25000000, 25, 0x0}, + {25000000, 25, 0x1}, + {50000000, 50, 0x2}, {50000000, 50, 0x3}, /* default */ {100000000, 100, 0x4}, {200000000, 200, 0x5},
{50000000, 50, 0x3}, /* default */ {100000000, 100, 0x4},
On Mon, 2017-12-04 at 21:51 -0600, Pierre-Louis Bossart wrote:
On 12/04/2017 02:16 PM, Liam Girdwood wrote:
Baytrail clock lookup has wrong ticks per MHz values for 19.2M. Fix.
Signed-off-by: Liam Girdwood liam.r.girdwood@linux.intel.com
src/platform/baytrail/clk.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/platform/baytrail/clk.c b/src/platform/baytrail/clk.c index eac64c3..b616eff 100644 --- a/src/platform/baytrail/clk.c +++ b/src/platform/baytrail/clk.c @@ -67,8 +67,8 @@ static struct clk_pdata *clk_pdata; #if defined CONFIG_BAYTRAIL /* increasing frequency order */ static const struct freq_table cpu_freq[] = {
- {19200000, 25, 0x0},
- {19200000, 25, 0x1},
- {19200000, 19, 0x0},
- {19200000, 19, 0x1}, {38400000, 50, 0x2},
are you sure about this? I double-checked in the HAS and the only thing which is related to 19.2 is the SSP clock, this is unrelated to the cpu_frequency.
this table should be
diff --git a/src/platform/baytrail/clk.c b/src/platform/baytrail/clk.c index eac64c3..b972aed 100644 --- a/src/platform/baytrail/clk.c +++ b/src/platform/baytrail/clk.c @@ -67,9 +67,9 @@ static struct clk_pdata *clk_pdata; #if defined CONFIG_BAYTRAIL /* increasing frequency order */ static const struct freq_table cpu_freq[] = {
{19200000, 25, 0x0},{19200000, 25, 0x1},{38400000, 50, 0x2},
{25000000, 25, 0x0},{25000000, 25, 0x1},{50000000, 50, 0x2}, {50000000, 50, 0x3}, /* default */ {100000000, 100, 0x4}, {200000000, 200, 0x5},{50000000, 50, 0x3}, /* default */ {100000000, 100, 0x4},
Yep, doubled checked that now and the CHT HAS too. So the original was correct wrt ticks per MHz, but wrong with clock. Both clocks are XTAL.
Fix in V2.
Liam
participants (2)
-
Liam Girdwood -
Pierre-Louis Bossart