[Sound-open-firmware] [PATCH V3 1/3] platform: add sof_ipc_window for byt, hsw and bdw
From: Pan Xiuli xiuli.pan@linux.intel.com
Add sof_ipc_window for all platforms, and add IPC send after boot compelted. Also remove the deprecated ready window.
Signed-off-by: Pan Xiuli xiuli.pan@linux.intel.com --- Test with: Mininow max rt5651 GP-MRB nocodec SOF master: 1693b66bb1d804ded975767cc1e5911e6ff9c93c SOF-Tool master: a02abb799405d0e4ad0d6bb46eacf6fbe958c06e https://github.com/plbossart/sound/tree/topic/sof-v4.14: 9513a73b981bc1917705671ec54402a7e21672eb
--- src/platform/baytrail/platform.c | 45 ++++++++++++++++++++++++++++++++++++---- src/platform/haswell/platform.c | 45 ++++++++++++++++++++++++++++++++++++---- 2 files changed, 82 insertions(+), 8 deletions(-)
diff --git a/src/platform/baytrail/platform.c b/src/platform/baytrail/platform.c index 4709fcd..2c4bfee 100644 --- a/src/platform/baytrail/platform.c +++ b/src/platform/baytrail/platform.c @@ -59,10 +59,6 @@ static const struct sof_ipc_fw_ready ready = { .size = sizeof(struct sof_ipc_fw_ready), }, /* dspbox is for DSP initiated IPC, hostbox is for host initiated IPC */ - .dspbox_offset = MAILBOX_HOST_OFFSET + MAILBOX_DSPBOX_OFFSET, - .hostbox_offset = MAILBOX_HOST_OFFSET + MAILBOX_HOSTBOX_OFFSET, - .dspbox_size = MAILBOX_DSPBOX_SIZE, - .hostbox_size = MAILBOX_HOSTBOX_SIZE, .version = { .build = REEF_BUILD, .minor = REEF_MINOR, @@ -74,6 +70,45 @@ static const struct sof_ipc_fw_ready ready = { /* TODO: add capabilities */ };
+#define NUM_BYT_WINDOWS 4 +static const struct sof_ipc_window sram_window = { + .ext_hdr = { + .hdr.cmd = SOF_IPC_FW_READY, + .hdr.size = sizeof(struct sof_ipc_window) + + sizeof(struct sof_ipc_window_elem) * NUM_BYT_WINDOWS, + .type = SOF_IPC_EXT_WINDOW, + }, + .num_windows = NUM_BYT_WINDOWS, + .window[0] = { + .type = SOF_IPC_REGION_UPBOX, + .id = 0, /* map to host window 0 */ + .flags = 0, // TODO: set later + .size = MAILBOX_DSPBOX_SIZE, + .offset = MAILBOX_DSPBOX_OFFSET, + }, + .window[1] = { + .type = SOF_IPC_REGION_DOWNBOX, + .id = 0, /* map to host window 0 */ + .flags = 0, // TODO: set later + .size = MAILBOX_HOSTBOX_SIZE, + .offset = MAILBOX_HOSTBOX_OFFSET, + }, + .window[2] = { + .type = SOF_IPC_REGION_DEBUG, + .id = 0, /* map to host window 0 */ + .flags = 0, // TODO: set later + .size = MAILBOX_DEBUG_SIZE, + .offset = MAILBOX_DEBUG_OFFSET, + }, + .window[3] = { + .type = SOF_IPC_REGION_TRACE, + .id = 0, /* map to host window 0 */ + .flags = 0, // TODO: set later + .size = MAILBOX_TRACE_SIZE, + .offset = MAILBOX_TRACE_OFFSET, + }, +}; + static struct work_queue_timesource platform_generic_queue = { .timer = { .id = TIMER3, /* external timer */ @@ -93,6 +128,8 @@ int platform_boot_complete(uint32_t boot_message) uint64_t outbox = MAILBOX_HOST_OFFSET >> 3;
mailbox_dspbox_write(0, &ready, sizeof(ready)); + mailbox_dspbox_write(sizeof(ready), &sram_window, + sram_window.ext_hdr.hdr.size);
/* now interrupt host to tell it we are done booting */ shim_write(SHIM_IPCDL, SOF_IPC_FW_READY | outbox); diff --git a/src/platform/haswell/platform.c b/src/platform/haswell/platform.c index 5f56a05..97b38af 100644 --- a/src/platform/haswell/platform.c +++ b/src/platform/haswell/platform.c @@ -58,10 +58,6 @@ static const struct sof_ipc_fw_ready ready = { .size = sizeof(struct sof_ipc_fw_ready), }, /* dspbox is for DSP initiated IPC, hostbox is for host initiated IPC */ - .dspbox_offset = MAILBOX_HOST_OFFSET + MAILBOX_DSPBOX_OFFSET, - .hostbox_offset = MAILBOX_HOST_OFFSET + MAILBOX_HOSTBOX_OFFSET, - .dspbox_size = MAILBOX_DSPBOX_SIZE, - .hostbox_size = MAILBOX_HOSTBOX_SIZE, .version = { .build = REEF_BUILD, .minor = REEF_MINOR, @@ -73,6 +69,45 @@ static const struct sof_ipc_fw_ready ready = { /* TODO: add capabilities */ };
+#define NUM_HSW_WINDOWS 4 +static const struct sof_ipc_window sram_window = { + .ext_hdr = { + .hdr.cmd = SOF_IPC_FW_READY, + .hdr.size = sizeof(struct sof_ipc_window) + + sizeof(struct sof_ipc_window_elem) * NUM_HSW_WINDOWS, + .type = SOF_IPC_EXT_WINDOW, + }, + .num_windows = NUM_HSW_WINDOWS, + .window[0] = { + .type = SOF_IPC_REGION_UPBOX, + .id = 0, /* map to host window 0 */ + .flags = 0, // TODO: set later + .size = MAILBOX_DSPBOX_SIZE, + .offset = MAILBOX_DSPBOX_OFFSET, + }, + .window[1] = { + .type = SOF_IPC_REGION_DOWNBOX, + .id = 0, /* map to host window 0 */ + .flags = 0, // TODO: set later + .size = MAILBOX_HOSTBOX_SIZE, + .offset = MAILBOX_HOSTBOX_OFFSET, + }, + .window[2] = { + .type = SOF_IPC_REGION_DEBUG, + .id = 0, /* map to host window 0 */ + .flags = 0, // TODO: set later + .size = MAILBOX_DEBUG_SIZE, + .offset = MAILBOX_DEBUG_OFFSET, + }, + .window[3] = { + .type = SOF_IPC_REGION_TRACE, + .id = 0, /* map to host window 0 */ + .flags = 0, // TODO: set later + .size = MAILBOX_TRACE_SIZE, + .offset = MAILBOX_TRACE_OFFSET, + }, +}; + static struct work_queue_timesource platform_generic_queue = { .timer = { .id = TIMER2, /* external timer using SSP */ @@ -92,6 +127,8 @@ int platform_boot_complete(uint32_t boot_message) uint32_t outbox = MAILBOX_HOST_OFFSET >> 3;
mailbox_dspbox_write(0, &ready, sizeof(ready)); + mailbox_dspbox_write(sizeof(ready), &sram_window, + sram_window.ext_hdr.hdr.size);
/* now interrupt host to tell it we are done booting */ shim_write(SHIM_IPCD, outbox | SHIM_IPCD_BUSY);
From: Pan Xiuli xiuli.pan@linux.intel.com
Add stream region memory window into sof_ipc_window used for position update. For APL and CNL, we got a 1 page space for stream region.
Signed-off-by: Pan Xiuli xiuli.pan@linux.intel.com --- Test with: Mininow max rt5651 GP-MRB nocodec SOF master: 1693b66bb1d804ded975767cc1e5911e6ff9c93c SOF-Tool master: a02abb799405d0e4ad0d6bb46eacf6fbe958c06e https://github.com/plbossart/sound/tree/topic/sof-v4.14: 9513a73b981bc1917705671ec54402a7e21672eb
--- src/platform/apollolake/include/platform/mailbox.h | 9 ++++----- src/platform/apollolake/include/platform/memory.h | 10 ++++++++-- src/platform/apollolake/platform.c | 12 +++++++++--- src/platform/baytrail/platform.c | 9 ++++++++- src/platform/cannonlake/include/platform/mailbox.h | 9 ++++----- src/platform/cannonlake/include/platform/memory.h | 11 ++++++++--- src/platform/cannonlake/platform.c | 12 +++++++++--- src/platform/haswell/platform.c | 9 ++++++++- 8 files changed, 58 insertions(+), 23 deletions(-)
diff --git a/src/platform/apollolake/include/platform/mailbox.h b/src/platform/apollolake/include/platform/mailbox.h index c166e90..e04bdb5 100644 --- a/src/platform/apollolake/include/platform/mailbox.h +++ b/src/platform/apollolake/include/platform/mailbox.h @@ -64,15 +64,14 @@ #define MAILBOX_EXCEPTION_BASE \ (MAILBOX_SW_REG_BASE + SRAM_REG_FW_END)
+#define MAILBOX_STREAM_SIZE SRAM_STREAM_SIZE +#define MAILBOX_STREAM_BASE SRAM_STREAM_BASE +#define MAILBOX_STREAM_OFFSET SRAM_DEBUG_SIZE + /* window 1 inbox/downlink and FW registers */ #define MAILBOX_HOSTBOX_SIZE SRAM_INBOX_SIZE #define MAILBOX_HOSTBOX_BASE SRAM_INBOX_BASE
- -#define MAILBOX_STREAM_SIZE 0x200 -#define MAILBOX_STREAM_BASE \ - (MAILBOX_BASE + MAILBOX_STREAM_OFFSET) - /* window 0 */ #define MAILBOX_DSPBOX_SIZE SRAM_OUTBOX_SIZE #define MAILBOX_DSPBOX_BASE SRAM_OUTBOX_BASE diff --git a/src/platform/apollolake/include/platform/memory.h b/src/platform/apollolake/include/platform/memory.h index b4fae8e..db2f171 100644 --- a/src/platform/apollolake/include/platform/memory.h +++ b/src/platform/apollolake/include/platform/memory.h @@ -214,6 +214,8 @@ * +---------------------+----------------+-----------------------------------+ * | SRAM_DEBUG_BASE | Debug data W2 | SRAM_DEBUG_SIZE | * +---------------------+----------------+-----------------------------------+ + * | SRAM_STREAM_BASE | Stream data W2 | SRAM_STREAM_SIZE | + * +---------------------+----------------+-----------------------------------+ * | SRAM_INBOX_BASE | Inbox W1 | SRAM_INBOX_SIZE | * +---------------------+----------------+-----------------------------------+ * | SRAM_SW_REG_BASE | SW Registers W0| SRAM_SW_REG_SIZE | @@ -236,8 +238,11 @@ #define SRAM_DEBUG_BASE (SRAM_TRACE_BASE + SRAM_TRACE_SIZE) #define SRAM_DEBUG_SIZE 0x1000
+#define SRAM_STREAM_BASE (SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE) +#define SRAM_STREAM_SIZE 0x1000 + /* window 1 */ -#define SRAM_INBOX_BASE (SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE) +#define SRAM_INBOX_BASE (SRAM_STREAM_BASE + SRAM_STREAM_SIZE) #define SRAM_INBOX_SIZE 0x2000
/* window 0 */ @@ -258,7 +263,7 @@ #define HP_SRAM_WIN1_BASE SRAM_INBOX_BASE #define HP_SRAM_WIN1_SIZE SRAM_INBOX_SIZE #define HP_SRAM_WIN2_BASE SRAM_DEBUG_BASE -#define HP_SRAM_WIN2_SIZE SRAM_DEBUG_SIZE +#define HP_SRAM_WIN2_SIZE (SRAM_DEBUG_SIZE + SRAM_STREAM_SIZE) #define HP_SRAM_WIN3_BASE SRAM_TRACE_BASE #define HP_SRAM_WIN3_SIZE SRAM_TRACE_SIZE
@@ -274,6 +279,7 @@ (HP_SRAM_SIZE - \ SRAM_TRACE_SIZE - \ SRAM_DEBUG_SIZE - \ + SRAM_STREAM_SIZE - \ SRAM_INBOX_SIZE - \ SRAM_OUTBOX_SIZE - \ SRAM_SW_REG_SIZE) diff --git a/src/platform/apollolake/platform.c b/src/platform/apollolake/platform.c index 3c1d76f..ae8a854 100644 --- a/src/platform/apollolake/platform.c +++ b/src/platform/apollolake/platform.c @@ -68,7 +68,7 @@ static const struct sof_ipc_fw_ready ready = {
#define SRAM_WINDOW_HOST_OFFSET(x) (0x80000 + x * 0x20000)
-#define NUM_APL_WINDOWS 5 +#define NUM_APL_WINDOWS 6
static const struct sof_ipc_window sram_window = { .ext_hdr = { @@ -103,17 +103,23 @@ static const struct sof_ipc_window sram_window = { .type = SOF_IPC_REGION_DEBUG, .id = 2, /* map to host window 2 */ .flags = 0, // TODO: set later - .size = SRAM_DEBUG_SIZE, + .size = MAILBOX_EXCEPTION_SIZE + MAILBOX_DEBUG_SIZE, .offset = 0, }, .window[4] = { + .type = SOF_IPC_REGION_STREAM, + .id = 2, /* map to host window 2 */ + .flags = 0, // TODO: set later + .size = MAILBOX_STREAM_SIZE, + .offset = MAILBOX_STREAM_OFFSET, + }, + .window[5] = { .type = SOF_IPC_REGION_TRACE, .id = 3, /* map to host window 3 */ .flags = 0, // TODO: set later .size = MAILBOX_TRACE_SIZE, .offset = 0, }, - };
static struct work_queue_timesource platform_generic_queue = { diff --git a/src/platform/baytrail/platform.c b/src/platform/baytrail/platform.c index 2c4bfee..cec8297 100644 --- a/src/platform/baytrail/platform.c +++ b/src/platform/baytrail/platform.c @@ -70,7 +70,7 @@ static const struct sof_ipc_fw_ready ready = { /* TODO: add capabilities */ };
-#define NUM_BYT_WINDOWS 4 +#define NUM_BYT_WINDOWS 5 static const struct sof_ipc_window sram_window = { .ext_hdr = { .hdr.cmd = SOF_IPC_FW_READY, @@ -107,6 +107,13 @@ static const struct sof_ipc_window sram_window = { .size = MAILBOX_TRACE_SIZE, .offset = MAILBOX_TRACE_OFFSET, }, + .window[4] = { + .type = SOF_IPC_REGION_STREAM, + .id = 0, /* map to host window 0 */ + .flags = 0, // TODO: set later + .size = MAILBOX_STREAM_SIZE, + .offset = MAILBOX_STREAM_OFFSET, + }, };
static struct work_queue_timesource platform_generic_queue = { diff --git a/src/platform/cannonlake/include/platform/mailbox.h b/src/platform/cannonlake/include/platform/mailbox.h index a3c4339..c58e310 100644 --- a/src/platform/cannonlake/include/platform/mailbox.h +++ b/src/platform/cannonlake/include/platform/mailbox.h @@ -65,15 +65,14 @@ #define MAILBOX_EXCEPTION_BASE \ (MAILBOX_SW_REG_BASE + SRAM_REG_FW_END)
+#define MAILBOX_STREAM_SIZE SRAM_STREAM_SIZE +#define MAILBOX_STREAM_BASE SRAM_STREAM_BASE +#define MAILBOX_STREAM_OFFSET SRAM_DEBUG_SIZE + /* window 1 inbox/downlink and FW registers */ #define MAILBOX_HOSTBOX_SIZE SRAM_INBOX_SIZE #define MAILBOX_HOSTBOX_BASE SRAM_INBOX_BASE
- -#define MAILBOX_STREAM_SIZE 0x200 -#define MAILBOX_STREAM_BASE \ - (MAILBOX_BASE + MAILBOX_STREAM_OFFSET) - /* window 0 */ #define MAILBOX_DSPBOX_SIZE SRAM_OUTBOX_SIZE #define MAILBOX_DSPBOX_BASE SRAM_OUTBOX_BASE diff --git a/src/platform/cannonlake/include/platform/memory.h b/src/platform/cannonlake/include/platform/memory.h index 7e7af82..16e0d85 100644 --- a/src/platform/cannonlake/include/platform/memory.h +++ b/src/platform/cannonlake/include/platform/memory.h @@ -146,6 +146,8 @@ * +---------------------+----------------+-----------------------------------+ * | SRAM_DEBUG_BASE | Debug data W2 | SRAM_DEBUG_SIZE | * +---------------------+----------------+-----------------------------------+ + * | SRAM_STREAM_BASE | Stream data W2 | SRAM_STREAM_SIZE | + * +---------------------+----------------+-----------------------------------+ * | SRAM_TRACE_BASE | Trace Buffer W3| SRAM_TRACE_SIZE | * +---------------------+----------------+-----------------------------------+ * | HP_SRAM_BASE | DMA | HEAP_HP_BUFFER_SIZE | @@ -206,16 +208,19 @@ #define SRAM_DEBUG_BASE (SRAM_INBOX_BASE + SRAM_INBOX_SIZE) #define SRAM_DEBUG_SIZE 0x1000
+#define SRAM_STREAM_BASE (SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE) +#define SRAM_STREAM_SIZE 0x1000 + /* window 3 */ -#define SRAM_TRACE_BASE (SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE) +#define SRAM_TRACE_BASE (SRAM_STREAM_BASE + SRAM_STREAM_SIZE) #define SRAM_TRACE_SIZE 0x2000
#define HP_SRAM_WIN0_BASE SRAM_SW_REG_BASE #define HP_SRAM_WIN0_SIZE (SRAM_SW_REG_SIZE + SRAM_OUTBOX_SIZE) #define HP_SRAM_WIN1_BASE SRAM_INBOX_BASE #define HP_SRAM_WIN1_SIZE SRAM_INBOX_SIZE -#define HP_SRAM_WIN2_BASE SRAM_DEBUG_BASE -#define HP_SRAM_WIN2_SIZE SRAM_DEBUG_SIZE +#define HP_SRAM_WIN2_BASE SRAM_EXCEPTION_BASE +#define HP_SRAM_WIN2_SIZE (SRAM_DEBUG_SIZE + SRAM_STREAM_SIZE) #define HP_SRAM_WIN3_BASE SRAM_TRACE_BASE #define HP_SRAM_WIN3_SIZE SRAM_TRACE_SIZE
diff --git a/src/platform/cannonlake/platform.c b/src/platform/cannonlake/platform.c index beb6582..32a4454 100644 --- a/src/platform/cannonlake/platform.c +++ b/src/platform/cannonlake/platform.c @@ -70,7 +70,7 @@ static const struct sof_ipc_fw_ready ready = {
#define SRAM_WINDOW_HOST_OFFSET(x) (0x80000 + x * 0x20000)
-#define NUM_CNL_WINDOWS 5 +#define NUM_CNL_WINDOWS 6
static const struct sof_ipc_window sram_window = { .ext_hdr = { @@ -105,17 +105,23 @@ static const struct sof_ipc_window sram_window = { .type = SOF_IPC_REGION_DEBUG, .id = 2, /* map to host window 2 */ .flags = 0, // TODO: set later - .size = SRAM_DEBUG_SIZE, + .size = MAILBOX_EXCEPTION_SIZE + MAILBOX_DEBUG_SIZE, .offset = 0, }, .window[4] = { + .type = SOF_IPC_REGION_STREAM, + .id = 2, /* map to host window 2 */ + .flags = 0, // TODO: set later + .size = MAILBOX_STREAM_SIZE, + .offset = MAILBOX_STREAM_OFFSET, + }, + .window[5] = { .type = SOF_IPC_REGION_TRACE, .id = 3, /* map to host window 3 */ .flags = 0, // TODO: set later .size = MAILBOX_TRACE_SIZE, .offset = 0, }, - };
static struct work_queue_timesource platform_generic_queue = { diff --git a/src/platform/haswell/platform.c b/src/platform/haswell/platform.c index 97b38af..95d80f8 100644 --- a/src/platform/haswell/platform.c +++ b/src/platform/haswell/platform.c @@ -69,7 +69,7 @@ static const struct sof_ipc_fw_ready ready = { /* TODO: add capabilities */ };
-#define NUM_HSW_WINDOWS 4 +#define NUM_HSW_WINDOWS 5 static const struct sof_ipc_window sram_window = { .ext_hdr = { .hdr.cmd = SOF_IPC_FW_READY, @@ -106,6 +106,13 @@ static const struct sof_ipc_window sram_window = { .size = MAILBOX_TRACE_SIZE, .offset = MAILBOX_TRACE_OFFSET, }, + .window[4] = { + .type = SOF_IPC_REGION_STREAM, + .id = 0, /* map to host window 0 */ + .flags = 0, // TODO: set later + .size = MAILBOX_STREAM_SIZE, + .offset = MAILBOX_STREAM_OFFSET, + }, };
static struct work_queue_timesource platform_generic_queue = {
From: Pan Xiuli xiuli.pan@linux.intel.com
Add memeory window for stream region. And position offset binding for component. Replace IPC position update with memory window update.
Signed-off-by: Pan Xiuli xiuli.pan@linux.intel.com --- Test with: Mininow max rt5651 GP-MRB nocodec SOF master: 1693b66bb1d804ded975767cc1e5911e6ff9c93c SOF-Tool master: a02abb799405d0e4ad0d6bb46eacf6fbe958c06e https://github.com/plbossart/sound/tree/topic/sof-v4.14: 9513a73b981bc1917705671ec54402a7e21672eb
--- src/include/reef/audio/pipeline.h | 3 +++ src/include/reef/ipc.h | 5 +++++ src/include/reef/mailbox.h | 7 +++++++ src/ipc/intel-ipc.c | 43 +++++++++++++++++++++++++++++---------- src/ipc/ipc.c | 25 +++++++++++++++++++++++ 5 files changed, 72 insertions(+), 11 deletions(-)
diff --git a/src/include/reef/audio/pipeline.h b/src/include/reef/audio/pipeline.h index 08a3f30..dca9413 100644 --- a/src/include/reef/audio/pipeline.h +++ b/src/include/reef/audio/pipeline.h @@ -69,6 +69,9 @@ struct pipeline { struct task pipe_task; /* pipeline processing task */ struct comp_dev *sched_comp; /* component that drives scheduling in this pipe */ struct comp_dev *source_comp; /* source component for this pipe */ + + /* position update */ + uint32_t posn_offset; /* position update array offset*/ };
/* static pipeline */ diff --git a/src/include/reef/ipc.h b/src/include/reef/ipc.h index 9261add..58d1f29 100644 --- a/src/include/reef/ipc.h +++ b/src/include/reef/ipc.h @@ -103,6 +103,9 @@ struct ipc { /* DMA for Trace*/ struct dma_trace_data *dmat;
+ /* mmap for posn_offset */ + struct pipeline *posn_map[PLATFORM_MAX_STREAMS]; + void *private; };
@@ -169,4 +172,6 @@ int ipc_comp_dai_config(struct ipc *ipc, struct sof_ipc_dai_config *config); /* send DMA trace host buffer position to host */ int ipc_dma_trace_send_position(void);
+/* get posn offset by pipeline. */ +int ipc_get_posn_offset(struct ipc *ipc, struct pipeline *pipe); #endif diff --git a/src/include/reef/mailbox.h b/src/include/reef/mailbox.h index c0580a9..f134548 100644 --- a/src/include/reef/mailbox.h +++ b/src/include/reef/mailbox.h @@ -78,4 +78,11 @@ dcache_invalidate_region((void*)(MAILBOX_HOSTBOX_BASE + src), bytes); \ rmemcpy(dest, (void*)(MAILBOX_HOSTBOX_BASE + src), bytes);
+#define mailbox_stream_write(dest, src, bytes) \ + do { \ + rmemcpy((void *)(MAILBOX_STREAM_BASE + dest), src, bytes); \ + dcache_writeback_region((void *)(MAILBOX_STREAM_BASE + dest), \ + bytes); \ + } while (0) + #endif diff --git a/src/ipc/intel-ipc.c b/src/ipc/intel-ipc.c index 04e8c1b..8b77219 100644 --- a/src/ipc/intel-ipc.c +++ b/src/ipc/intel-ipc.c @@ -237,7 +237,7 @@ static int ipc_stream_pcm_params(uint32_t stream) struct sof_ipc_pcm_params_reply reply; struct ipc_comp_dev *pcm_dev; struct comp_dev *cd; - int err; + int err, posn_offset;
trace_ipc("SAl");
@@ -291,13 +291,17 @@ static int ipc_stream_pcm_params(uint32_t stream) goto error; }
- + posn_offset = ipc_get_posn_offset(_ipc, pcm_dev->cd->pipeline); + if (posn_offset < 0) { + trace_ipc_error("eAo"); + goto error; + } /* write component values to the outbox */ reply.rhdr.hdr.size = sizeof(reply); reply.rhdr.hdr.cmd = stream; reply.rhdr.error = 0; reply.comp_id = pcm_params->comp_id; - reply.posn_offset = 0; /* TODO: set this up for mmaped components */ + reply.posn_offset = posn_offset; mailbox_hostbox_write(0, &reply, sizeof(reply)); return 1;
@@ -353,15 +357,18 @@ static int ipc_stream_position(uint32_t header) }
/* set message fields - TODO; get others */ - posn.rhdr.hdr.cmd = SOF_IPC_GLB_STREAM_MSG | SOF_IPC_STREAM_POSITION; + posn.rhdr.hdr.cmd = SOF_IPC_GLB_STREAM_MSG | SOF_IPC_STREAM_POSITION | + stream->comp_id; posn.rhdr.hdr.size = sizeof(posn); posn.comp_id = stream->comp_id;
/* get the stream positions and timestamps */ pipeline_get_timestamp(pcm_dev->cd->pipeline, pcm_dev->cd, &posn);
- /* copy positions to outbox */ - mailbox_hostbox_write(0, &posn, sizeof(posn)); + /* copy positions to stream region */ + mailbox_stream_write(pcm_dev->cd->pipeline->posn_offset, + &posn, sizeof(posn)); + return 1; }
@@ -369,24 +376,38 @@ static int ipc_stream_position(uint32_t header) int ipc_stream_send_position(struct comp_dev *cdev, struct sof_ipc_stream_posn *posn) { - posn->rhdr.hdr.cmd = SOF_IPC_GLB_STREAM_MSG | SOF_IPC_STREAM_POSITION; + struct sof_ipc_hdr hdr; + + tracev_ipc("Pos"); + posn->rhdr.hdr.cmd = SOF_IPC_GLB_STREAM_MSG | SOF_IPC_STREAM_POSITION | + cdev->comp.id; posn->rhdr.hdr.size = sizeof(*posn); posn->comp_id = cdev->comp.id;
- return ipc_queue_host_message(_ipc, posn->rhdr.hdr.cmd, posn, - sizeof(*posn), NULL, 0, NULL, NULL, 1); + hdr.cmd = posn->rhdr.hdr.cmd; + hdr.size = sizeof(hdr); + + mailbox_stream_write(cdev->pipeline->posn_offset, posn, sizeof(*posn)); + return ipc_queue_host_message(_ipc, posn->rhdr.hdr.cmd, &hdr, + sizeof(hdr), NULL, 0, NULL, NULL, 0); }
/* send stream position TODO: send compound message */ int ipc_stream_send_xrun(struct comp_dev *cdev, struct sof_ipc_stream_posn *posn) { + struct sof_ipc_hdr hdr; + posn->rhdr.hdr.cmd = SOF_IPC_GLB_STREAM_MSG | SOF_IPC_STREAM_TRIG_XRUN; posn->rhdr.hdr.size = sizeof(*posn); posn->comp_id = cdev->comp.id;
- return ipc_queue_host_message(_ipc, posn->rhdr.hdr.cmd, posn, - sizeof(*posn), NULL, 0, NULL, NULL, 1); + hdr.cmd = posn->rhdr.hdr.cmd; + hdr.size = sizeof(hdr); + + mailbox_stream_write(cdev->pipeline->posn_offset, posn, sizeof(*posn)); + return ipc_queue_host_message(_ipc, posn->rhdr.hdr.cmd, &hdr, + sizeof(hdr), NULL, 0, NULL, NULL, 0); }
static int ipc_stream_trigger(uint32_t header) diff --git a/src/ipc/ipc.c b/src/ipc/ipc.c index b753efd..898a69e 100644 --- a/src/ipc/ipc.c +++ b/src/ipc/ipc.c @@ -77,6 +77,27 @@ struct ipc_comp_dev *ipc_get_comp(struct ipc *ipc, uint32_t id) return NULL; }
+int ipc_get_posn_offset(struct ipc *ipc, struct pipeline *pipe) +{ + int i; + uint32_t posn_size = sizeof(struct sof_ipc_stream_posn); + + for (i = 0; i < PLATFORM_MAX_STREAMS; i++) { + if (ipc->posn_map[i] == pipe) + return pipe->posn_offset; + } + + for (i = 0; i < PLATFORM_MAX_STREAMS; i++) { + if (ipc->posn_map[i] == NULL) { + ipc->posn_map[i] = pipe; + pipe->posn_offset = i * posn_size; + return pipe->posn_offset; + } + } + + return -EINVAL; +} + int ipc_comp_new(struct ipc *ipc, struct sof_ipc_comp *comp) { struct comp_dev *cd; @@ -345,6 +366,7 @@ int ipc_comp_dai_config(struct ipc *ipc, struct sof_ipc_dai_config *config)
int ipc_init(struct reef *reef) { + int i; trace_ipc("IPI");
/* init ipc data */ @@ -352,6 +374,9 @@ int ipc_init(struct reef *reef) reef->ipc->comp_data = rzalloc(RZONE_SYS, RFLAGS_NONE, SOF_IPC_MSG_MAX_SIZE); reef->ipc->dmat = reef->dmat;
+ for (i = 0; i < PLATFORM_MAX_STREAMS; i++) + reef->ipc->posn_map[i] = NULL; + list_init(&reef->ipc->comp_list);
return platform_ipc_init(reef->ipc);
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Xiuli Pan