For memory to memory copy, we don't require user to set msize, and set them to default 3, that is 2^3=8 items for each burst transaction.

For copy have peripheral device source/destination, we use the user configured src_msize and dest_msize, which usually be constrained by device hardware/fifos.

Signed-off-by: Keyon Jie yang.jie@linux.intel.com --- src/drivers/dw-dma.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/src/drivers/dw-dma.c b/src/drivers/dw-dma.c index a28281a..958a659 100644 --- a/src/drivers/dw-dma.c +++ b/src/drivers/dw-dma.c @@ -518,8 +518,6 @@ static int dw_dma_set_config(struct dma *dma, int channel, goto out; }

- lli_desc->ctrl_lo |= DW_CTLL_SRC_MSIZE(3); /* config the src msize length 2^2 */ - lli_desc->ctrl_lo |= DW_CTLL_DST_MSIZE(3); /* config the dest msize length 2^2 */ lli_desc->ctrl_lo |= DW_CTLL_INT_EN; /* enable interrupt */

/* config the SINC and DINC field of CTL_LOn, SRC/DST_PER filed of CFGn */ @@ -530,6 +528,8 @@ static int dw_dma_set_config(struct dma *dma, int channel, lli_desc->sar = (uint32_t)sg_elem->src | PLATFORM_HOST_DMA_MASK; lli_desc->dar = (uint32_t)sg_elem->dest; + lli_desc->ctrl_lo |= DW_CTLL_SRC_MSIZE(3); /* 2^3 items */ + lli_desc->ctrl_lo |= DW_CTLL_DST_MSIZE(3); /* 2^3 items */ break; case DMA_DIR_HMEM_TO_LMEM: lli_desc->ctrl_lo |= DW_CTLL_FC_M2M; @@ -537,12 +537,16 @@ static int dw_dma_set_config(struct dma *dma, int channel, lli_desc->dar = (uint32_t)sg_elem->dest | PLATFORM_HOST_DMA_MASK; lli_desc->sar = (uint32_t)sg_elem->src; + lli_desc->ctrl_lo |= DW_CTLL_SRC_MSIZE(3); /* 2^3 items */ + lli_desc->ctrl_lo |= DW_CTLL_DST_MSIZE(3); /* 2^3 items */ break; case DMA_DIR_MEM_TO_MEM: lli_desc->ctrl_lo |= DW_CTLL_FC_M2M; lli_desc->ctrl_lo |= DW_CTLL_SRC_INC | DW_CTLL_DST_INC; lli_desc->sar = (uint32_t)sg_elem->src | PLATFORM_HOST_DMA_MASK; lli_desc->dar = (uint32_t)sg_elem->dest | PLATFORM_HOST_DMA_MASK; + lli_desc->ctrl_lo |= DW_CTLL_SRC_MSIZE(3); /* 2^3 items */ + lli_desc->ctrl_lo |= DW_CTLL_DST_MSIZE(3); /* 2^3 items */ break; case DMA_DIR_MEM_TO_DEV: lli_desc->ctrl_lo |= DW_CTLL_FC_M2P; @@ -551,6 +555,8 @@ static int dw_dma_set_config(struct dma *dma, int channel, DW_CFGH_DST_PER(config->dest_dev); lli_desc->sar = (uint32_t)sg_elem->src | PLATFORM_HOST_DMA_MASK; lli_desc->dar = (uint32_t)sg_elem->dest; + lli_desc->ctrl_lo |= DW_CTLL_SRC_MSIZE(config->src_msize); + lli_desc->ctrl_lo |= DW_CTLL_DST_MSIZE(config->dest_msize); break; case DMA_DIR_DEV_TO_MEM: lli_desc->ctrl_lo |= DW_CTLL_FC_P2M; @@ -559,6 +565,8 @@ static int dw_dma_set_config(struct dma *dma, int channel, DW_CFGH_SRC_PER(config->src_dev); lli_desc->sar = (uint32_t)sg_elem->src; lli_desc->dar = (uint32_t)sg_elem->dest | PLATFORM_HOST_DMA_MASK; + lli_desc->ctrl_lo |= DW_CTLL_SRC_MSIZE(config->src_msize); + lli_desc->ctrl_lo |= DW_CTLL_DST_MSIZE(config->dest_msize); break; case DMA_DIR_DEV_TO_DEV: lli_desc->ctrl_lo |= DW_CTLL_FC_P2P; @@ -568,6 +576,8 @@ static int dw_dma_set_config(struct dma *dma, int channel, DW_CFGH_DST_PER(config->dest_dev); lli_desc->sar = (uint32_t)sg_elem->src; lli_desc->dar = (uint32_t)sg_elem->dest; + lli_desc->ctrl_lo |= DW_CTLL_SRC_MSIZE(config->src_msize); + lli_desc->ctrl_lo |= DW_CTLL_DST_MSIZE(config->dest_msize); break; default: trace_dma_error("eD4");