On 2/25/19 8:35 AM, Dragos Tarcatu wrote:

alsatplg allows setting inverted bclk and fsync polarities by setting either bclk_invert or fsync_invert to "true". This patch adds a default parameter in the SSP_CLOCK m4 macro which allows setting inverted bclk and fsync polarities.

Signed-off-by: Dragos Tarcatu dragos_tarcatu@mentor.com

The change looks ok, I had a similar fix a long time ago and never upstreamed it... we'll also need to add support for missing Intel quirks that the firmware supports but neither topology or kernel do.

since the patch handling is now mostly on github, would you mind creating a Pull Request here: https://github.com/thesofproject/sof/pulls

Thanks!

---

tools/topology/platform/common/ssp.m4 | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/tools/topology/platform/common/ssp.m4 b/tools/topology/platform/common/ssp.m4 index f3c7862..76b2766 100644 --- a/tools/topology/platform/common/ssp.m4 +++ b/tools/topology/platform/common/ssp.m4 @@ -2,11 +2,12 @@ divert(-1)

dnl SSP related macros

-dnl SSP_CLOCK(clock, freq, codec_master) +dnl SSP_CLOCK(clock, freq, codec_master, polarity) +dnl polarity is optional define(`SSP_CLOCK', $1 STR($3)

• $1_freq STR($2))

• $1_freq STR($2)

• `ifelse($4, `inverted', `$1_invert "true"',`')')

  dnl SSP_TDM(slots, width, tx_mask, rx_mask) define(`SSP_TDM',