[Sound-open-firmware] [PATCH 0/3] Use correct clock values
Copy-pastes left uncorrected...
Still TODO for CNL/APL: 1. use SSP for workqueues 2. match external timer with MCLK value from topology (not sure how).
Pierre-Louis Bossart (3): clk: fix ApolloLake SSP clock values clk: fix CNL clk allocation platform: cnl: fix clock settings
src/platform/apollolake/clk.c | 3 +-- src/platform/cannonlake/clk.c | 2 +- src/platform/cannonlake/platform.c | 4 ++-- 3 files changed, 4 insertions(+), 5 deletions(-)
24.576, not 24.0 MHz
Signed-off-by: Pierre-Louis Bossart pierre-louis.bossart@linux.intel.com --- src/platform/apollolake/clk.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/src/platform/apollolake/clk.c b/src/platform/apollolake/clk.c index 32d3236..555caae 100644 --- a/src/platform/apollolake/clk.c +++ b/src/platform/apollolake/clk.c @@ -72,11 +72,10 @@ static const struct freq_table cpu_freq[] = {
/* * XTAL clock, used as Wall Clock(external timer), - * 19.2M for Atom and 24M for core */ static const struct freq_table ssp_freq[] = { {19200000, 19,}, /* default */ - {24000000, 24,}, + {24576000, 24,}, };
#define CPU_DEFAULT_IDX 2
On 2018年03月07日 08:07, Pierre-Louis Bossart wrote:
24.576, not 24.0 MHz
Signed-off-by: Pierre-Louis Bossart pierre-louis.bossart@linux.intel.com
src/platform/apollolake/clk.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/src/platform/apollolake/clk.c b/src/platform/apollolake/clk.c index 32d3236..555caae 100644 --- a/src/platform/apollolake/clk.c +++ b/src/platform/apollolake/clk.c @@ -72,11 +72,10 @@ static const struct freq_table cpu_freq[] = {
/*
- XTAL clock, used as Wall Clock(external timer),
*/ static const struct freq_table ssp_freq[] = { {19200000, 19,}, /* default */
- 19.2M for Atom and 24M for core
- {24000000, 24,},
- {24576000, 24,},
I am not sure if this is correct. For historical reason, here we use it for work queue timer but not SSP related actually, detail to APL, it is the frequency of Wall Clock, I verified it is 19.2M for Atom(e.g. GPMRB) and heard from Seppo that it is 24M on core(I haven't verified it yet).
Thanks, ~Keyon
};
#define CPU_DEFAULT_IDX 2
On 03/06/2018 08:06 PM, Keyon Jie wrote:
On 2018年03月07日 08:07, Pierre-Louis Bossart wrote:
24.576, not 24.0 MHz
Signed-off-by: Pierre-Louis Bossart
pierre-louis.bossart@linux.intel.com
src/platform/apollolake/clk.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/src/platform/apollolake/clk.c b/src/platform/apollolake/clk.c index 32d3236..555caae 100644 --- a/src/platform/apollolake/clk.c +++ b/src/platform/apollolake/clk.c @@ -72,11 +72,10 @@ static const struct freq_table cpu_freq[] = { /* * XTAL clock, used as Wall Clock(external timer),
- 19.2M for Atom and 24M for core
*/ static const struct freq_table ssp_freq[] = { {19200000, 19,}, /* default */ - {24000000, 24,}, + {24576000, 24,},
I am not sure if this is correct. For historical reason, here we use it for work queue timer but not SSP related actually, detail to APL, it is the frequency of Wall Clock, I verified it is 19.2M for Atom(e.g. GPMRB) and heard from Seppo that it is 24M on core(I haven't verified it yet).
this is for ApolloLake only, and 24MHz does not exist at all. 24.576 is the output of the PLL, whether this is usable or not as wall clock is a separate story. If not then let's remove this value completely. For CNL there is a different table in src/platform/cannonlake.c.
Thanks, ~Keyon
}; #define CPU_DEFAULT_IDX 2
All other platforms use RZONE_SYS, not sure why CannonLake should be any different.
Signed-off-by: Pierre-Louis Bossart pierre-louis.bossart@linux.intel.com --- src/platform/cannonlake/clk.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/platform/cannonlake/clk.c b/src/platform/cannonlake/clk.c index f27e691..02cfc68 100644 --- a/src/platform/cannonlake/clk.c +++ b/src/platform/cannonlake/clk.c @@ -191,7 +191,7 @@ uint64_t clock_time_elapsed(int clock, uint64_t previous, uint64_t *current)
void init_platform_clocks(void) { - clk_pdata = rmalloc(RZONE_RUNTIME, SOF_MEM_CAPS_RAM, + clk_pdata = rmalloc(RZONE_SYS, SOF_MEM_CAPS_RAM, sizeof(*clk_pdata));
spinlock_init(&clk_pdata->clk[0].lock);
25MHz is not supported, use 24MHz
Signed-off-by: Pierre-Louis Bossart pierre-louis.bossart@linux.intel.com --- src/platform/cannonlake/platform.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/platform/cannonlake/platform.c b/src/platform/cannonlake/platform.c index 32a4454..c2d1c0b 100644 --- a/src/platform/cannonlake/platform.c +++ b/src/platform/cannonlake/platform.c @@ -233,9 +233,9 @@ int platform_init(struct reef *reef) trace_point(TRACE_BOOT_SYS_CPU_FREQ); clock_set_freq(CLK_CPU, CLK_MAX_CPU_HZ);
- /* set SSP clock to 25M */ + /* set SSP clock to 24M */ trace_point(TRACE_BOOT_PLATFORM_SSP_FREQ); - clock_set_freq(CLK_SSP, 25000000); + clock_set_freq(CLK_SSP, 24000000);
/* initialise the host IPC mechanisms */ trace_point(TRACE_BOOT_PLATFORM_IPC);
On Tue, 2018-03-06 at 18:07 -0600, Pierre-Louis Bossart wrote:
Copy-pastes left uncorrected...
Still TODO for CNL/APL:
- use SSP for workqueues
- match external timer with MCLK value from topology (not sure how).
Pierre-Louis Bossart (3): clk: fix ApolloLake SSP clock values clk: fix CNL clk allocation platform: cnl: fix clock settings
src/platform/apollolake/clk.c | 3 +-- src/platform/cannonlake/clk.c | 2 +- src/platform/cannonlake/platform.c | 4 ++-- 3 files changed, 4 insertions(+), 5 deletions(-)
All Applied.
Thanks
Liam
participants (3)
-
Keyon Jie -
Liam Girdwood -
Pierre-Louis Bossart