10 May
2018
10 May
'18
10:37 p.m.
On Thu, 2018-05-10 at 13:32 +0800, Rander Wang wrote:
The issue for original data structure and algorithm is that: (1)it only support 2 level interrupt architecture. (2)it doesn't support two HW interrupt triggered by one irq pin.
Unify irq parent and child to irq_desc. Now each irq_desc maybe directly attach to xtensa core or another irq_desc.Each irq_desc may have 32 child list instead of 32 child.
V2: check whether memory allocation failed V3: remove useless declaration in interrupt.h
Applied, but squashed to preserve bisection.
Thanks
Liam