For CNL or later chips, a group of HW IP(like GP-DMA) share the same IRQ value. Now add id in IRQ to identify each HW interrupt. If no IRQ shared, call SOF_IRQ to get the IRQ value, and the default id value would be zero. otherwise call SOF_ID_IRQ to record its id in IRQ value.
Signed-off-by: Rander Wang rander.wang@linux.intel.com --- src/include/sof/interrupt-map.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)
diff --git a/src/include/sof/interrupt-map.h b/src/include/sof/interrupt-map.h index bea567a..cec85df 100644 --- a/src/include/sof/interrupt-map.h +++ b/src/include/sof/interrupt-map.h @@ -33,6 +33,7 @@
#include <config.h>
+#define SOF_IRQ_ID_SHIFT 29 #define SOF_IRQ_BIT_SHIFT 24 #define SOF_IRQ_LEVEL_SHIFT 16 #define SOF_IRQ_CPU_SHIFT 8 @@ -41,6 +42,7 @@ #define SOF_IRQ_LEVEL_MASK 0xff #define SOF_IRQ_BIT_MASK 0x1f #define SOF_IRQ_CPU_MASK 0xff +#define SOF_IRQ_ID_MASK 0x7
#define SOF_IRQ(_bit, _level, _cpu, _number) \ (((_bit) << SOF_IRQ_BIT_SHIFT) \ @@ -48,6 +50,18 @@ | ((_cpu) << SOF_IRQ_CPU_SHIFT) \ | ((_number) << SOF_IRQ_NUM_SHIFT))
+/* + * for chip CNL or later, a group of HW IP(GP-DMA) share + * the same IRQ. So add id in IRQ to identify each HW IP + * for this case, it will be 5 levels + */ +#define SOF_ID_IRQ(_id, _bit, _level, _cpu, _number) \ + (((_id) << SOF_IRQ_ID_SHIFT) \ + | ((_bit) << SOF_IRQ_BIT_SHIFT) \ + | ((_level) << SOF_IRQ_LEVEL_SHIFT) \ + | ((_cpu) << SOF_IRQ_CPU_SHIFT) \ + | ((_number) << SOF_IRQ_NUM_SHIFT)) + #ifdef CONFIG_IRQ_MAP /* * IRQs are mapped on 4 levels. @@ -65,6 +79,8 @@ (((_bit) >> SOF_IRQ_BIT_SHIFT) & SOF_IRQ_BIT_MASK) #define SOF_IRQ_CPU(_cpu) \ (((_cpu) >> SOF_IRQ_CPU_SHIFT) & SOF_IRQ_CPU_MASK) +#define SOF_IRQ_ID(_bit) \ + (((_bit) >> SOF_IRQ_ID_SHIFT) & SOF_IRQ_ID_MASK) #else /* * IRQs are directly mapped onto a single level, bit and level. @@ -73,6 +89,7 @@ #define SOF_IRQ_LEVEL(_level) 0 #define SOF_IRQ_BIT(_bit) 0 #define SOF_IRQ_CPU(_cpu) 0 +#define SOF_IRQ_ID(_bit) 0 #endif
#endif