On Mon, Feb 11, 2019 at 11:30 PM Pierre-Louis Bossart pierre-louis.bossart@linux.intel.com wrote:
On 2/11/19 2:58 PM, Daniel Baluta wrote:
Hi all,
First of all I'm now in the phase where I only need to implement the DMA driver for i.MX and create the topology file.
Few questions:
- Is there any simple scenario (topology file) where I could test
that scheduling, ipc, pipelines, etc works without the DMA?
DMA is a loaded term for intel folks, depending on the skews we use either the same DMA controller for host memory <-> internal DSP memory and internal memory <-> audio peripherals.
Are you missing the first, the second or both? the information would help provide guidance on what topologies you can try to use.
Both for the moment.
host memory <-> internal DSP memory, I don't think we have something like this. Both host and DSP have access to a big chunk of shared SDRAM.
internal memory <-> audio peripheral, we have a DMA controller here but I would expect to take me some time to write the driver for this.
It is my first time using topology and I'm still yet to get around the m4 topology description.
In simple cases it may be easier to work directly with an alsaconf format. M4 is mostly there for reuse of configurations, it's not always readable or concise...
Good to know. Will try.
- Is there any design document for the SOF architecture. I'm still
yet to understand how components and scheduler interact.
Mostly by the definition of priorities and rates.
Thanks!