From: Pan Xiuli xiuli.pan@linux.intel.com
Add sof_ipc_window for all platforms, and add IPC send after boot compelted. Also remove the deprecated ready window.
Signed-off-by: Pan Xiuli xiuli.pan@linux.intel.com
--- Test with: Mininow max rt5651 SOF master: 019637ab250daa53c15da0a0a98c54f1c58d8ca3 SOF-Tool master: 33e4b0cc6f6a44e3e7ee849c04c515a5537242c7 https://github.com/plbossart/sound/tree/topic/sof-v4.14: 6fa721a8b7c6567eea0a2181bf9a3d2a12c31b00 --- src/platform/baytrail/platform.c | 45 ++++++++++++++++++++++++++++++++++++---- src/platform/haswell/platform.c | 45 ++++++++++++++++++++++++++++++++++++---- 2 files changed, 82 insertions(+), 8 deletions(-)
diff --git a/src/platform/baytrail/platform.c b/src/platform/baytrail/platform.c index 3114ac1..6d08e47 100644 --- a/src/platform/baytrail/platform.c +++ b/src/platform/baytrail/platform.c @@ -59,10 +59,6 @@ static const struct sof_ipc_fw_ready ready = { .size = sizeof(struct sof_ipc_fw_ready), }, /* dspbox is for DSP initiated IPC, hostbox is for host initiated IPC */ - .dspbox_offset = MAILBOX_HOST_OFFSET + MAILBOX_DSPBOX_OFFSET, - .hostbox_offset = MAILBOX_HOST_OFFSET + MAILBOX_HOSTBOX_OFFSET, - .dspbox_size = MAILBOX_DSPBOX_SIZE, - .hostbox_size = MAILBOX_HOSTBOX_SIZE, .version = { .build = REEF_BUILD, .minor = REEF_MINOR, @@ -74,6 +70,45 @@ static const struct sof_ipc_fw_ready ready = { /* TODO: add capabilities */ };
+#define NUM_BYT_WINDOWS 4 +static const struct sof_ipc_window sram_window = { + .ext_hdr = { + .hdr.cmd = SOF_IPC_FW_READY, + .hdr.size = sizeof(struct sof_ipc_window) + + sizeof(struct sof_ipc_window_elem) * NUM_BYT_WINDOWS, + .type = SOF_IPC_EXT_WINDOW, + }, + .num_windows = NUM_BYT_WINDOWS, + .window[0] = { + .type = SOF_IPC_REGION_UPBOX, + .id = 0, /* map to host window 0 */ + .flags = 0, // TODO: set later + .size = MAILBOX_DSPBOX_SIZE, + .offset = MAILBOX_DSPBOX_OFFSET, + }, + .window[1] = { + .type = SOF_IPC_REGION_DOWNBOX, + .id = 0, /* map to host window 0 */ + .flags = 0, // TODO: set later + .size = MAILBOX_HOSTBOX_SIZE, + .offset = MAILBOX_HOSTBOX_OFFSET, + }, + .window[2] = { + .type = SOF_IPC_REGION_DEBUG, + .id = 0, /* map to host window 0 */ + .flags = 0, // TODO: set later + .size = MAILBOX_DEBUG_SIZE, + .offset = MAILBOX_DEBUG_OFFSET, + }, + .window[3] = { + .type = SOF_IPC_REGION_TRACE, + .id = 0, /* map to host window 0 */ + .flags = 0, // TODO: set later + .size = MAILBOX_TRACE_SIZE, + .offset = MAILBOX_TRACE_OFFSET, + }, +}; + static struct work_queue_timesource platform_generic_queue = { .timer = { .id = TIMER3, /* external timer */ @@ -93,6 +128,8 @@ int platform_boot_complete(uint32_t boot_message) uint64_t outbox = MAILBOX_HOST_OFFSET >> 3;
mailbox_dspbox_write(0, &ready, sizeof(ready)); + mailbox_dspbox_write(sizeof(ready), &sram_window, + sram_window.ext_hdr.hdr.size);
/* now interrupt host to tell it we are done booting */ shim_write(SHIM_IPCDL, SOF_IPC_FW_READY | outbox); diff --git a/src/platform/haswell/platform.c b/src/platform/haswell/platform.c index 1b82464..2ed3d50 100644 --- a/src/platform/haswell/platform.c +++ b/src/platform/haswell/platform.c @@ -58,10 +58,6 @@ static const struct sof_ipc_fw_ready ready = { .size = sizeof(struct sof_ipc_fw_ready), }, /* dspbox is for DSP initiated IPC, hostbox is for host initiated IPC */ - .dspbox_offset = MAILBOX_HOST_OFFSET + MAILBOX_DSPBOX_OFFSET, - .hostbox_offset = MAILBOX_HOST_OFFSET + MAILBOX_HOSTBOX_OFFSET, - .dspbox_size = MAILBOX_DSPBOX_SIZE, - .hostbox_size = MAILBOX_HOSTBOX_SIZE, .version = { .build = REEF_BUILD, .minor = REEF_MINOR, @@ -73,6 +69,45 @@ static const struct sof_ipc_fw_ready ready = { /* TODO: add capabilities */ };
+#define NUM_HSW_WINDOWS 4 +static const struct sof_ipc_window sram_window = { + .ext_hdr = { + .hdr.cmd = SOF_IPC_FW_READY, + .hdr.size = sizeof(struct sof_ipc_window) + + sizeof(struct sof_ipc_window_elem) * NUM_HSW_WINDOWS, + .type = SOF_IPC_EXT_WINDOW, + }, + .num_windows = NUM_HSW_WINDOWS, + .window[0] = { + .type = SOF_IPC_REGION_UPBOX, + .id = 0, /* map to host window 0 */ + .flags = 0, // TODO: set later + .size = MAILBOX_DSPBOX_SIZE, + .offset = MAILBOX_DSPBOX_OFFSET, + }, + .window[1] = { + .type = SOF_IPC_REGION_DOWNBOX, + .id = 0, /* map to host window 0 */ + .flags = 0, // TODO: set later + .size = MAILBOX_HOSTBOX_SIZE, + .offset = MAILBOX_HOSTBOX_OFFSET, + }, + .window[2] = { + .type = SOF_IPC_REGION_DEBUG, + .id = 0, /* map to host window 0 */ + .flags = 0, // TODO: set later + .size = MAILBOX_DEBUG_SIZE, + .offset = MAILBOX_DEBUG_OFFSET, + }, + .window[3] = { + .type = SOF_IPC_REGION_TRACE, + .id = 0, /* map to host window 0 */ + .flags = 0, // TODO: set later + .size = MAILBOX_TRACE_SIZE, + .offset = MAILBOX_TRACE_OFFSET, + }, +}; + static struct work_queue_timesource platform_generic_queue = { .timer = { .id = TIMER0, /* external timer using SSP */ @@ -92,6 +127,8 @@ int platform_boot_complete(uint32_t boot_message) uint64_t outbox = MAILBOX_HOST_OFFSET >> 3;
mailbox_dspbox_write(0, &ready, sizeof(ready)); + mailbox_dspbox_write(sizeof(ready), &sram_window, + sram_window.ext_hdr.hdr.size);
/* now interrupt host to tell it we are done booting */ shim_write(SHIM_IPCD, outbox | SHIM_IPCD_BUSY);