The issues for original data structure and algorithm are: (1)it only supports 2 level interrupt architecture. (2)it doesn't support different HW interrupt shares one IRQ value. (3)it doesn't support multi-core.
The refinement is based on the prototype provided by Liam. refine irq data structure to make it support more than 2 level and issue(2). Add multi-core support in interrupt setting
test on CNL & APL & BYT, pass SOF: master c1f2682c210201 kernel: v4.14 d09db67c5a9d6d SOF-tools: master 13b56fa6047c566a
Rander Wang (7): interrupt: refine irq structure and algorithm interrupt: add irq id in IRQ cnl-interrupt: refine interrupt setting for change in irq_desc cnl-dma: remove special dma code for cnl apl-interrupt: refine interrupt code according to interrupt change byt-interrupt: port irq change to byt hsw-interrupt: port irq change to hsw
src/drivers/dw-dma.c | 32 +-- src/include/sof/interrupt-map.h | 17 ++ src/include/sof/interrupt.h | 32 +-- src/lib/interrupt.c | 120 +++++------ .../apollolake/include/platform/interrupt.h | 2 +- src/platform/apollolake/include/platform/memory.h | 4 +- .../apollolake/include/platform/platform.h | 2 + src/platform/apollolake/interrupt.c | 210 ++++++++++++-------- src/platform/baytrail/include/platform/interrupt.h | 2 +- src/platform/cannonlake/dma.c | 2 +- .../cannonlake/include/platform/interrupt.h | 16 +- src/platform/cannonlake/include/platform/memory.h | 2 +- .../cannonlake/include/platform/platform.h | 2 + src/platform/cannonlake/interrupt.c | 220 +++++++++++++-------- src/platform/haswell/include/platform/interrupt.h | 2 +- 15 files changed, 382 insertions(+), 283 deletions(-)