From: Pan Xiuli xiuli.pan@linux.intel.com
Add stream region memory window into sof_ipc_window used for position update. For APL and CNL, we got a 1 page space for stream region.
Signed-off-by: Pan Xiuli xiuli.pan@linux.intel.com --- Test with: Mininow max rt5651 GP-MRB nocodec SOF master: 1693b66bb1d804ded975767cc1e5911e6ff9c93c SOF-Tool master: a02abb799405d0e4ad0d6bb46eacf6fbe958c06e https://github.com/plbossart/sound/tree/topic/sof-v4.14: 9513a73b981bc1917705671ec54402a7e21672eb
--- src/platform/apollolake/include/platform/mailbox.h | 9 ++++----- src/platform/apollolake/include/platform/memory.h | 10 ++++++++-- src/platform/apollolake/platform.c | 12 +++++++++--- src/platform/baytrail/platform.c | 9 ++++++++- src/platform/cannonlake/include/platform/mailbox.h | 9 ++++----- src/platform/cannonlake/include/platform/memory.h | 11 ++++++++--- src/platform/cannonlake/platform.c | 12 +++++++++--- src/platform/haswell/platform.c | 9 ++++++++- 8 files changed, 58 insertions(+), 23 deletions(-)
diff --git a/src/platform/apollolake/include/platform/mailbox.h b/src/platform/apollolake/include/platform/mailbox.h index c166e90..e04bdb5 100644 --- a/src/platform/apollolake/include/platform/mailbox.h +++ b/src/platform/apollolake/include/platform/mailbox.h @@ -64,15 +64,14 @@ #define MAILBOX_EXCEPTION_BASE \ (MAILBOX_SW_REG_BASE + SRAM_REG_FW_END)
+#define MAILBOX_STREAM_SIZE SRAM_STREAM_SIZE +#define MAILBOX_STREAM_BASE SRAM_STREAM_BASE +#define MAILBOX_STREAM_OFFSET SRAM_DEBUG_SIZE + /* window 1 inbox/downlink and FW registers */ #define MAILBOX_HOSTBOX_SIZE SRAM_INBOX_SIZE #define MAILBOX_HOSTBOX_BASE SRAM_INBOX_BASE
- -#define MAILBOX_STREAM_SIZE 0x200 -#define MAILBOX_STREAM_BASE \ - (MAILBOX_BASE + MAILBOX_STREAM_OFFSET) - /* window 0 */ #define MAILBOX_DSPBOX_SIZE SRAM_OUTBOX_SIZE #define MAILBOX_DSPBOX_BASE SRAM_OUTBOX_BASE diff --git a/src/platform/apollolake/include/platform/memory.h b/src/platform/apollolake/include/platform/memory.h index b4fae8e..db2f171 100644 --- a/src/platform/apollolake/include/platform/memory.h +++ b/src/platform/apollolake/include/platform/memory.h @@ -214,6 +214,8 @@ * +---------------------+----------------+-----------------------------------+ * | SRAM_DEBUG_BASE | Debug data W2 | SRAM_DEBUG_SIZE | * +---------------------+----------------+-----------------------------------+ + * | SRAM_STREAM_BASE | Stream data W2 | SRAM_STREAM_SIZE | + * +---------------------+----------------+-----------------------------------+ * | SRAM_INBOX_BASE | Inbox W1 | SRAM_INBOX_SIZE | * +---------------------+----------------+-----------------------------------+ * | SRAM_SW_REG_BASE | SW Registers W0| SRAM_SW_REG_SIZE | @@ -236,8 +238,11 @@ #define SRAM_DEBUG_BASE (SRAM_TRACE_BASE + SRAM_TRACE_SIZE) #define SRAM_DEBUG_SIZE 0x1000
+#define SRAM_STREAM_BASE (SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE) +#define SRAM_STREAM_SIZE 0x1000 + /* window 1 */ -#define SRAM_INBOX_BASE (SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE) +#define SRAM_INBOX_BASE (SRAM_STREAM_BASE + SRAM_STREAM_SIZE) #define SRAM_INBOX_SIZE 0x2000
/* window 0 */ @@ -258,7 +263,7 @@ #define HP_SRAM_WIN1_BASE SRAM_INBOX_BASE #define HP_SRAM_WIN1_SIZE SRAM_INBOX_SIZE #define HP_SRAM_WIN2_BASE SRAM_DEBUG_BASE -#define HP_SRAM_WIN2_SIZE SRAM_DEBUG_SIZE +#define HP_SRAM_WIN2_SIZE (SRAM_DEBUG_SIZE + SRAM_STREAM_SIZE) #define HP_SRAM_WIN3_BASE SRAM_TRACE_BASE #define HP_SRAM_WIN3_SIZE SRAM_TRACE_SIZE
@@ -274,6 +279,7 @@ (HP_SRAM_SIZE - \ SRAM_TRACE_SIZE - \ SRAM_DEBUG_SIZE - \ + SRAM_STREAM_SIZE - \ SRAM_INBOX_SIZE - \ SRAM_OUTBOX_SIZE - \ SRAM_SW_REG_SIZE) diff --git a/src/platform/apollolake/platform.c b/src/platform/apollolake/platform.c index 3c1d76f..ae8a854 100644 --- a/src/platform/apollolake/platform.c +++ b/src/platform/apollolake/platform.c @@ -68,7 +68,7 @@ static const struct sof_ipc_fw_ready ready = {
#define SRAM_WINDOW_HOST_OFFSET(x) (0x80000 + x * 0x20000)
-#define NUM_APL_WINDOWS 5 +#define NUM_APL_WINDOWS 6
static const struct sof_ipc_window sram_window = { .ext_hdr = { @@ -103,17 +103,23 @@ static const struct sof_ipc_window sram_window = { .type = SOF_IPC_REGION_DEBUG, .id = 2, /* map to host window 2 */ .flags = 0, // TODO: set later - .size = SRAM_DEBUG_SIZE, + .size = MAILBOX_EXCEPTION_SIZE + MAILBOX_DEBUG_SIZE, .offset = 0, }, .window[4] = { + .type = SOF_IPC_REGION_STREAM, + .id = 2, /* map to host window 2 */ + .flags = 0, // TODO: set later + .size = MAILBOX_STREAM_SIZE, + .offset = MAILBOX_STREAM_OFFSET, + }, + .window[5] = { .type = SOF_IPC_REGION_TRACE, .id = 3, /* map to host window 3 */ .flags = 0, // TODO: set later .size = MAILBOX_TRACE_SIZE, .offset = 0, }, - };
static struct work_queue_timesource platform_generic_queue = { diff --git a/src/platform/baytrail/platform.c b/src/platform/baytrail/platform.c index 2c4bfee..cec8297 100644 --- a/src/platform/baytrail/platform.c +++ b/src/platform/baytrail/platform.c @@ -70,7 +70,7 @@ static const struct sof_ipc_fw_ready ready = { /* TODO: add capabilities */ };
-#define NUM_BYT_WINDOWS 4 +#define NUM_BYT_WINDOWS 5 static const struct sof_ipc_window sram_window = { .ext_hdr = { .hdr.cmd = SOF_IPC_FW_READY, @@ -107,6 +107,13 @@ static const struct sof_ipc_window sram_window = { .size = MAILBOX_TRACE_SIZE, .offset = MAILBOX_TRACE_OFFSET, }, + .window[4] = { + .type = SOF_IPC_REGION_STREAM, + .id = 0, /* map to host window 0 */ + .flags = 0, // TODO: set later + .size = MAILBOX_STREAM_SIZE, + .offset = MAILBOX_STREAM_OFFSET, + }, };
static struct work_queue_timesource platform_generic_queue = { diff --git a/src/platform/cannonlake/include/platform/mailbox.h b/src/platform/cannonlake/include/platform/mailbox.h index a3c4339..c58e310 100644 --- a/src/platform/cannonlake/include/platform/mailbox.h +++ b/src/platform/cannonlake/include/platform/mailbox.h @@ -65,15 +65,14 @@ #define MAILBOX_EXCEPTION_BASE \ (MAILBOX_SW_REG_BASE + SRAM_REG_FW_END)
+#define MAILBOX_STREAM_SIZE SRAM_STREAM_SIZE +#define MAILBOX_STREAM_BASE SRAM_STREAM_BASE +#define MAILBOX_STREAM_OFFSET SRAM_DEBUG_SIZE + /* window 1 inbox/downlink and FW registers */ #define MAILBOX_HOSTBOX_SIZE SRAM_INBOX_SIZE #define MAILBOX_HOSTBOX_BASE SRAM_INBOX_BASE
- -#define MAILBOX_STREAM_SIZE 0x200 -#define MAILBOX_STREAM_BASE \ - (MAILBOX_BASE + MAILBOX_STREAM_OFFSET) - /* window 0 */ #define MAILBOX_DSPBOX_SIZE SRAM_OUTBOX_SIZE #define MAILBOX_DSPBOX_BASE SRAM_OUTBOX_BASE diff --git a/src/platform/cannonlake/include/platform/memory.h b/src/platform/cannonlake/include/platform/memory.h index 7e7af82..16e0d85 100644 --- a/src/platform/cannonlake/include/platform/memory.h +++ b/src/platform/cannonlake/include/platform/memory.h @@ -146,6 +146,8 @@ * +---------------------+----------------+-----------------------------------+ * | SRAM_DEBUG_BASE | Debug data W2 | SRAM_DEBUG_SIZE | * +---------------------+----------------+-----------------------------------+ + * | SRAM_STREAM_BASE | Stream data W2 | SRAM_STREAM_SIZE | + * +---------------------+----------------+-----------------------------------+ * | SRAM_TRACE_BASE | Trace Buffer W3| SRAM_TRACE_SIZE | * +---------------------+----------------+-----------------------------------+ * | HP_SRAM_BASE | DMA | HEAP_HP_BUFFER_SIZE | @@ -206,16 +208,19 @@ #define SRAM_DEBUG_BASE (SRAM_INBOX_BASE + SRAM_INBOX_SIZE) #define SRAM_DEBUG_SIZE 0x1000
+#define SRAM_STREAM_BASE (SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE) +#define SRAM_STREAM_SIZE 0x1000 + /* window 3 */ -#define SRAM_TRACE_BASE (SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE) +#define SRAM_TRACE_BASE (SRAM_STREAM_BASE + SRAM_STREAM_SIZE) #define SRAM_TRACE_SIZE 0x2000
#define HP_SRAM_WIN0_BASE SRAM_SW_REG_BASE #define HP_SRAM_WIN0_SIZE (SRAM_SW_REG_SIZE + SRAM_OUTBOX_SIZE) #define HP_SRAM_WIN1_BASE SRAM_INBOX_BASE #define HP_SRAM_WIN1_SIZE SRAM_INBOX_SIZE -#define HP_SRAM_WIN2_BASE SRAM_DEBUG_BASE -#define HP_SRAM_WIN2_SIZE SRAM_DEBUG_SIZE +#define HP_SRAM_WIN2_BASE SRAM_EXCEPTION_BASE +#define HP_SRAM_WIN2_SIZE (SRAM_DEBUG_SIZE + SRAM_STREAM_SIZE) #define HP_SRAM_WIN3_BASE SRAM_TRACE_BASE #define HP_SRAM_WIN3_SIZE SRAM_TRACE_SIZE
diff --git a/src/platform/cannonlake/platform.c b/src/platform/cannonlake/platform.c index beb6582..32a4454 100644 --- a/src/platform/cannonlake/platform.c +++ b/src/platform/cannonlake/platform.c @@ -70,7 +70,7 @@ static const struct sof_ipc_fw_ready ready = {
#define SRAM_WINDOW_HOST_OFFSET(x) (0x80000 + x * 0x20000)
-#define NUM_CNL_WINDOWS 5 +#define NUM_CNL_WINDOWS 6
static const struct sof_ipc_window sram_window = { .ext_hdr = { @@ -105,17 +105,23 @@ static const struct sof_ipc_window sram_window = { .type = SOF_IPC_REGION_DEBUG, .id = 2, /* map to host window 2 */ .flags = 0, // TODO: set later - .size = SRAM_DEBUG_SIZE, + .size = MAILBOX_EXCEPTION_SIZE + MAILBOX_DEBUG_SIZE, .offset = 0, }, .window[4] = { + .type = SOF_IPC_REGION_STREAM, + .id = 2, /* map to host window 2 */ + .flags = 0, // TODO: set later + .size = MAILBOX_STREAM_SIZE, + .offset = MAILBOX_STREAM_OFFSET, + }, + .window[5] = { .type = SOF_IPC_REGION_TRACE, .id = 3, /* map to host window 3 */ .flags = 0, // TODO: set later .size = MAILBOX_TRACE_SIZE, .offset = 0, }, - };
static struct work_queue_timesource platform_generic_queue = { diff --git a/src/platform/haswell/platform.c b/src/platform/haswell/platform.c index 97b38af..95d80f8 100644 --- a/src/platform/haswell/platform.c +++ b/src/platform/haswell/platform.c @@ -69,7 +69,7 @@ static const struct sof_ipc_fw_ready ready = { /* TODO: add capabilities */ };
-#define NUM_HSW_WINDOWS 4 +#define NUM_HSW_WINDOWS 5 static const struct sof_ipc_window sram_window = { .ext_hdr = { .hdr.cmd = SOF_IPC_FW_READY, @@ -106,6 +106,13 @@ static const struct sof_ipc_window sram_window = { .size = MAILBOX_TRACE_SIZE, .offset = MAILBOX_TRACE_OFFSET, }, + .window[4] = { + .type = SOF_IPC_REGION_STREAM, + .id = 0, /* map to host window 0 */ + .flags = 0, // TODO: set later + .size = MAILBOX_STREAM_SIZE, + .offset = MAILBOX_STREAM_OFFSET, + }, };
static struct work_queue_timesource platform_generic_queue = {