I've had some of these patches on a work branch for some time now and only found the time to rebase/clean them now. The most important parts are support for DSP_A/B modes which never worked on Baytrail, Cherrytrail and clarifications on how the MCLK/Bitclock are generated on ApolloLake (parallel dividers instead of serial ones, allowing for independent selection of the source and ratios)
I could use comments on the code. I still have a couple of tests to run so it's not ready for integration but if I could have additional reviews or tests in parallel it'd be nice. Thanks!
Pierre-Louis Bossart (4): ssp: rename clk_id as mclk_id, remove dead code apl-ssp: fix MCLK and BCLK source selection byt-ssp: fixes for DSP modes byt-ssp: fix frame sync polarity for DSP modes
src/drivers/apl-ssp.c | 132 +++++++++++++++++++++++++++++++++---------------- src/drivers/byt-ssp.c | 42 +++++----------- src/include/sof/ssp.h | 5 ++ src/include/uapi/ipc.h | 2 +- 4 files changed, 107 insertions(+), 74 deletions(-)