hi Liam,
yes all the clk and data output are validated by scope.
And it is also validated by ZhiGang on APL. And the setting
is compared to the setting used by COE provided by YuXin.
Rander
On 3/7/2018 10:46 PM, Liam Girdwood wrote:
On Wed, 2018-03-07 at 08:01 -0600, Pierre-Louis Bossart wrote:
On 3/6/18 10:31 PM, Rander Wang wrote:
set ssp according to DSP_B spec
Signed-off-by: Rander Wang rander.wang@linux.intel.com
src/drivers/apl-ssp.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/drivers/apl-ssp.c b/src/drivers/apl-ssp.c index a726f3c..c32bd35 100644 --- a/src/drivers/apl-ssp.c +++ b/src/drivers/apl-ssp.c @@ -333,10 +333,11 @@ static inline int ssp_set_config(struct dai *dai, sscr0 |= SSCR0_MOD | SSCR0_FRDC(config-
num_slots);
/* set asserted frame length */
frame_len = config->sample_container_bits;
frame_len = 1;this needs to be done for DSP_B as well.
/* handle frame polarity, DSP_A default isrising/active high */
sspsp |= SSPSP_SFRMP(inverted_frame);
sspsp |= SSPSP_SFRMP(!inverted_frame);I don't think this is correct. the documentation says with this bit asserted (value=1) the frame is active high which is exactly what we want.
Rander, I'm assuming this was validated with a scope ?
Liam