Re: [alsa-devel] WM8731 using I2S on omap3 McBSP2 issues
Hi Peter,
Yes it is indicating so. I read through this thread I didn't find any simple reason why it's not working. Your setup is similar with the Pandora, i.e. McBSP functional clock is coming the codec and codec is slave.
Yes, I pretty much used the pandora as an example to write mine.
The McBSP is operating if the FSX and CLKX are toggling in this setup. Is it so that you don't get any DMA interrupts or just few of them?
I don't get any DMA int's:
~# cat /proc/interrupts CPU0 11: 0 INTC prcm 12: 0 INTC DMA 25: 0 INTC dispc 37: 5003 INTC gp timer 56: 3425 INTC i2c_omap 62: 0 INTC McBSP 63: 0 INTC McBSP
Your CLKGDV divisor value 256 means too low bit clock and sample rate for both external 12.288 MHz and internal 96 MHz but still the DMA should be running (if there is no bug with this divisor value). Can you try divisor value 8 does it work then? For 48 kHz sample rate with I2S you need a bit clock of 48 kHz*2*16 = 1.536 MHz and this you get by dividing the 12.288 MHz with 8.
Yes, I had tried 8 before and just tried it now. Same result. It really seems like there is a DMA issue. Can you think of anything else to try before I dive into the DMA code?
Rick
On Sat, 26 Sep 2009 08:59:52 -0700 Rick Bronson rick@efn.org wrote:
Yes, I had tried 8 before and just tried it now. Same result. It really seems like there is a DMA issue. Can you think of anything else to try before I dive into the DMA code?
Ok, that wasn't the reason.
Have you tried to reverse roles of codec and omap? I.e. by using the codec as a master and omap as a slave with SND_SOC_DAIFMT_CBM_CFM.
I don't think there is any HW reason as you have seen the bit-clock and frame sync signals toggling but I remember one case few years back where codec had slight too high capacitive load on the bit-clock line. That was then causing unstable frame sync as it was internally derived directly from the bit-clock pin without any buffer. Bit-clock signal looked just fine on oscilloscope but wasn't well enough for internal circuits of the cpu.
So if assuming similar problem here, I could imagine that if the FSX is used similar way directly inside the omap and if signal is not well enough, the McBSP and DMA may not be running.
This migh be a bit far reason to look for but at least easy to try by switching the roles as then the codec is driving the both bit-clock and fs.
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Rick Bronson