Hi,

I'm playing with a custom iMX6SX board having the SSI connected to a SLIC in TDM mode. SSI has TXC (PCLK) coming from an external oscillator running at 2.048MHz while TXFS (FSYNC) is set to be generated from internal or at least this is what I'm trying to do.

The SSI documentation is not really clear in case, so wondering to know if it is possible to generate FSYNC with this particular configuration: SSI set in I2S normal mode, synchronous transfers, network mode, TXC taken from external oscillator.

The relevant part reported in iMX6SXRM doc (62.8.4 SSI Clocking) is:

"In master and synchronous mode, the unused port SRCK is used as network clock (oversampling clock) enabled by the SCR register bit 15, SYS_CLK_EN. This network clock is an oversampling clock of the frame sync clock (STFS). In this mode, the word length (WL), Prescaler Range (PSR), Prescaler Modulus (PM) and Frame rate (DC) selects the ratio of network clock to sampling clock STFS. In case of I2S mode, the network clock (oversampling clock) can be made available on this port if the SYS_CLK_EN bit is set."

Accordingly with Figure 62-22 in the iMX6SX reference manual network clock on SRCK can be activated only when both TXDIR and SYS_CLK_EN are set. But if TXDIR is set I cannot get STCK from external oscillator because SSI is now generating it from internal. I've also changed the way how audmux is routing FYSNC, internal port is SSI1 and external is SSI6

int audmux_config(unsigned int master, unsigned int slave) { unsigned int ptcr, pdcr;

ptcr = IMX_AUDMUX_V2_PTCR_SYN /* Synchronous mode */ | IMX_AUDMUX_V2_PTCR_TCSEL(slave); /* transmit clock select from external port */ pdcr = IMX_AUDMUX_V2_PDCR_RXDSEL(slave); audmux_v2_configure_port(master, ptcr, pdcr); /* configure internal port */

ptcr = IMX_AUDMUX_V2_PTCR_SYN | IMX_AUDMUX_V2_PTCR_TFSDIR /* Transmit Frame Sync from Internal */ | IMX_AUDMUX_V2_PTCR_TFSEL(master); /* from master port */ pdcr = IMX_AUDMUX_V2_PDCR_RXDSEL(master); audmux_v2_configure_port(slave, ptcr, pdcr); /* configure external port */ return 0; }

and SSI1 is set as:

scr = CCSR_SSI_SCR_I2S_MODE_NORMAL | CCSR_SSI_SCR_SYN | /* Synchronous mode */ CCSR_SSI_SCR_NET; /* Network mode to enable TDM */

stcr = CCSR_SSI_STCR_TXBIT0 | /* LSB Aligned */ CCSR_SSI_STCR_TFDIR | /* Transmit Frame Direction Internal - generated internally */ CCSR_SSI_STCR_TFEN0 | /* Enable TX FIFO0 */ CCSR_SSI_STCR_TSCKP; /* Transmit Clock Polarity - Data Clocked out on falling edge */

Doesn't anyone know if it's possible to have this particular TDM configuration?

Thanks in advance, Roberto Fichera.