Hi,

I think simple-card doesn't have .set_pll / .set_clkdiv feature today. You can add such feature if needed.

Implementing such a feature into simple-card driver alone might not be possible, as the PLL output frequency and resulting MCLK/BCLK divisors are codec dependent.

I wonder if the right place would be within the codec driver, after all? The machine code would just request a certain bitclock frequency and frame length in case the codec is selected to be the clock master.

Is this in line with ASoC architecture?

-Jukka