From: Kenneth Westfield kwestfie@codeaurora.org

Signed-off-by: Kenneth Westfield kwestfie@codeaurora.org Acked-by: Banajit Goswami bgoswami@codeaurora.org --- MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS index ddb9ac8d32b3eddc46d66bd408392ae09b637ea7..19141e405644cd9b4d41a4d291d5644513bea337 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5169,6 +5169,13 @@ F: drivers/char/ipmi/ F: include/linux/ipmi* F: include/uapi/linux/ipmi*

+QCOM AUDIO (ASoC) DRIVERS +M: Patrick Lai plai@codeaurora.org +M: Banajit Goswami bgoswami@codeaurora.org +L: alsa-devel@alsa-project.org (moderated for non-subscribers) +S: Supported +F: sound/soc/qcom/ + IPS SCSI RAID DRIVER M: Adaptec OEM Raid Solutions aacraid@adaptec.com L: linux-scsi@vger.kernel.org

From: Kenneth Westfield kwestfie@codeaurora.org

Add the CPU DAI driver for the QCOM LPASS SOC.

Signed-off-by: Kenneth Westfield kwestfie@codeaurora.org Acked-by: Banajit Goswami bgoswami@codeaurora.org --- sound/soc/qcom/lpass-cpu-mi2s.c | 378 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 378 insertions(+) create mode 100644 sound/soc/qcom/lpass-cpu-mi2s.c

diff --git a/sound/soc/qcom/lpass-cpu-mi2s.c b/sound/soc/qcom/lpass-cpu-mi2s.c new file mode 100644 index 0000000000000000000000000000000000000000..dc1bd53a78c3d6c097909dd240b6580efae19577 --- /dev/null +++ b/sound/soc/qcom/lpass-cpu-mi2s.c @@ -0,0 +1,378 @@ +/* + * Copyright (c) 2010-2011,2013-2014 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/module.h> +#include <linux/clk.h> +#include <linux/dma-mapping.h> +#include <sound/soc.h> +#include <sound/pcm_params.h> +#include "lpass-lpaif-reg.h" +#include "lpass-mi2s.h" + +#define DRV_NAME "lpass-cpu-mi2s" + +#define LPASS_OSR_TO_BIT_DIVIDER 4 + +static inline int lpass_lpaif_mi2s_config(struct snd_soc_dai *dai, + unsigned int channels, unsigned int bitwidth) +{ + struct lpass_mi2s_data *drvdata = snd_soc_dai_get_drvdata(dai); + u32 mi2s_control_offset = LPAIF_MI2S_CTL_OFFSET(LPAIF_I2S_PORT_MI2S); + u32 value; + + value = 0; + + value &= ~LPAIF_MI2SCTL_WS; + + switch (bitwidth) { + case 16: + value |= LPAIF_MI2SCTL_BITWIDTH_16; + break; + case 24: + value |= LPAIF_MI2SCTL_BITWIDTH_24; + break; + case 32: + value |= LPAIF_MI2SCTL_BITWIDTH_32; + break; + default: + dev_err(dai->dev, "%s: invalid bitwidth given: %u\n", __func__, + bitwidth); + return -EINVAL; + } + + switch (channels) { + case 1: + value |= LPAIF_MI2SCTL_SPKMODE_SD0; + value |= LPAIF_MI2SCTL_SPKMONO_MONO; + break; + case 2: + value |= LPAIF_MI2SCTL_SPKMODE_SD0; + value |= LPAIF_MI2SCTL_SPKMONO_STEREO; + break; + case 4: + value |= LPAIF_MI2SCTL_SPKMODE_QUAD01; + value |= LPAIF_MI2SCTL_SPKMONO_STEREO; + break; + case 6: + value |= LPAIF_MI2SCTL_SPKMODE_6CH; + value |= LPAIF_MI2SCTL_SPKMONO_STEREO; + break; + case 8: + value |= LPAIF_MI2SCTL_SPKMODE_8CH; + value |= LPAIF_MI2SCTL_SPKMONO_STEREO; + break; + default: + dev_err(dai->dev, "%s: invalid channels given: %u\n", __func__, + channels); + return -EINVAL; + } + + writel(value, drvdata->base + mi2s_control_offset); + + return 0; +} + +static inline void lpass_lpaif_mi2s_playback_start(struct snd_soc_dai *dai) +{ + struct lpass_mi2s_data *drvdata = snd_soc_dai_get_drvdata(dai); + u32 mi2s_control_offset = LPAIF_MI2S_CTL_OFFSET(LPAIF_I2S_PORT_MI2S); + u32 value; + + value = readl(drvdata->base + mi2s_control_offset); + value |= LPAIF_MI2SCTL_SPKEN; + writel(value, drvdata->base + mi2s_control_offset); +} + +static inline void lpass_lpaif_mi2s_playback_stop(struct snd_soc_dai *dai) +{ + struct lpass_mi2s_data *drvdata = snd_soc_dai_get_drvdata(dai); + u32 mi2s_control_offset = LPAIF_MI2S_CTL_OFFSET(LPAIF_I2S_PORT_MI2S); + u32 value; + + value = readl(drvdata->base + mi2s_control_offset); + value &= ~LPAIF_MI2SCTL_SPKEN; + writel(value, drvdata->base + mi2s_control_offset); +} + +static inline void lpass_lpaif_mi2s_playback_stop_clear(struct snd_soc_dai *dai) +{ + struct lpass_mi2s_data *drvdata = snd_soc_dai_get_drvdata(dai); + u32 mi2s_control_offset = LPAIF_MI2S_CTL_OFFSET(LPAIF_I2S_PORT_MI2S); + + writel(0, drvdata->base + mi2s_control_offset); +} + +static int lpass_cpu_mi2s_daiops_startup(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct lpass_mi2s_data *drvdata = snd_soc_dai_get_drvdata(dai); + int ret; + + ret = clk_prepare_enable(drvdata->mi2s_osr_clk); + if (ret) { + dev_err(dai->dev, "%s: error in enabling mi2s osr clk: %d\n", + __func__, ret); + return ret; + } + + ret = clk_prepare_enable(drvdata->mi2s_bit_clk); + if (ret) { + dev_err(dai->dev, "%s: error in enabling mi2s bit clk: %d\n", + __func__, ret); + clk_disable_unprepare(drvdata->mi2s_osr_clk); + return ret; + } + + return 0; +} + +static void lpass_cpu_mi2s_daiops_shutdown(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct lpass_mi2s_data *drvdata = snd_soc_dai_get_drvdata(dai); + + clk_disable_unprepare(drvdata->mi2s_bit_clk); + clk_disable_unprepare(drvdata->mi2s_osr_clk); +} + +static int lpass_cpu_mi2s_daiops_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) +{ + struct lpass_mi2s_data *drvdata = snd_soc_dai_get_drvdata(dai); + snd_pcm_format_t format = params_format(params); + unsigned int channels = params_channels(params); + unsigned int rate = params_rate(params); + int bitwidth; + int ret; + + bitwidth = snd_pcm_format_width(format); + if (bitwidth < 0) { + dev_err(dai->dev, "%s: Invalid bit width given\n", __func__); + return bitwidth; + } + + ret = lpass_lpaif_mi2s_config(dai, channels, bitwidth); + if (ret) { + dev_err(dai->dev, "%s: Channel setting unsuccessful\n", + __func__); + return -EINVAL; + } + + ret = clk_set_rate(drvdata->mi2s_osr_clk, + (rate * bitwidth * channels * LPASS_OSR_TO_BIT_DIVIDER)); + if (ret) { + dev_err(dai->dev, "%s: error in setting mi2s osr clk: %d\n", + __func__, ret); + return ret; + } + + ret = clk_set_rate(drvdata->mi2s_bit_clk, rate * bitwidth * channels); + if (ret) { + dev_err(dai->dev, "%s: error in setting mi2s bit clk: %d\n", + __func__, ret); + return ret; + } + + return 0; +} + +static int lpass_cpu_mi2s_daiops_hw_free(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + lpass_lpaif_mi2s_playback_stop_clear(dai); + + return 0; +} + +static int lpass_cpu_mi2s_daiops_prepare(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + lpass_lpaif_mi2s_playback_start(dai); + + return 0; +} + +static int lpass_cpu_mi2s_daiops_set_sysclk(struct snd_soc_dai *dai, + int clk_id, unsigned int freq, int dir) +{ + struct lpass_mi2s_data *drvdata = snd_soc_dai_get_drvdata(dai); + int ret; + + ret = clk_set_rate(drvdata->mi2s_osr_clk, freq); + if (ret) { + dev_err(dai->dev, "%s: error in setting mi2s osr clk: %d\n", + __func__, ret); + return ret; + } + + return 0; +} + +static struct snd_soc_dai_ops lpass_cpu_mi2s_dai_ops = { + .startup = lpass_cpu_mi2s_daiops_startup, + .shutdown = lpass_cpu_mi2s_daiops_shutdown, + .hw_params = lpass_cpu_mi2s_daiops_hw_params, + .hw_free = lpass_cpu_mi2s_daiops_hw_free, + .prepare = lpass_cpu_mi2s_daiops_prepare, + .set_sysclk = lpass_cpu_mi2s_daiops_set_sysclk, +}; + +static int lpass_cpu_mi2s_dai_probe(struct snd_soc_dai *dai) +{ + struct lpass_mi2s_data *drvdata = snd_soc_dai_get_drvdata(dai); + + drvdata->mi2s_osr_clk = devm_clk_get(dai->dev, "mi2s_osr_clk"); + if (IS_ERR(drvdata->mi2s_osr_clk)) { + dev_err(dai->dev, "%s: Error in getting mi2s_osr_clk\n", + __func__); + return PTR_ERR(drvdata->mi2s_osr_clk); + } + + drvdata->mi2s_bit_clk = devm_clk_get(dai->dev, "mi2s_bit_clk"); + if (IS_ERR(drvdata->mi2s_bit_clk)) { + dev_err(dai->dev, "%s: Error in getting mi2s_bit_clk\n", + __func__); + return PTR_ERR(drvdata->mi2s_bit_clk); + } + + /* ensure MI2S port is disabled */ + lpass_lpaif_mi2s_playback_stop_clear(dai); + + return 0; +} + +static struct snd_soc_dai_driver lpass_cpu_mi2s_dai_driver = { + .playback = { + .stream_name = "lpass-cpu-mi2s-playback", + .formats = SNDRV_PCM_FMTBIT_S16 | + SNDRV_PCM_FMTBIT_S24 | + SNDRV_PCM_FMTBIT_S32, + .rates = SNDRV_PCM_RATE_8000 | + SNDRV_PCM_RATE_16000 | + SNDRV_PCM_RATE_32000 | + SNDRV_PCM_RATE_48000 | + SNDRV_PCM_RATE_96000, + .rate_min = 8000, + .rate_max = 96000, + .channels_min = 1, + .channels_max = 8, + }, + .probe = &lpass_cpu_mi2s_dai_probe, + .ops = &lpass_cpu_mi2s_dai_ops, +}; + +static const struct snd_soc_component_driver lpass_cpu_mi2s_comp_driver = { + .name = DRV_NAME, +}; + +static int lpass_cpu_mi2s_platform_probe(struct platform_device *pdev) +{ + struct device_node *of_node = pdev->dev.of_node; + struct lpass_mi2s_data *drvdata; + struct resource *lpass_res; + u32 freq; + int ret; + + drvdata = devm_kzalloc(&pdev->dev, sizeof(struct lpass_mi2s_data), + GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + platform_set_drvdata(pdev, drvdata); + + lpass_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "lpass-lpaif-mem"); + if (!lpass_res) { + dev_err(&pdev->dev, "%s: error getting resource\n", __func__); + return -ENODEV; + } + + drvdata->base = devm_ioremap_resource(&pdev->dev, lpass_res); + if (IS_ERR(drvdata->base)) { + dev_err(&pdev->dev, "%s: error remapping resource\n", + __func__); + return PTR_ERR(drvdata->base); + } + + drvdata->irqnum = platform_get_irq_byname(pdev, "lpass-lpaif-irq"); + if (drvdata->irqnum < 0) { + dev_err(&pdev->dev, "%s: failed get irq res\n", __func__); + return -ENODEV; + } + + drvdata->ahbix_clk = devm_clk_get(&pdev->dev, "ahbix_clk"); + if (IS_ERR(drvdata->ahbix_clk)) { + dev_err(&pdev->dev, "%s: Error getting ahbix_clk\n", __func__); + return PTR_ERR(drvdata->ahbix_clk); + } + + if (of_property_read_bool(of_node, "ahbix-frequency")) + of_property_read_u32(of_node, "ahbix-frequency", &freq); + clk_set_rate(drvdata->ahbix_clk, freq); + + ret = clk_prepare_enable(drvdata->ahbix_clk); + if (ret) { + dev_err(&pdev->dev, "%s: Error enabling ahbix_clk\n", __func__); + return ret; + } + + ret = devm_snd_soc_register_component(&pdev->dev, + &lpass_cpu_mi2s_comp_driver, + &lpass_cpu_mi2s_dai_driver, 1); + if (ret) { + dev_err(&pdev->dev, "%s: error registering soc dai\n", + __func__); + goto err_clk; + } + + ret = lpass_pcm_mi2s_platform_register(&pdev->dev); + if (ret) { + dev_err(&pdev->dev, "%s: error registering pcm device\n", + __func__); + goto err_clk; + } + + return 0; + +err_clk: + clk_disable_unprepare(drvdata->ahbix_clk); + return ret; +} + +static int lpass_cpu_mi2s_platform_remove(struct platform_device *pdev) +{ + struct lpass_mi2s_data *drvdata = platform_get_drvdata(pdev); + + clk_disable_unprepare(drvdata->ahbix_clk); + + return 0; +} + +static const struct of_device_id lpass_cpu_mi2s_dt_match[] = { + {.compatible = "qcom,lpass-cpu-mi2s"}, + {} +}; + +static struct platform_driver lpass_cpu_mi2s_platform_driver = { + .driver = { + .name = DRV_NAME, + .of_match_table = lpass_cpu_mi2s_dt_match, + }, + .probe = lpass_cpu_mi2s_platform_probe, + .remove = lpass_cpu_mi2s_platform_remove, +}; +module_platform_driver(lpass_cpu_mi2s_platform_driver); + +MODULE_DESCRIPTION("QCOM LPASS MI2S CPU DRIVER"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" DRV_NAME); +MODULE_DEVICE_TABLE(of, lpass_cpu_mi2s_dt_match);

From: Kenneth Westfield kwestfie@codeaurora.org

Add PCM platform driver for the LPASS I2S port.

Signed-off-by: Kenneth Westfield kwestfie@codeaurora.org Acked-by: Banajit Goswami bgoswami@codeaurora.org --- sound/soc/qcom/lpass-pcm-mi2s.c | 486 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 486 insertions(+) create mode 100644 sound/soc/qcom/lpass-pcm-mi2s.c

diff --git a/sound/soc/qcom/lpass-pcm-mi2s.c b/sound/soc/qcom/lpass-pcm-mi2s.c new file mode 100644 index 0000000000000000000000000000000000000000..7cf2ef9525388e9cad1c1b532cd6bc3b46a48b9d --- /dev/null +++ b/sound/soc/qcom/lpass-pcm-mi2s.c @@ -0,0 +1,486 @@ +/* + * Copyright (c) 2010-2011,2013-2014 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/module.h> +#include <linux/dma-mapping.h> +#include <sound/soc.h> +#include <sound/pcm_params.h> +#include "lpass-lpaif-reg.h" +#include "lpass-mi2s.h" + +#define DRV_NAME "lpass-pcm-mi2s" + +/* MI2S HW params */ +#define LPASS_MI2S_PERIOD_SIZE (8064) +#define LPASS_MI2S_PERIODS_MIN (2) +#define LPASS_MI2S_PERIODS_MAX (4) +#define LPASS_MI2S_BUFF_SIZE_MIN (LPASS_MI2S_PERIOD_SIZE * \ + LPASS_MI2S_PERIODS_MIN) +#define LPASS_MI2S_BUFF_SIZE_MAX (LPASS_MI2S_PERIOD_SIZE * \ + LPASS_MI2S_PERIODS_MAX) + +static struct snd_pcm_hardware lpass_pcm_mi2s_hardware_playback = { + .info = SNDRV_PCM_INFO_MMAP | + SNDRV_PCM_INFO_BLOCK_TRANSFER | + SNDRV_PCM_INFO_MMAP_VALID | + SNDRV_PCM_INFO_INTERLEAVED | + SNDRV_PCM_INFO_PAUSE | + SNDRV_PCM_INFO_RESUME, + .formats = SNDRV_PCM_FMTBIT_S16 | + SNDRV_PCM_FMTBIT_S24 | + SNDRV_PCM_FMTBIT_S32, + .rates = SNDRV_PCM_RATE_8000_192000, + .rate_min = 8000, + .rate_max = 192000, + .channels_min = 1, + .channels_max = 8, + .buffer_bytes_max = LPASS_MI2S_BUFF_SIZE_MAX, + .period_bytes_max = LPASS_MI2S_PERIOD_SIZE, + .period_bytes_min = LPASS_MI2S_PERIOD_SIZE, + .periods_min = LPASS_MI2S_PERIODS_MIN, + .periods_max = LPASS_MI2S_PERIODS_MAX, + .fifo_size = 0, +}; + +static inline void lpass_lpaif_int_enable(struct snd_soc_platform *platform) +{ + struct lpass_mi2s_data *drvdata = + snd_soc_platform_get_drvdata(platform); + u32 clear_offset = LPAIF_DMAIRQ_CLEAR(LPAIF_IRQ_RECV_HOST); + u32 enable_offset = LPAIF_DMAIRQ_EN(LPAIF_IRQ_RECV_HOST); + u32 chan_bitmask = LPAIF_DMAIRQ_ALL(LPAIF_DMA_RD_CH_MI2S); + u32 value; + + /* clear status before enabling interrupts */ + writel(chan_bitmask, drvdata->base + clear_offset); + + value = readl(drvdata->base + enable_offset); + value |= chan_bitmask; + writel(value, drvdata->base + enable_offset); +} + +static inline void lpass_lpaif_int_disable(struct snd_soc_platform *platform) +{ + struct lpass_mi2s_data *drvdata = + snd_soc_platform_get_drvdata(platform); + u32 enable_offset = LPAIF_DMAIRQ_EN(LPAIF_IRQ_RECV_HOST); + u32 chan_bitmask = LPAIF_DMAIRQ_ALL(LPAIF_DMA_RD_CH_MI2S); + u32 value; + + value = readl(drvdata->base + enable_offset); + value &= ~chan_bitmask; + writel(value, drvdata->base + enable_offset); +} + +static inline u32 lpass_lpaif_int_retrieve(struct snd_soc_platform *platform) +{ + struct lpass_mi2s_data *drvdata = + snd_soc_platform_get_drvdata(platform); + u32 status_offset = LPAIF_DMAIRQ_STAT(LPAIF_IRQ_RECV_HOST); + u32 clear_offset = LPAIF_DMAIRQ_CLEAR(LPAIF_IRQ_RECV_HOST); + u32 chan_bitmask = LPAIF_DMAIRQ_ALL(LPAIF_DMA_RD_CH_MI2S); + u32 value; + + value = readl(drvdata->base + status_offset); + value &= chan_bitmask; + writel(value, drvdata->base + clear_offset); + + return value; +} + +static inline int lpass_lpaif_dma_set_format(struct snd_soc_platform *platform, + unsigned int channels, unsigned int bitwidth) +{ + struct lpass_mi2s_data *drvdata = + snd_soc_platform_get_drvdata(platform); + u32 dma_control_offset = LPAIF_DMA_CTL(LPAIF_DMA_RD_CH_MI2S); + u32 value = 0; + + value |= LPAIF_DMACTL_BURST_EN; + value |= LPAIF_DMACTL_AUDIO_INTF_MI2S; + value |= LPAIF_DMACTL_FIFO_WM_8; + + switch (bitwidth) { + case 16: + switch (channels) { + case 1: + case 2: + value |= LPAIF_DMACTL_WPSCNT_SINGLE; + break; + case 4: + value |= LPAIF_DMACTL_WPSCNT_DOUBLE; + break; + case 6: + value |= LPAIF_DMACTL_WPSCNT_TRIPLE; + break; + case 8: + value |= LPAIF_DMACTL_WPSCNT_QUAD; + break; + default: + dev_err(platform->dev, "%s: invalid PCM config given: bw=%u, ch=%u\n", + __func__, bitwidth, channels); + return -EINVAL; + } + break; + case 24: + case 32: + switch (channels) { + case 1: + value |= LPAIF_DMACTL_WPSCNT_SINGLE; + break; + case 2: + value |= LPAIF_DMACTL_WPSCNT_DOUBLE; + break; + case 4: + value |= LPAIF_DMACTL_WPSCNT_QUAD; + break; + case 6: + value |= LPAIF_DMACTL_WPSCNT_SIXPACK; + break; + case 8: + value |= LPAIF_DMACTL_WPSCNT_OCTAL; + break; + default: + dev_err(platform->dev, "%s: invalid PCM config given: bw=%u, ch=%u\n", + __func__, bitwidth, channels); + return -EINVAL; + } + break; + default: + dev_err(platform->dev, "%s: invalid PCM config given: bw=%u, ch=%u\n", + __func__, bitwidth, channels); + return -EINVAL; + } + + writel(value, drvdata->base + dma_control_offset); + + return 0; +} + +static inline void lpass_lpaif_dma_set_addr(struct snd_soc_platform *platform, + dma_addr_t src_start, size_t buffer_size, size_t period_size) +{ + struct lpass_mi2s_data *drvdata = + snd_soc_platform_get_drvdata(platform); + u32 base_address_offset = LPAIF_DMA_BASEADDR(LPAIF_DMA_RD_CH_MI2S); + u32 buffer_length_offset = LPAIF_DMA_BUFFLEN(LPAIF_DMA_RD_CH_MI2S); + u32 period_length_offset = LPAIF_DMA_PERLEN(LPAIF_DMA_RD_CH_MI2S); + + writel(src_start, drvdata->base + base_address_offset); + writel((buffer_size >> 2) - 1, drvdata->base + buffer_length_offset); + writel((period_size >> 2) - 1, drvdata->base + period_length_offset); +} + +static inline void lpass_lpaif_dma_start(struct snd_soc_platform *platform) +{ + struct lpass_mi2s_data *drvdata = + snd_soc_platform_get_drvdata(platform); + u32 dma_control_offset = LPAIF_DMA_CTL(LPAIF_DMA_RD_CH_MI2S); + u32 value; + + value = readl(drvdata->base + dma_control_offset); + value |= LPAIF_DMACTL_ENABLE; + writel(value, drvdata->base + dma_control_offset); +} + +static inline void lpass_lpaif_dma_stop(struct snd_soc_platform *platform) +{ + struct lpass_mi2s_data *drvdata = + snd_soc_platform_get_drvdata(platform); + u32 dma_control_offset = LPAIF_DMA_CTL(LPAIF_DMA_RD_CH_MI2S); + u32 value; + + value = readl(drvdata->base + dma_control_offset); + value &= ~LPAIF_DMACTL_ENABLE; + writel(value, drvdata->base + dma_control_offset); +} + +static inline void lpass_lpaif_dma_stop_clear(struct snd_soc_platform *platform) +{ + struct lpass_mi2s_data *drvdata = + snd_soc_platform_get_drvdata(platform); + u32 dma_control_offset = LPAIF_DMA_CTL(LPAIF_DMA_RD_CH_MI2S); + + writel(0, drvdata->base + dma_control_offset); +} + +static int lpass_pcm_mi2s_alloc_buffer(struct snd_pcm *pcm, int stream) +{ + struct snd_pcm_substream *substream = pcm->streams[stream].substream; + struct snd_soc_pcm_runtime *soc_runtime = substream->private_data; + struct snd_dma_buffer *buf = &substream->dma_buffer; + size_t size; + + size = lpass_pcm_mi2s_hardware_playback.buffer_bytes_max; + + buf->dev.type = SNDRV_DMA_TYPE_DEV; + buf->dev.dev = pcm->card->dev; + buf->private_data = NULL; + buf->area = dma_alloc_coherent(pcm->card->dev, size, + &buf->addr, GFP_KERNEL); + if (!buf->area) { + dev_err(soc_runtime->dev, "%s: Could not allocate DMA buffer\n", + __func__); + return -ENOMEM; + } + buf->bytes = size; + + return 0; +} + +static void lpass_pcm_mi2s_free_buffer(struct snd_pcm *pcm, int stream) +{ + struct snd_pcm_substream *substream; + struct snd_dma_buffer *buf; + + substream = pcm->streams[stream].substream; + buf = &substream->dma_buffer; + if (buf->area) { + dma_free_coherent(pcm->card->dev, buf->bytes, buf->area, + buf->addr); + } + buf->area = NULL; +} + +static irqreturn_t lpass_pcm_mi2s_irq(int irq, void *data) +{ + struct snd_pcm_substream *substream = data; + struct snd_pcm_runtime *runtime = substream->runtime; + struct snd_soc_pcm_runtime *soc_runtime = substream->private_data; + struct lpass_mi2s_data *drvdata = + snd_soc_platform_get_drvdata(soc_runtime->platform); + u32 xrun_bitmask = LPAIF_DMAIRQ_XRUN(LPAIF_DMA_RD_CH_MI2S); + u32 period_bitmask = LPAIF_DMAIRQ_PER(LPAIF_DMA_RD_CH_MI2S); + u32 error_bitmask = LPAIF_DMAIRQ_ERR(LPAIF_DMA_RD_CH_MI2S); + u32 pending; + irqreturn_t ret = IRQ_NONE; + + pending = lpass_lpaif_int_retrieve(soc_runtime->platform); + + if (unlikely(pending & xrun_bitmask) && snd_pcm_running(substream)) { + dev_warn(soc_runtime->dev, "%s: xrun warning\n", __func__); + snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN); + pending &= ~xrun_bitmask; + ret = IRQ_HANDLED; + } + + if (pending & period_bitmask) { + if (++drvdata->period_index >= runtime->periods) + drvdata->period_index = 0; + snd_pcm_period_elapsed(substream); + pending &= ~period_bitmask; + ret = IRQ_HANDLED; + } + + if (pending & xrun_bitmask) { + snd_pcm_period_elapsed(substream); + dev_warn(soc_runtime->dev, "%s: xrun warning\n", __func__); + ret = IRQ_HANDLED; + } + + if (pending & error_bitmask) { + dev_err(soc_runtime->dev, "%s: Bus access error\n", __func__); + ret = IRQ_HANDLED; + } + + return ret; +} + +static int lpass_pcm_mi2s_open(struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + struct snd_soc_pcm_runtime *soc_runtime = substream->private_data; + struct lpass_mi2s_data *drvdata = + snd_soc_platform_get_drvdata(soc_runtime->platform); + int ret; + + drvdata->prepare_start = 0; + drvdata->period_index = 0; + + runtime->dma_bytes = lpass_pcm_mi2s_hardware_playback.buffer_bytes_max; + snd_soc_set_runtime_hwparams(substream, + &lpass_pcm_mi2s_hardware_playback); + + ret = snd_pcm_hw_constraint_integer(runtime, + SNDRV_PCM_HW_PARAM_PERIODS); + if (ret < 0) { + dev_err(soc_runtime->dev, + "%s: snd_pcm_hw_constraint_integer failed\n", + __func__); + return -EINVAL; + } + + snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer); + + return 0; +} + +static int lpass_pcm_mi2s_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_pcm_runtime *soc_runtime = substream->private_data; + snd_pcm_format_t format = params_format(params); + unsigned int channels = params_channels(params); + int bitwidth; + int ret; + + bitwidth = snd_pcm_format_width(format); + if (bitwidth < 0) { + dev_err(soc_runtime->dev, "%s: Invalid bit width given\n", + __func__); + return bitwidth; + } + + ret = lpass_lpaif_dma_set_format(soc_runtime->platform, channels, + bitwidth); + if (ret) { + dev_err(soc_runtime->dev, "%s: Error setting DMA format\n", + __func__); + return -EINVAL; + } + + return 0; +} + +static int lpass_pcm_mi2s_hw_free(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *soc_runtime = substream->private_data; + + lpass_lpaif_dma_stop_clear(soc_runtime->platform); + lpass_lpaif_int_disable(soc_runtime->platform); + + return 0; +} + +static int lpass_pcm_mi2s_prepare(struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + struct snd_soc_pcm_runtime *soc_runtime = substream->private_data; + struct lpass_mi2s_data *drvdata = + snd_soc_platform_get_drvdata(soc_runtime->platform); + + /* xrun recovery */ + if (drvdata->prepare_start) + return 0; + drvdata->prepare_start = 1; + + lpass_lpaif_dma_set_addr(soc_runtime->platform, runtime->dma_addr, + snd_pcm_lib_buffer_bytes(substream), + snd_pcm_lib_period_bytes(substream)); + + lpass_lpaif_int_enable(soc_runtime->platform); + lpass_lpaif_dma_start(soc_runtime->platform); + + return 0; +} + +static int lpass_pcm_mi2s_mmap(struct snd_pcm_substream *substream, + struct vm_area_struct *vma) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + + return dma_mmap_coherent(substream->pcm->card->dev, vma, + runtime->dma_area, runtime->dma_addr, runtime->dma_bytes); +} + +static snd_pcm_uframes_t lpass_pcm_mi2s_pointer( + struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + struct snd_soc_pcm_runtime *soc_runtime = substream->private_data; + struct lpass_mi2s_data *drvdata = + snd_soc_platform_get_drvdata(soc_runtime->platform); + snd_pcm_uframes_t offset; + + offset = drvdata->period_index * runtime->period_size; + + return offset >= (runtime->buffer_size) ? 0 : offset; +} + +static struct snd_pcm_ops lpass_pcm_mi2s_soc_ops = { + .open = lpass_pcm_mi2s_open, + .hw_params = lpass_pcm_mi2s_hw_params, + .hw_free = lpass_pcm_mi2s_hw_free, + .prepare = lpass_pcm_mi2s_prepare, + .mmap = lpass_pcm_mi2s_mmap, + .pointer = lpass_pcm_mi2s_pointer, + .ioctl = snd_pcm_lib_ioctl, +}; + +static int lpass_pcm_mi2s_soc_new(struct snd_soc_pcm_runtime *soc_runtime) +{ + struct snd_card *card = soc_runtime->card->snd_card; + struct snd_pcm *pcm = soc_runtime->pcm; + struct snd_pcm_substream *substream = + pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream; + struct lpass_mi2s_data *drvdata = + snd_soc_platform_get_drvdata(soc_runtime->platform); + int ret; + + if (!card->dev->coherent_dma_mask) + card->dev->coherent_dma_mask = DMA_BIT_MASK(32); + + if (!card->dev->dma_mask) + card->dev->dma_mask = &card->dev->coherent_dma_mask; + + ret = lpass_pcm_mi2s_alloc_buffer(pcm, SNDRV_PCM_STREAM_PLAYBACK); + if (ret) + return ret; + + ret = request_irq(drvdata->irqnum, lpass_pcm_mi2s_irq, + IRQF_TRIGGER_RISING, "lpass-lpaif-intr", substream); + if (ret) { + dev_err(soc_runtime->dev, "%s: irq resource request failed\n", + __func__); + goto err_buf; + } + + /* ensure DMA hw is turned off */ + lpass_lpaif_dma_stop_clear(soc_runtime->platform); + lpass_lpaif_int_disable(soc_runtime->platform); + + return 0; + +err_buf: + lpass_pcm_mi2s_free_buffer(pcm, SNDRV_PCM_STREAM_PLAYBACK); + return ret; +} + +static void lpass_pcm_mi2s_soc_free(struct snd_pcm *pcm) +{ + struct snd_pcm_substream *substream = + pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream; + struct snd_soc_pcm_runtime *soc_runtime = substream->private_data; + struct lpass_mi2s_data *drvdata = + snd_soc_platform_get_drvdata(soc_runtime->platform); + + lpass_pcm_mi2s_free_buffer(pcm, SNDRV_PCM_STREAM_PLAYBACK); + + disable_irq(drvdata->irqnum); + free_irq(drvdata->irqnum, NULL); +} + +static struct snd_soc_platform_driver lpass_pcm_mi2s_soc_driver = { + .pcm_new = lpass_pcm_mi2s_soc_new, + .pcm_free = lpass_pcm_mi2s_soc_free, + .ops = &lpass_pcm_mi2s_soc_ops, +}; + +int lpass_pcm_mi2s_platform_register(struct device *dev) +{ + return devm_snd_soc_register_platform(dev, &lpass_pcm_mi2s_soc_driver); +} + +MODULE_DESCRIPTION("QCOM LPASS MI2S PLATFORM DRIVER"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" DRV_NAME);

From: Kenneth Westfield kwestfie@codeaurora.org

Now all drivers are in place, allow them to build.

Signed-off-by: Kenneth Westfield kwestfie@codeaurora.org Acked-by: Banajit Goswami bgoswami@codeaurora.org --- sound/soc/qcom/Kconfig | 27 +++++++++++++++++++++++++++ sound/soc/qcom/Makefile | 6 ++++++ 2 files changed, 33 insertions(+) create mode 100644 sound/soc/qcom/Kconfig create mode 100644 sound/soc/qcom/Makefile

diff --git a/sound/soc/qcom/Kconfig b/sound/soc/qcom/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..847530a7fe5caa980b763fc3f77889825c20f47b --- /dev/null +++ b/sound/soc/qcom/Kconfig @@ -0,0 +1,27 @@ +config SND_SOC_QCOM + tristate "SoC Audio support for QCOM platforms" + help + Support for audio in Qualcomm Technologies SOC-based systems. + Say Y if you want to use audio devices such as I2S, PCM, + S/PDIF, etc. + +config SND_SOC_CPU_MI2S + tristate + depends on SND_SOC_QCOM + +config SND_SOC_IPQ806X + tristate "SoC Audio support for IPQ806x based platforms" + depends on SND_SOC_QCOM || ARCH_QCOM || COMPILE_TEST + select SND_SIMPLE_CARD + select SND_SOC_PCM_MI2S + select SND_SOC_CPU_MI2S + select SND_SOC_MAX98357A + help + Support for Qualcomm Technologies LPASS audio block in + IPQ806X SOC-based systems. + Say Y if you want to use audio devices such as I2S, PCM, + S/PDIF, etc. + +config SND_SOC_PCM_MI2S + tristate + depends on SND_SOC_QCOM diff --git a/sound/soc/qcom/Makefile b/sound/soc/qcom/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..214f3617d016386b445466e14e47288f9179590a --- /dev/null +++ b/sound/soc/qcom/Makefile @@ -0,0 +1,6 @@ +# Platform +snd-soc-lpass-pcm-mi2s-objs := lpass-pcm-mi2s.o +snd-soc-lpass-cpu-mi2s-objs := lpass-cpu-mi2s.o + +obj-$(CONFIG_SND_SOC_PCM_MI2S) += snd-soc-lpass-pcm-mi2s.o +obj-$(CONFIG_SND_SOC_CPU_MI2S) += snd-soc-lpass-cpu-mi2s.o

From: Kenneth Westfield kwestfie@codeaurora.org

Model the LPASS audio hardware for the IPQ806X.

Signed-off-by: Kenneth Westfield kwestfie@codeaurora.org Acked-by: Banajit Goswami bgoswami@codeaurora.org --- arch/arm/boot/dts/qcom-ipq8064.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index 63b2146f563b541e4994697af5ee1bbb41a4abd1..f34f29c5683908a5d33c5e1ff14d2c4fb05737df 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -2,6 +2,7 @@

#include "skeleton.dtsi" #include <dt-bindings/clock/qcom,gcc-ipq806x.h> +#include <dt-bindings/clock/qcom,lcc-ipq806x.h> #include <dt-bindings/soc/qcom,gsbi.h>

/ { @@ -66,6 +67,21 @@ ranges; compatible = "simple-bus";

+ lpass-cpu-mi2s { + compatible = "qcom,lpass-cpu-mi2s"; + status = "disabled"; + clocks = <&lcc AHBIX_CLK>, + <&lcc MI2S_OSR_CLK>, + <&lcc MI2S_BIT_CLK>; + clock-names = "ahbix_clk", + "mi2s_osr_clk", + "mi2s_bit_clk"; + interrupts = <0 85 1>; + interrupt-names = "lpass-lpaif-irq"; + reg = <0x28100000 0x10000>; + reg-names = "lpass-lpaif-mem"; + }; + qcom_pinmux: pinmux@800000 { compatible = "qcom,ipq8064-pinctrl"; reg = <0x800000 0x4000>; @@ -279,5 +295,12 @@ #clock-cells = <1>; #reset-cells = <1>; }; + + lcc: clock-controller@28000000 { + compatible = "qcom,lcc-ipq8064"; + reg = <0x28000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; }; };