[alsa-devel] (SoC) Does i.MX27's SSI work as I2S clock master?
Hello, lists.
Now I'm porting WM8728 driver with i.MX27ADS, based on Freescale's BSP kernel(2.6.22) and refering to ALSA SoC git repository.
I'm connecting the WM8728 to the SSI2 controller via SSI-3 signal set. Then, my ADS board has altered: i.MX27 WM8728 --------------------- SSI3_CLK BCLKIN SSI3_FS LRCIN SSI3_TXDAT DIN TOUT/SSI2_MCLK MCLK
Of course, I added some codes to configure GPIO pins as appropriate into board specific sources.
Then, I'm trying to play sounds via WM8728 and have not hear any sounds yet. I checked SSI-3 signal set with an oscilloscope, no clock signal appears on SSI3_CLK. I tried the various SSI setting, I2S normal, I2S master, asychronous/synchronous, normal mode/network mode, ... But, I can't see clock signal, yet.
I want to know an example setting to act i.MX' SSI as I2S clock master.
Regards,
-------------- NOGUCHI Hiroshi ngc@drvlabo.jp
On Wed, Nov 26, 2008 at 04:54:11AM +0900, ngc@drvlabo.jp wrote:
Then, I'm trying to play sounds via WM8728 and have not hear any sounds yet. I checked SSI-3 signal set with an oscilloscope, no clock signal appears on SSI3_CLK. I tried the various SSI setting, I2S normal, I2S master, asychronous/synchronous, normal mode/network mode, ... But, I can't see clock signal, yet.
Is it just SSI3_CLK that produces no output or do you also see nothing on the I2S bit clock, frame sync and data signals?
I want to know an example setting to act i.MX' SSI as I2S clock master.
I'm not aware of any public examples of i.MX code other than what is in the ASoC git repository and the Freescale BSPs, and the only example I can see in ASoC git is for i.MX31.
On Tue, 2008-11-25 at 20:27 +0000, Mark Brown wrote:
On Wed, Nov 26, 2008 at 04:54:11AM +0900, ngc@drvlabo.jp wrote:
Then, I'm trying to play sounds via WM8728 and have not hear any sounds yet. I checked SSI-3 signal set with an oscilloscope, no clock signal appears on SSI3_CLK. I tried the various SSI setting, I2S normal, I2S master, asychronous/synchronous, normal mode/network mode, ... But, I can't see clock signal, yet.
Is it just SSI3_CLK that produces no output or do you also see nothing on the I2S bit clock, frame sync and data signals?
I want to know an example setting to act i.MX' SSI as I2S clock master.
I'm not aware of any public examples of i.MX code other than what is in the ASoC git repository and the Freescale BSPs, and the only example I can see in ASoC git is for i.MX31.
It's probably also worth checking your AUDMUX settings wrt to SSI clock source and direction, SSI controller clock and SSI GPIO's.
Liam
On Dienstag, 25. November 2008, ngc@drvlabo.jp wrote:
Now I'm porting WM8728 driver with i.MX27ADS, based on Freescale's BSP kernel(2.6.22) and refering to ALSA SoC git repository.
I'm connecting the WM8728 to the SSI2 controller via SSI-3 signal set. Then, my ADS board has altered: i.MX27 WM8728
SSI3_CLK BCLKIN SSI3_FS LRCIN SSI3_TXDAT DIN TOUT/SSI2_MCLK MCLK
Of course, I added some codes to configure GPIO pins as appropriate into board specific sources.
Then, I'm trying to play sounds via WM8728 and have not hear any sounds yet. I checked SSI-3 signal set with an oscilloscope, no clock signal appears on SSI3_CLK. I tried the various SSI setting, I2S normal, I2S master, asychronous/synchronous, normal mode/network mode, ... But, I can't see clock signal, yet.
I want to know an example setting to act i.MX' SSI as I2S clock master.
Maybe the SPI-DAM-PIN mapping could help you:
SSI1_* pin group is port 4 at the DAM unit SSI2_* pin group is port 5 at the DAM unit SSI3_* pin group is port 6 at the DAM unit SSI4_* pin group is port 3 at the DAM unit
I didn't find this info in the datasheet yet.
Regards, Juergen
Hello.
I found some mistakes. - AUDMUX configuration : Tx clock/fs direction I noticed this mistake when checking i.MX21's applicaton note #2628. The descriptions in the reference manual is very hard to understand the AUDMUX's specfications. - in ADS board, TOUT/SSI2_MCLK is used to receive IRQ from MC13783, there is a conflict and the pin configuration was overwritten when register IRQ handler.
After correct the above mistakes, I could see the signals: SSI_CLK,FS,TxDAT and MCLK. But, still I have a problem. Though I want to provide an oversampling clock with MCLK to the codec device, now the frequency of MCLK is same as SSI_CLK. Can't the MCLK provide the oversampling frequency?
Now I'm porting WM8728 driver with i.MX27ADS, based on Freescale's BSP kernel(2.6.22) and refering to ALSA SoC git repository.
I checked SSI-3 signal set with an oscilloscope, no clock signal appears on SSI3_CLK. I tried the various SSI setting, I2S normal, I2S master, asychronous/synchronous, normal mode/network mode, ... But, I can't see clock signal, yet.
On Sun, Nov 30, 2008 at 4:47 PM, ngc ngc@drvlabo.jp wrote:
Though I want to provide an oversampling clock with MCLK to the codec device, now the frequency of MCLK is same as SSI_CLK. Can't the MCLK provide the oversampling frequency?
I wrote the SSI driver for the MPC8610. It's the same circuitry, so I presume the same rules apply.
The main SSI clock must be 64 times the sample rate. This is because the SSI uses a clock pulse to send out one bit of sample. Each sample is normally 32 bits, of which only the most significant 24 have any real value. Since I2S is always stereo, 32 * 2 = 64 pulses per sample.
Does that answer your question?
participants (6)
-
Juergen Beisert -
Liam Girdwood -
Mark Brown -
ngc -
ngc＠drvlabo.jp
-
Timur Tabi