[alsa-devel] [PATCH] ASoC: adau1701: Add 44.1 KHz to supported sample rates
From: Pascal Huerst pascal.huerst@gmail.com
According to the datasheet, this device does also support 44.1 KHz as sample rate. This adds the necessary changes to support this.
See Datasheet: Rev. B / page 39 / SR[1:0]
Signed-off-by: Pascal Huerst pascal.huerst@gmail.com --- sound/soc/codecs/adau1701.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/sound/soc/codecs/adau1701.c b/sound/soc/codecs/adau1701.c index de53c0d..8b3ba51 100644 --- a/sound/soc/codecs/adau1701.c +++ b/sound/soc/codecs/adau1701.c @@ -459,6 +459,7 @@ static int adau1701_hw_params(struct snd_pcm_substream *substream, case 96000: val = ADAU1701_DSPCTRL_SR_96; break; + case 44100: case 48000: val = ADAU1701_DSPCTRL_SR_48; break; @@ -623,8 +624,8 @@ static int adau1701_startup(struct snd_pcm_substream *substream, return sigmadsp_restrict_params(adau1701->sigmadsp, substream); }
-#define ADAU1701_RATES (SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | \ - SNDRV_PCM_RATE_192000) +#define ADAU1701_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\ + SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
#define ADAU1701_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ SNDRV_PCM_FMTBIT_S24_LE)
On 10/15/2015 01:16 PM, pascal.huerst@gmail.com wrote:
From: Pascal Huerst pascal.huerst@gmail.com
According to the datasheet, this device does also support 44.1 KHz as sample rate. This adds the necessary changes to support this.
See Datasheet: Rev. B / page 39 / SR[1:0]
Signed-off-by: Pascal Huerst pascal.huerst@gmail.com
Hm, right. The sample rates that part can run at depend on the external clock rate. It can run at ext_clk / 256, ext_clk / 128 or ext_clk / 64. Maybe we should just implement it like that.
Do you have support for switching the external clock at runtime on your platform?
sound/soc/codecs/adau1701.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/sound/soc/codecs/adau1701.c b/sound/soc/codecs/adau1701.c index de53c0d..8b3ba51 100644 --- a/sound/soc/codecs/adau1701.c +++ b/sound/soc/codecs/adau1701.c @@ -459,6 +459,7 @@ static int adau1701_hw_params(struct snd_pcm_substream *substream, case 96000: val = ADAU1701_DSPCTRL_SR_96; break;
- case 44100: case 48000: val = ADAU1701_DSPCTRL_SR_48; break;
@@ -623,8 +624,8 @@ static int adau1701_startup(struct snd_pcm_substream *substream, return sigmadsp_restrict_params(adau1701->sigmadsp, substream); }
-#define ADAU1701_RATES (SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | \
- SNDRV_PCM_RATE_192000)
+#define ADAU1701_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
- SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
#define ADAU1701_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ SNDRV_PCM_FMTBIT_S24_LE)
On 20.10.2015 11:10, Lars-Peter Clausen wrote:
On 10/15/2015 01:16 PM, pascal.huerst@gmail.com wrote:
From: Pascal Huerst pascal.huerst@gmail.com
According to the datasheet, this device does also support 44.1 KHz as sample rate. This adds the necessary changes to support this.
See Datasheet: Rev. B / page 39 / SR[1:0]
Signed-off-by: Pascal Huerst pascal.huerst@gmail.com
Hm, right. The sample rates that part can run at depend on the external clock rate. It can run at ext_clk / 256, ext_clk / 128 or ext_clk / 64. Maybe we should just implement it like that.
Do you have support for switching the external clock at runtime on your platform?
Yes, I can switch th eclock at runtime.
sound/soc/codecs/adau1701.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/sound/soc/codecs/adau1701.c b/sound/soc/codecs/adau1701.c index de53c0d..8b3ba51 100644 --- a/sound/soc/codecs/adau1701.c +++ b/sound/soc/codecs/adau1701.c @@ -459,6 +459,7 @@ static int adau1701_hw_params(struct snd_pcm_substream *substream, case 96000: val = ADAU1701_DSPCTRL_SR_96; break;
- case 44100: case 48000: val = ADAU1701_DSPCTRL_SR_48; break;
@@ -623,8 +624,8 @@ static int adau1701_startup(struct snd_pcm_substream *substream, return sigmadsp_restrict_params(adau1701->sigmadsp, substream); }
-#define ADAU1701_RATES (SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | \
- SNDRV_PCM_RATE_192000)
+#define ADAU1701_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
- SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
#define ADAU1701_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ SNDRV_PCM_FMTBIT_S24_LE)
On 11/11/2015 12:40 PM, Pascal Huerst wrote:
On 20.10.2015 11:10, Lars-Peter Clausen wrote:
On 10/15/2015 01:16 PM, pascal.huerst@gmail.com wrote:
From: Pascal Huerst pascal.huerst@gmail.com
According to the datasheet, this device does also support 44.1 KHz as sample rate. This adds the necessary changes to support this.
See Datasheet: Rev. B / page 39 / SR[1:0]
Signed-off-by: Pascal Huerst pascal.huerst@gmail.com
Hm, right. The sample rates that part can run at depend on the external clock rate. It can run at ext_clk / 256, ext_clk / 128 or ext_clk / 64. Maybe we should just implement it like that.
Do you have support for switching the external clock at runtime on your platform?
Yes, I can switch th eclock at runtime.
How do you do it? From the board driver?
- Lars
On 11.11.2015 12:49, Lars-Peter Clausen wrote:
On 11/11/2015 12:40 PM, Pascal Huerst wrote:
On 20.10.2015 11:10, Lars-Peter Clausen wrote:
On 10/15/2015 01:16 PM, pascal.huerst@gmail.com wrote:
From: Pascal Huerst pascal.huerst@gmail.com
According to the datasheet, this device does also support 44.1 KHz as sample rate. This adds the necessary changes to support this.
See Datasheet: Rev. B / page 39 / SR[1:0]
Signed-off-by: Pascal Huerst pascal.huerst@gmail.com
Hm, right. The sample rates that part can run at depend on the external clock rate. It can run at ext_clk / 256, ext_clk / 128 or ext_clk / 64. Maybe we should just implement it like that.
Do you have support for switching the external clock at runtime on your platform?
Yes, I can switch th eclock at runtime.
How do you do it? From the board driver?
Yes, in the board driver, within the .hw_params callback.
- Lars
Alsa-devel mailing list Alsa-devel@alsa-project.org http://mailman.alsa-project.org/mailman/listinfo/alsa-devel
On 20.10.2015 11:10, Lars-Peter Clausen wrote:
On 10/15/2015 01:16 PM, pascal.huerst@gmail.com wrote:
From: Pascal Huerst pascal.huerst@gmail.com
According to the datasheet, this device does also support 44.1 KHz as sample rate. This adds the necessary changes to support this.
See Datasheet: Rev. B / page 39 / SR[1:0]
Signed-off-by: Pascal Huerst pascal.huerst@gmail.com
Hm, right. The sample rates that part can run at depend on the external clock rate. It can run at ext_clk / 256, ext_clk / 128 or ext_clk / 64. Maybe we should just implement it like that.
Don't you think, that it is just consistent to add 44100, just as the other sample rates that are supported?
Do you have support for switching the external clock at runtime on your platform?
sound/soc/codecs/adau1701.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/sound/soc/codecs/adau1701.c b/sound/soc/codecs/adau1701.c index de53c0d..8b3ba51 100644 --- a/sound/soc/codecs/adau1701.c +++ b/sound/soc/codecs/adau1701.c @@ -459,6 +459,7 @@ static int adau1701_hw_params(struct snd_pcm_substream *substream, case 96000: val = ADAU1701_DSPCTRL_SR_96; break;
- case 44100: case 48000: val = ADAU1701_DSPCTRL_SR_48; break;
@@ -623,8 +624,8 @@ static int adau1701_startup(struct snd_pcm_substream *substream, return sigmadsp_restrict_params(adau1701->sigmadsp, substream); }
-#define ADAU1701_RATES (SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | \
- SNDRV_PCM_RATE_192000)
+#define ADAU1701_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
- SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
#define ADAU1701_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ SNDRV_PCM_FMTBIT_S24_LE)
participants (3)
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pascal.huerst＠gmail.com