[alsa-devel] [PATCH] ASoC: adau17x1: Cache writes when core clock is disabled
In some configurations, the dai registers get written before the bias level is changed in the codec driver. This leads to a situation where an initial write to the serial port register gets ignored, and future writes may as well, since regmap thinks that the codec already holds the value. More specifically, configuring the codec as i2s master would in fact result in the codec running as slave, a situation where no i2s clocks are generated and hence no data is transferred.
This change makes sure that regmap only caches writes when the core clock is disabled, and syncs regmap whenever enabling the core clock again.
Signed-off-by: Andreas Irestål andire@axis.com --- sound/soc/codecs/adau1761.c | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/sound/soc/codecs/adau1761.c b/sound/soc/codecs/adau1761.c index 2f12477..e7136b1 100644 --- a/sound/soc/codecs/adau1761.c +++ b/sound/soc/codecs/adau1761.c @@ -456,13 +456,17 @@ static int adau1761_set_bias_level(struct snd_soc_codec *codec, case SND_SOC_BIAS_PREPARE: break; case SND_SOC_BIAS_STANDBY: + regcache_cache_only(adau->regmap, false); regmap_update_bits(adau->regmap, ADAU17X1_CLOCK_CONTROL, ADAU17X1_CLOCK_CONTROL_SYSCLK_EN, ADAU17X1_CLOCK_CONTROL_SYSCLK_EN); + if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) + regcache_sync(adau->regmap); break; case SND_SOC_BIAS_OFF: regmap_update_bits(adau->regmap, ADAU17X1_CLOCK_CONTROL, ADAU17X1_CLOCK_CONTROL_SYSCLK_EN, 0); + regcache_cache_only(adau->regmap, true); break;
} @@ -783,6 +787,10 @@ int adau1761_probe(struct device *dev, struct regmap *regmap, if (ret) return ret;
+ /* Enable cache only mode as we could miss writes before bias level + * reaches standby and the core clock is enabled */ + regcache_cache_only(regmap, true); + return snd_soc_register_codec(dev, &adau1761_codec_driver, dai_drv, 1); } EXPORT_SYMBOL_GPL(adau1761_probe);
On 02/04/2016 03:05 PM, Andreas Irestål wrote:
In some configurations, the dai registers get written before the bias level is changed in the codec driver. This leads to a situation where an initial write to the serial port register gets ignored, and future writes may as well, since regmap thinks that the codec already holds the value. More specifically, configuring the codec as i2s master would in fact result in the codec running as slave, a situation where no i2s clocks are generated and hence no data is transferred.
This change makes sure that regmap only caches writes when the core clock is disabled, and syncs regmap whenever enabling the core clock again.
Signed-off-by: Andreas Irestål andire@axis.com
Looks good, thanks for the patch.
Acked-by: Lars-Peter Clausen lars@metafoo.de
sound/soc/codecs/adau1761.c | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/sound/soc/codecs/adau1761.c b/sound/soc/codecs/adau1761.c index 2f12477..e7136b1 100644 --- a/sound/soc/codecs/adau1761.c +++ b/sound/soc/codecs/adau1761.c @@ -456,13 +456,17 @@ static int adau1761_set_bias_level(struct snd_soc_codec *codec, case SND_SOC_BIAS_PREPARE: break; case SND_SOC_BIAS_STANDBY:
regcache_cache_only(adau->regmap, false);regmap_update_bits(adau->regmap, ADAU17X1_CLOCK_CONTROL, ADAU17X1_CLOCK_CONTROL_SYSCLK_EN, ADAU17X1_CLOCK_CONTROL_SYSCLK_EN);
if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF)regcache_sync(adau->regmap);break; case SND_SOC_BIAS_OFF: regmap_update_bits(adau->regmap, ADAU17X1_CLOCK_CONTROL, ADAU17X1_CLOCK_CONTROL_SYSCLK_EN, 0);
regcache_cache_only(adau->regmap, true);break;
}
@@ -783,6 +787,10 @@ int adau1761_probe(struct device *dev, struct regmap *regmap, if (ret) return ret;
- /* Enable cache only mode as we could miss writes before bias level
* reaches standby and the core clock is enabled */- regcache_cache_only(regmap, true);
There are a few register writes before this where the hardware configuration is setup. When I look at my test setup those writes seem to go through, even though they shouldn't according to what you say (and to what is written in the datasheet).
On the other hand I've never seen the issue you are having either and I've tested both master and slave configuration of the device. Maybe something changed in the silicon in newer revisions of the device. Can you take a look whether the hardware configuration is correctly applied for you?
return snd_soc_register_codec(dev, &adau1761_codec_driver, dai_drv, 1); } EXPORT_SYMBOL_GPL(adau1761_probe);
On 02/04/2016 06:22 PM, Lars-Peter Clausen wrote: [...]
- /* Enable cache only mode as we could miss writes before bias level
* reaches standby and the core clock is enabled */- regcache_cache_only(regmap, true);
There are a few register writes before this where the hardware configuration is setup. When I look at my test setup those writes seem to go through, even though they shouldn't according to what you say (and to what is written in the datasheet).
On the other hand I've never seen the issue you are having either and I've tested both master and slave configuration of the device. Maybe something changed in the silicon in newer revisions of the device. Can you take a look whether the hardware configuration is correctly applied for you?
Ah, no, ignore that. Those writes happen later on.
On Thu, Feb 04, 2016 at 06:24:08PM +0100, Lars-Peter Clausen wrote:
On 02/04/2016 06:22 PM, Lars-Peter Clausen wrote: [...]
- /* Enable cache only mode as we could miss writes before bias level
* reaches standby and the core clock is enabled */- regcache_cache_only(regmap, true);
There are a few register writes before this where the hardware configuration is setup. When I look at my test setup those writes seem to go through, even though they shouldn't according to what you say (and to what is written in the datasheet).
On the other hand I've never seen the issue you are having either and I've tested both master and slave configuration of the device. Maybe something changed in the silicon in newer revisions of the device. Can you take a look whether the hardware configuration is correctly applied for you?
Ah, no, ignore that. Those writes happen later on.
The whole thing depends on what driver you are using. We had our own board drivers before moving to DT, where we would call set_dai_fmt in hw_params, so the register would get written again before we wanted to do something useful anyway. The simple-card driver only set the dai format at probing time and never again, so that's why we started to notice this issue.
I posted a set of patches a few days ago which added DT support and fixed minor things in adau17x1, but I realized I was clumsy just sending it to the alsa-devel list and not including DT maintainers or any maintainers at all. Would you have a look at it, or do you want me to resubmit the patches with the correct recipents?
/Andreas
On Thu, Feb 04, 2016 at 08:01:30PM +0100, Andreas Irestål wrote:
I posted a set of patches a few days ago which added DT support and fixed minor things in adau17x1, but I realized I was clumsy just sending it to the alsa-devel list and not including DT maintainers or any maintainers at all. Would you have a look at it, or do you want me to resubmit the patches with the correct recipents?
I'm not likely to look at things that don't get sent to me.
The patch
ASoC: adau17x1: Cache writes when core clock is disabled
has been applied to the asoc tree at
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git
All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying to this mail.
Thanks, Mark
From 27d6e7d1c96c9f51379e0feb972fec26029098bc Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Andreas=20Irest=C3=A5l?= andreas.irestal@axis.com Date: Thu, 4 Feb 2016 15:05:19 +0100 Subject: [PATCH] ASoC: adau17x1: Cache writes when core clock is disabled MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit
In some configurations, the dai registers get written before the bias level is changed in the codec driver. This leads to a situation where an initial write to the serial port register gets ignored, and future writes may as well, since regmap thinks that the codec already holds the value. More specifically, configuring the codec as i2s master would in fact result in the codec running as slave, a situation where no i2s clocks are generated and hence no data is transferred.
This change makes sure that regmap only caches writes when the core clock is disabled, and syncs regmap whenever enabling the core clock again.
Signed-off-by: Andreas Irestål andire@axis.com Acked-by: Lars-Peter Clausen lars@metafoo.de Signed-off-by: Mark Brown broonie@kernel.org --- sound/soc/codecs/adau1761.c | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/sound/soc/codecs/adau1761.c b/sound/soc/codecs/adau1761.c index 2f12477..e7136b1 100644 --- a/sound/soc/codecs/adau1761.c +++ b/sound/soc/codecs/adau1761.c @@ -456,13 +456,17 @@ static int adau1761_set_bias_level(struct snd_soc_codec *codec, case SND_SOC_BIAS_PREPARE: break; case SND_SOC_BIAS_STANDBY: + regcache_cache_only(adau->regmap, false); regmap_update_bits(adau->regmap, ADAU17X1_CLOCK_CONTROL, ADAU17X1_CLOCK_CONTROL_SYSCLK_EN, ADAU17X1_CLOCK_CONTROL_SYSCLK_EN); + if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) + regcache_sync(adau->regmap); break; case SND_SOC_BIAS_OFF: regmap_update_bits(adau->regmap, ADAU17X1_CLOCK_CONTROL, ADAU17X1_CLOCK_CONTROL_SYSCLK_EN, 0); + regcache_cache_only(adau->regmap, true); break;
} @@ -783,6 +787,10 @@ int adau1761_probe(struct device *dev, struct regmap *regmap, if (ret) return ret;
+ /* Enable cache only mode as we could miss writes before bias level + * reaches standby and the core clock is enabled */ + regcache_cache_only(regmap, true); + return snd_soc_register_codec(dev, &adau1761_codec_driver, dai_drv, 1); } EXPORT_SYMBOL_GPL(adau1761_probe);
participants (3)
-
Andreas Irestål -
Lars-Peter Clausen -
Mark Brown