[alsa-devel] [PATCH v1 0/4] Patches to fix some problem for rockchip i2s
These patches to fix some problem for rockchip i2s.
Sugar Zhang (3): ASoC: rockchip: i2s: add a delay before i2s clear ASoC: rockchip: i2s: add support for i2s bclk fs configuration ASoC: rockchip: i2s: fixup clk div
zhangjun (1): ASoC: rockchip: i2s: add other configurable formats
.../devicetree/bindings/sound/rockchip-i2s.txt | 2 + sound/soc/rockchip/rockchip_i2s.c | 45 +++++++++++++++++++--- sound/soc/rockchip/rockchip_i2s.h | 3 ++ 3 files changed, 45 insertions(+), 5 deletions(-)
in order to guarantee i2s lrck signal integrity, when i2s stop, need at least one lrck cycle to ensure signal integrity.
the max delay time is when lrck is 8khz, the delay time is 125us(1/8khz), using udelay(150) with a 25us margin.
Signed-off-by: Sugar Zhang sugar.zhang@rock-chips.com ---
sound/soc/rockchip/rockchip_i2s.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/sound/soc/rockchip/rockchip_i2s.c b/sound/soc/rockchip/rockchip_i2s.c index 974915c..f548433 100644 --- a/sound/soc/rockchip/rockchip_i2s.c +++ b/sound/soc/rockchip/rockchip_i2s.c @@ -116,6 +116,7 @@ static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on) I2S_XFER_TXS_STOP | I2S_XFER_RXS_STOP);
+ udelay(150); regmap_update_bits(i2s->regmap, I2S_CLR, I2S_CLR_TXC | I2S_CLR_RXC, I2S_CLR_TXC | I2S_CLR_RXC); @@ -162,6 +163,7 @@ static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on) I2S_XFER_TXS_STOP | I2S_XFER_RXS_STOP);
+ udelay(150); regmap_update_bits(i2s->regmap, I2S_CLR, I2S_CLR_TXC | I2S_CLR_RXC, I2S_CLR_TXC | I2S_CLR_RXC);
The patch
ASoC: rockchip: i2s: add a delay before i2s clear
has been applied to the asoc tree at
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git
All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying to this mail.
Thanks, Mark
From 5894b91d1e700f38b4157df143be1502cf08daa8 Mon Sep 17 00:00:00 2001
From: Sugar Zhang sugar.zhang@rock-chips.com Date: Fri, 9 Jun 2017 16:52:46 +0800 Subject: [PATCH] ASoC: rockchip: i2s: add a delay before i2s clear
in order to guarantee i2s lrck signal integrity, when i2s stop, need at least one lrck cycle to ensure signal integrity.
the max delay time is when lrck is 8khz, the delay time is 125us(1/8khz), using udelay(150) with a 25us margin.
Signed-off-by: Sugar Zhang sugar.zhang@rock-chips.com Signed-off-by: Mark Brown broonie@kernel.org --- sound/soc/rockchip/rockchip_i2s.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/sound/soc/rockchip/rockchip_i2s.c b/sound/soc/rockchip/rockchip_i2s.c index 974915cb4c4f..f54843342ee2 100644 --- a/sound/soc/rockchip/rockchip_i2s.c +++ b/sound/soc/rockchip/rockchip_i2s.c @@ -116,6 +116,7 @@ static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on) I2S_XFER_TXS_STOP | I2S_XFER_RXS_STOP);
+ udelay(150); regmap_update_bits(i2s->regmap, I2S_CLR, I2S_CLR_TXC | I2S_CLR_RXC, I2S_CLR_TXC | I2S_CLR_RXC); @@ -162,6 +163,7 @@ static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on) I2S_XFER_TXS_STOP | I2S_XFER_RXS_STOP);
+ udelay(150); regmap_update_bits(i2s->regmap, I2S_CLR, I2S_CLR_TXC | I2S_CLR_RXC, I2S_CLR_TXC | I2S_CLR_RXC);
this patch add support for i2s bclk fs configuration, we can configure bclk_fs by devicetree as required.
Signed-off-by: Sugar Zhang sugar.zhang@rock-chips.com ---
Documentation/devicetree/bindings/sound/rockchip-i2s.txt | 2 ++ sound/soc/rockchip/rockchip_i2s.c | 9 ++++++++- 2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/sound/rockchip-i2s.txt b/Documentation/devicetree/bindings/sound/rockchip-i2s.txt index 206aba1..de3cbbe 100644 --- a/Documentation/devicetree/bindings/sound/rockchip-i2s.txt +++ b/Documentation/devicetree/bindings/sound/rockchip-i2s.txt @@ -23,6 +23,7 @@ Required properties: - "i2s_clk" : clock for I2S controller - rockchip,playback-channels: max playback channels, if not set, 8 channels default. - rockchip,capture-channels: max capture channels, if not set, 2 channels default. +- rockchip,bclk-fs: configure the i2s bclk fs.
Required properties for controller which support multi channels playback/capture: @@ -41,4 +42,5 @@ i2s@ff890000 { clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; rockchip,playback-channels = <8>; rockchip,capture-channels = <2>; + rockchip,bclk-fs = <128>; }; diff --git a/sound/soc/rockchip/rockchip_i2s.c b/sound/soc/rockchip/rockchip_i2s.c index f548433..220232b 100644 --- a/sound/soc/rockchip/rockchip_i2s.c +++ b/sound/soc/rockchip/rockchip_i2s.c @@ -51,6 +51,7 @@ struct rk_i2s_dev { bool rx_start; bool is_master_mode; const struct rk_i2s_pins *pins; + unsigned int bclk_fs; };
static int i2s_runtime_suspend(struct device *dev) @@ -254,7 +255,7 @@ static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
if (i2s->is_master_mode) { mclk_rate = clk_get_rate(i2s->mclk); - bclk_rate = 2 * 32 * params_rate(params); + bclk_rate = i2s->bclk_fs * params_rate(params); if (bclk_rate && mclk_rate % bclk_rate) return -EINVAL;
@@ -633,6 +634,12 @@ static int rockchip_i2s_probe(struct platform_device *pdev) soc_dai->capture.channels_max = val; }
+ i2s->bclk_fs = 64; + if (!of_property_read_u32(node, "rockchip,bclk-fs", &val)) { + if ((val >= 32) && (val % 2 == 0)) + i2s->bclk_fs = val; + } + ret = devm_snd_soc_register_component(&pdev->dev, &rockchip_i2s_component, soc_dai, 1);
On Fri, Jun 09, 2017 at 04:52:47PM +0800, Sugar Zhang wrote:
+- rockchip,bclk-fs: configure the i2s bclk fs.
Rather than having a driver DT property for this the device should implement a set_bclk_ratio() operation and let the ratio be set by the machine driver. The simple and graph cards may need extending for that, I know they have MCLK configuration support already.
From: zhangjun zhangjun@rock-chips.com
simple-audio-card,bitclock-inversion = <1> : bclk falling edge taken simple-audio-card,format = "dsp_a" : pcm no delay mode simple-audio-card,format = "dsp_b" : pcm late 1 mode
Signed-off-by: zhangjun zhangjun@rock-chips.com Signed-off-by: Sugar Zhang sugar.zhang@rock-chips.com ---
sound/soc/rockchip/rockchip_i2s.c | 30 ++++++++++++++++++++++++++++-- sound/soc/rockchip/rockchip_i2s.h | 3 +++ 2 files changed, 31 insertions(+), 2 deletions(-)
diff --git a/sound/soc/rockchip/rockchip_i2s.c b/sound/soc/rockchip/rockchip_i2s.c index 220232b..2a15a00 100644 --- a/sound/soc/rockchip/rockchip_i2s.c +++ b/sound/soc/rockchip/rockchip_i2s.c @@ -207,7 +207,21 @@ static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
- mask = I2S_TXCR_IBM_MASK; + mask = I2S_CKR_CKP_MASK; + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_NB_NF: + val = I2S_CKR_CKP_NEG; + break; + case SND_SOC_DAIFMT_IB_NF: + val = I2S_CKR_CKP_POS; + break; + default: + return -EINVAL; + } + + regmap_update_bits(i2s->regmap, I2S_CKR, mask, val); + + mask = I2S_TXCR_IBM_MASK | I2S_TXCR_TFS_MASK | I2S_TXCR_PBM_MASK; switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { case SND_SOC_DAIFMT_RIGHT_J: val = I2S_TXCR_IBM_RSJM; @@ -218,13 +232,19 @@ static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai, case SND_SOC_DAIFMT_I2S: val = I2S_TXCR_IBM_NORMAL; break; + case SND_SOC_DAIFMT_DSP_A: /* PCM no delay mode */ + val = I2S_TXCR_TFS_PCM; + break; + case SND_SOC_DAIFMT_DSP_B: /* PCM delay 1 mode */ + val = I2S_TXCR_TFS_PCM | I2S_TXCR_PBM_MODE(1); + break; default: return -EINVAL; }
regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val);
- mask = I2S_RXCR_IBM_MASK; + mask = I2S_RXCR_IBM_MASK | I2S_RXCR_TFS_MASK | I2S_RXCR_PBM_MASK; switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { case SND_SOC_DAIFMT_RIGHT_J: val = I2S_RXCR_IBM_RSJM; @@ -235,6 +255,12 @@ static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai, case SND_SOC_DAIFMT_I2S: val = I2S_RXCR_IBM_NORMAL; break; + case SND_SOC_DAIFMT_DSP_A: /* PCM no delay mode */ + val = I2S_RXCR_TFS_PCM; + break; + case SND_SOC_DAIFMT_DSP_B: /* PCM delay 1 mode */ + val = I2S_RXCR_TFS_PCM | I2S_RXCR_PBM_MODE(1); + break; default: return -EINVAL; } diff --git a/sound/soc/rockchip/rockchip_i2s.h b/sound/soc/rockchip/rockchip_i2s.h index 31f11fd..a7b8527 100644 --- a/sound/soc/rockchip/rockchip_i2s.h +++ b/sound/soc/rockchip/rockchip_i2s.h @@ -41,6 +41,7 @@ #define I2S_TXCR_TFS_SHIFT 5 #define I2S_TXCR_TFS_I2S (0 << I2S_TXCR_TFS_SHIFT) #define I2S_TXCR_TFS_PCM (1 << I2S_TXCR_TFS_SHIFT) +#define I2S_TXCR_TFS_MASK (1 << I2S_TXCR_TFS_SHIFT) #define I2S_TXCR_VDW_SHIFT 0 #define I2S_TXCR_VDW(x) ((x - 1) << I2S_TXCR_VDW_SHIFT) #define I2S_TXCR_VDW_MASK (0x1f << I2S_TXCR_VDW_SHIFT) @@ -70,6 +71,7 @@ #define I2S_RXCR_TFS_SHIFT 5 #define I2S_RXCR_TFS_I2S (0 << I2S_RXCR_TFS_SHIFT) #define I2S_RXCR_TFS_PCM (1 << I2S_RXCR_TFS_SHIFT) +#define I2S_RXCR_TFS_MASK (1 << I2S_RXCR_TFS_SHIFT) #define I2S_RXCR_VDW_SHIFT 0 #define I2S_RXCR_VDW(x) ((x - 1) << I2S_RXCR_VDW_SHIFT) #define I2S_RXCR_VDW_MASK (0x1f << I2S_RXCR_VDW_SHIFT) @@ -91,6 +93,7 @@ #define I2S_CKR_CKP_SHIFT 26 #define I2S_CKR_CKP_NEG (0 << I2S_CKR_CKP_SHIFT) #define I2S_CKR_CKP_POS (1 << I2S_CKR_CKP_SHIFT) +#define I2S_CKR_CKP_MASK (1 << I2S_CKR_CKP_SHIFT) #define I2S_CKR_RLP_SHIFT 25 #define I2S_CKR_RLP_NORMAL (0 << I2S_CKR_RLP_SHIFT) #define I2S_CKR_RLP_OPPSITE (1 << I2S_CKR_RLP_SHIFT)
The patch
ASoC: rockchip: i2s: add other configurable formats
has been applied to the asoc tree at
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git
All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying to this mail.
Thanks, Mark
From ec2212c4af20d84841ae288a397d8ee9ecec72a0 Mon Sep 17 00:00:00 2001
From: zhangjun zhangjun@rock-chips.com Date: Fri, 9 Jun 2017 16:52:48 +0800 Subject: [PATCH] ASoC: rockchip: i2s: add other configurable formats
simple-audio-card,bitclock-inversion = <1> : bclk falling edge taken simple-audio-card,format = "dsp_a" : pcm no delay mode simple-audio-card,format = "dsp_b" : pcm late 1 mode
Signed-off-by: zhangjun zhangjun@rock-chips.com Signed-off-by: Sugar Zhang sugar.zhang@rock-chips.com Signed-off-by: Mark Brown broonie@kernel.org --- sound/soc/rockchip/rockchip_i2s.c | 30 ++++++++++++++++++++++++++++-- sound/soc/rockchip/rockchip_i2s.h | 3 +++ 2 files changed, 31 insertions(+), 2 deletions(-)
diff --git a/sound/soc/rockchip/rockchip_i2s.c b/sound/soc/rockchip/rockchip_i2s.c index 974915cb4c4f..66a26c56c658 100644 --- a/sound/soc/rockchip/rockchip_i2s.c +++ b/sound/soc/rockchip/rockchip_i2s.c @@ -204,7 +204,21 @@ static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
- mask = I2S_TXCR_IBM_MASK; + mask = I2S_CKR_CKP_MASK; + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_NB_NF: + val = I2S_CKR_CKP_NEG; + break; + case SND_SOC_DAIFMT_IB_NF: + val = I2S_CKR_CKP_POS; + break; + default: + return -EINVAL; + } + + regmap_update_bits(i2s->regmap, I2S_CKR, mask, val); + + mask = I2S_TXCR_IBM_MASK | I2S_TXCR_TFS_MASK | I2S_TXCR_PBM_MASK; switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { case SND_SOC_DAIFMT_RIGHT_J: val = I2S_TXCR_IBM_RSJM; @@ -215,13 +229,19 @@ static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai, case SND_SOC_DAIFMT_I2S: val = I2S_TXCR_IBM_NORMAL; break; + case SND_SOC_DAIFMT_DSP_A: /* PCM no delay mode */ + val = I2S_TXCR_TFS_PCM; + break; + case SND_SOC_DAIFMT_DSP_B: /* PCM delay 1 mode */ + val = I2S_TXCR_TFS_PCM | I2S_TXCR_PBM_MODE(1); + break; default: return -EINVAL; }
regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val);
- mask = I2S_RXCR_IBM_MASK; + mask = I2S_RXCR_IBM_MASK | I2S_RXCR_TFS_MASK | I2S_RXCR_PBM_MASK; switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { case SND_SOC_DAIFMT_RIGHT_J: val = I2S_RXCR_IBM_RSJM; @@ -232,6 +252,12 @@ static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai, case SND_SOC_DAIFMT_I2S: val = I2S_RXCR_IBM_NORMAL; break; + case SND_SOC_DAIFMT_DSP_A: /* PCM no delay mode */ + val = I2S_RXCR_TFS_PCM; + break; + case SND_SOC_DAIFMT_DSP_B: /* PCM delay 1 mode */ + val = I2S_RXCR_TFS_PCM | I2S_RXCR_PBM_MODE(1); + break; default: return -EINVAL; } diff --git a/sound/soc/rockchip/rockchip_i2s.h b/sound/soc/rockchip/rockchip_i2s.h index 31f11fd25393..a7b8527d8a73 100644 --- a/sound/soc/rockchip/rockchip_i2s.h +++ b/sound/soc/rockchip/rockchip_i2s.h @@ -41,6 +41,7 @@ #define I2S_TXCR_TFS_SHIFT 5 #define I2S_TXCR_TFS_I2S (0 << I2S_TXCR_TFS_SHIFT) #define I2S_TXCR_TFS_PCM (1 << I2S_TXCR_TFS_SHIFT) +#define I2S_TXCR_TFS_MASK (1 << I2S_TXCR_TFS_SHIFT) #define I2S_TXCR_VDW_SHIFT 0 #define I2S_TXCR_VDW(x) ((x - 1) << I2S_TXCR_VDW_SHIFT) #define I2S_TXCR_VDW_MASK (0x1f << I2S_TXCR_VDW_SHIFT) @@ -70,6 +71,7 @@ #define I2S_RXCR_TFS_SHIFT 5 #define I2S_RXCR_TFS_I2S (0 << I2S_RXCR_TFS_SHIFT) #define I2S_RXCR_TFS_PCM (1 << I2S_RXCR_TFS_SHIFT) +#define I2S_RXCR_TFS_MASK (1 << I2S_RXCR_TFS_SHIFT) #define I2S_RXCR_VDW_SHIFT 0 #define I2S_RXCR_VDW(x) ((x - 1) << I2S_RXCR_VDW_SHIFT) #define I2S_RXCR_VDW_MASK (0x1f << I2S_RXCR_VDW_SHIFT) @@ -91,6 +93,7 @@ #define I2S_CKR_CKP_SHIFT 26 #define I2S_CKR_CKP_NEG (0 << I2S_CKR_CKP_SHIFT) #define I2S_CKR_CKP_POS (1 << I2S_CKR_CKP_SHIFT) +#define I2S_CKR_CKP_MASK (1 << I2S_CKR_CKP_SHIFT) #define I2S_CKR_RLP_SHIFT 25 #define I2S_CKR_RLP_NORMAL (0 << I2S_CKR_RLP_SHIFT) #define I2S_CKR_RLP_OPPSITE (1 << I2S_CKR_RLP_SHIFT)
we found mclk maybe not precise as required because of PLL, but it still can be used and no side effect. for example, if we require mclk 11289600, but get 11289598, it doesn't matter. so using DIV_ROUND_CLOSEST to fix it.
Signed-off-by: Sugar Zhang sugar.zhang@rock-chips.com
---
sound/soc/rockchip/rockchip_i2s.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/sound/soc/rockchip/rockchip_i2s.c b/sound/soc/rockchip/rockchip_i2s.c index 2a15a00..b56e00d 100644 --- a/sound/soc/rockchip/rockchip_i2s.c +++ b/sound/soc/rockchip/rockchip_i2s.c @@ -282,10 +282,10 @@ static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream, if (i2s->is_master_mode) { mclk_rate = clk_get_rate(i2s->mclk); bclk_rate = i2s->bclk_fs * params_rate(params); - if (bclk_rate && mclk_rate % bclk_rate) + if (!bclk_rate) return -EINVAL;
- div_bclk = mclk_rate / bclk_rate; + div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate); div_lrck = bclk_rate / params_rate(params); regmap_update_bits(i2s->regmap, I2S_CKR, I2S_CKR_MDIV_MASK,
On Fri, Jun 09, 2017 at 04:52:49PM +0800, Sugar Zhang wrote:
we found mclk maybe not precise as required because of PLL, but it still can be used and no side effect. for example, if we require mclk 11289600, but get 11289598, it doesn't matter. so using DIV_ROUND_CLOSEST to fix it.
This is fine but seems to depend on patch 2.
participants (2)
-
Mark Brown -
Sugar Zhang