[alsa-devel] Problem to init AD1938 on i.MX25
Hello,
we're working on an ALSA driver for AD1938 for i.MX25 based system. On the I²S the CODEC is Master. On the SPI, the MCU is Master.
SSI seems to work (when we set the CODEC as Master by Hardware).
We have problems to get the communication via SPI working. The CODEC requires 24Bit words and we can set SPI according to this in the board-file and verify this also with a logic analyzer. However, we can send only one word to the CODEC! This first word is transferred correctly, but all subsequent transfers show no activity on the SPI lines. We do not get any error messages from the SPI drivers! All SPI writes after the first word seem to be executed in software but show not effect in hardware. All reads return 0xff.
We assume that something with the set-up of the platform device is wrong: if we do not set the 24 Bit word size for each message, the SPI transfer is only 8 bit long - only when we set 24 bit in the spi_transfer struct for a transmission, the correct signals appear on the logic analyzer.
Could anybody point us to an example of platform device set-up for a similar CODEC on this MCU? Are there known limitations of SPI transfers on the i.MX24 (like it can do only 8-Bit transfers)?
Any idea for further investigations would be highly appreciated...!
We have the following SPI / SSI set-up in the board file:
static struct pad_desc stk5_ad1938_pads[] = { MX25_PAD_RW__AUD4_TXFS, MX25_PAD_EB0__AUD4_TXD, MX25_PAD_EB1__AUD4_RXD, MX25_PAD_OE__AUD4_TXC, };
static int stk5_ad1938_plat_init(void) { int ret; DBG(0, "%s: \n", __FUNCTION__); ret = mxc_iomux_v3_setup_multiple_pads(stk5_ad1938_pads, ARRAY_SIZE(stk5_ad1938_pads)); return ret; }
static void stk5_ad1938_plat_finit(void) { DBG(0, "%s: \n", __FUNCTION__);
mxc_iomux_v3_release_multiple_pads(stk5_ad1938_pads, ARRAY_SIZE(stk5_ad1938_pads)); }
static struct mxc_audio_platform_data stk5_ad1938_data = { .ssi_num = 0, .src_port = 1, .ext_port = 4, .sysclk = 11289600, .init = stk5_ad1938_plat_init, .finit = stk5_ad1938_plat_finit, };
static struct platform_device stk5_ad1938_device = { .name = "imx-ad1938", .dev = { .platform_data =&stk5_ad1938_data, }, };
static int __init stk5_ad1938_init(void) { DBG(0, "%s: Registering device %s\n", __FUNCTION__, stk5_ad1938_device.name); return platform_device_register(&stk5_ad1938_device); } arch_initcall(stk5_ad1938_init);
static int stk5_spi_chipselect[] = { MXC_SPI_CS(0), };
static struct pad_desc stk5_cspi1_pads[] = { MX25_PAD_CSPI1_MOSI__CSPI1_MOSI, MX25_PAD_CSPI1_MISO__CSPI1_MISO, MX25_PAD_CSPI1_SS0__CSPI1_SS0, MX25_PAD_CSPI1_SS1__CSPI1_SS1, MX25_PAD_CSPI1_SCLK__CSPI1_SCLK, MX25_PAD_CSPI1_RDY__CSPI1_RDY, };
static struct spi_device ad1938_spi_chip_info = { .bits_per_word = 24, };
static struct spi_board_info stk5_spi_info[] = { { .modalias = "ad1938", .max_speed_hz = 10000000, .bus_num = 0, .chip_select = 0, .controller_data =&ad1938_spi_chip_info, .mode = SPI_MODE_0, }, };
static struct spi_imx_master stk5_spi1_data = { .chipselect = stk5_spi_chipselect, .num_chipselect = ARRAY_SIZE(stk5_spi_chipselect), };
static int __init stk5_spi_register(void) { int ret;
ret = mxc_iomux_v3_setup_multiple_pads(stk5_cspi1_pads, ARRAY_SIZE(stk5_cspi1_pads)); if (ret) { printk(KERN_ERR "Failed to configure CSPI1 pads\n"); return ret; } ret = spi_register_board_info(stk5_spi_info, ARRAY_SIZE(stk5_spi_info)); if (ret) { printk(KERN_ERR "%s: Failed to register SPI board_info: %d\n", __FUNCTION__, ret); goto err; } ret = mxc_register_device(&mxc_spi_device0,&stk5_spi1_data); DBG(0, "%s: mxc_register_device() returned: %d\n", __FUNCTION__, ret); return 0;
err: mxc_iomux_v3_release_multiple_pads(stk5_cspi1_pads, ARRAY_SIZE(stk5_cspi1_pads)); return ret; } device_initcall(stk5_spi_register);
And the following functino to write to the CODEC Registers:
static int ad1938_write_reg(struct snd_soc_codec *codec, unsigned int reg, unsigned int value) { u8 *reg_cache = codec->reg_cache; int ret = 0;
if (value != reg_cache[reg]) { uint8_t buf[AD1938_SPI_BUFLEN]; struct spi_transfer t = { .tx_buf = buf, .len = AD1938_SPI_BUFLEN, .bits_per_word = 24, .cs_change = 0, }; struct spi_message m;
buf[2] = AD1938_SPI_ADDR<< 1; buf[1] = reg; buf[0] = value; spi_message_init(&m); spi_message_add_tail(&t,&m); m.is_dma_mapped =0; printk(KERN_ERR "SPI-WRITE->Reg= %x, value=%x\n",reg,buf[2]); ret = spi_sync(codec->control_data,&m); printk(KERN_ERR "SPI-WRITE->Return %i\n",ret); if (ret == 0) reg_cache[reg] = value; }
return ret; }
BR, Sven Zeisberg
Hello Sven,
On Mon, Aug 16, 2010 at 06:51:17AM +0200, Sven Zeisberg wrote:
Hello,
we're working on an ALSA driver for AD1938 for i.MX25 based system. On the I²S the CODEC is Master. On the SPI, the MCU is Master.
SSI seems to work (when we set the CODEC as Master by Hardware).
We have problems to get the communication via SPI working. The CODEC requires 24Bit words and we can set SPI according to this in the board-file and verify this also with a logic analyzer. However, we can send only one word to the CODEC! This first word is transferred correctly, but all subsequent transfers show no activity on the SPI lines. We do not get any error messages from the SPI drivers! All SPI writes after the first word seem to be executed in software but show not effect in hardware. All reads return 0xff.
This is probaly more a problem in the SPI driver than alsa related. The i.MX SPI unit comes in many different variants and there may well be a bug in the i.MX25 path. As a test you could configure the SPI pads in gpio mode and use the bitbang gpio spi driver (drivers/spi/spi_gpio.c). When this works you can hunt down the bug in the SPI driver.
Sascha
Thank you, Sascha, for helping!
You're probably right - there is actually no "i.MX25" path in the SPI driver! Since I'm on a congress for the rest of the week, a colleague of mine will takeover and return with the results of the test you suggested.
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Am 16.08.2010 09:30, schrieb Sascha Hauer:
Hello Sven,
On Mon, Aug 16, 2010 at 06:51:17AM +0200, Sven Zeisberg wrote:
Hello,
we're working on an ALSA driver for AD1938 for i.MX25 based system. On the I²S the CODEC is Master. On the SPI, the MCU is Master.
SSI seems to work (when we set the CODEC as Master by Hardware).
We have problems to get the communication via SPI working. The CODEC requires 24Bit words and we can set SPI according to this in the board-file and verify this also with a logic analyzer. However, we can send only one word to the CODEC! This first word is transferred correctly, but all subsequent transfers show no activity on the SPI lines. We do not get any error messages from the SPI drivers! All SPI writes after the first word seem to be executed in software but show not effect in hardware. All reads return 0xff.
This is probaly more a problem in the SPI driver than alsa related. The i.MX SPI unit comes in many different variants and there may well be a bug in the i.MX25 path. As a test you could configure the SPI pads in gpio mode and use the bitbang gpio spi driver (drivers/spi/spi_gpio.c). When this works you can hunt down the bug in the SPI driver.
Sascha
Please do not top post.
On Mon, Aug 16, 2010 at 10:39:40AM +0200, Sven Zeisberg wrote:
Thank you, Sascha, for helping!
You're probably right - there is actually no "i.MX25" path in the SPI driver!
Yes, there is. See this block in the probe function:
if (cpu_is_mx25() || cpu_is_mx31() || cpu_is_mx35()) { spi_imx->intctrl = mx31_intctrl; spi_imx->config = mx31_config; spi_imx->trigger = mx31_trigger; spi_imx->rx_available = mx31_rx_available; } else if (cpu_is_mx27() || cpu_is_mx21()) { spi_imx->intctrl = mx27_intctrl; spi_imx->config = mx27_config; spi_imx->trigger = mx27_trigger; spi_imx->rx_available = mx27_rx_available; } else if (cpu_is_mx1()) { spi_imx->intctrl = mx1_intctrl; spi_imx->config = mx1_config; spi_imx->trigger = mx1_trigger; spi_imx->rx_available = mx1_rx_available; } else BUG();
Sascha
Thanks Sascha for your Informations. The Problem was solved by adding soc-cache.c and changing the KARO-SPI driver with them from Mainline.
The codec is still running, but now we have another problem. The AD1938 has 8 channels, the driver for i.mx25 supports 2 channels. How we can solve the Problem?
static int imx_ad1938_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai_link *machine = rtd->dai; struct snd_soc_dai *cpu_dai = machine->cpu_dai; struct snd_soc_dai *codec_dai = machine->codec_dai; struct imx_ssi *ssi_mode = cpu_dai->private_data; unsigned int channels = params_channels(params); u32 dai_format;
int ret;
ssi_mode->sync_mode = 1; if (channels == 1) ssi_mode->network_mode = 0; else ssi_mode->network_mode = 1;
dai_format = SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_IF | SND_SOC_DAIFMT_CBM_CFM;
/* set codec DAI configuration */ ret = snd_soc_dai_set_fmt(codec_dai, dai_format); if (ret) { pr_err("%s: failed set codec dai format\n", __func__); return ret; }
/* set codec DAI slots, 8 channels, all channels are enabled */ ret = snd_soc_dai_set_tdm_slot(codec_dai, 0xFF, 0xFF, 8, 32); if (ret) { pr_err("%s: failed set codec dai tdm slot\n", __func__); return ret; }
BR Murat Sahin Zeisberg GmbH
participants (3)
-
Murat Sahin
-
Sascha Hauer
-
Sven Zeisberg