[alsa-devel] [PATCH v2] drm: bridge/dw_hdmi: add audio sample channel status setting
From: Yakir Yang ykk@rock-chips.com
When transmitting IEC60985 linear PCM audio, we configure the Aduio Sample Channel Status information of all the channel status bits in the IEC60958 frame. Refer to 60958-3 page 10 for frequency, original frequency, and wordlength setting.
This fix the issue that audio does not come out on some monitors (e.g. LG 22CV241)
Note that these registers are only for interfaces: I2S audio interface, General Purpose Audio (GPA), or AHB audio DMA (AHBAUDDMA). For S/PDIF interface this information comes from the stream.
Currently this function dw_hdmi_set_channel_status is only called from dw-hdmi-i2s-audio in I2S setup.
Signed-off-by: Yakir Yang ykk@rock-chips.com Signed-off-by: Cheng-Yi Chiang cychiang@chromium.org --- Original patch by Yakir Yang is at
https://lore.kernel.org/patchwork/patch/539653/
Change from v1 to v2: 1. Remove the version check because this will only be called by dw-hdmi-i2s-audio, and the registers are available in I2S setup. 2. Set these registers in dw_hdmi_i2s_hw_params. 3. Fix the sample width setting so it can use 16 or 24 bits.
.../drm/bridge/synopsys/dw-hdmi-i2s-audio.c | 1 + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 70 +++++++++++++++++++ drivers/gpu/drm/bridge/synopsys/dw-hdmi.h | 20 ++++++ include/drm/bridge/dw_hdmi.h | 2 + 4 files changed, 93 insertions(+)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c index 34d8e837555f..b801a28b0f17 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c @@ -102,6 +102,7 @@ static int dw_hdmi_i2s_hw_params(struct device *dev, void *data, }
dw_hdmi_set_sample_rate(hdmi, hparms->sample_rate); + dw_hdmi_set_channel_status(hdmi, hparms->sample_width); dw_hdmi_set_channel_count(hdmi, hparms->channels); dw_hdmi_set_channel_allocation(hdmi, hparms->cea.channel_allocation);
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c index bd65d0479683..d1daa369c8ae 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -582,6 +582,76 @@ static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk) return n; }
+/* + * When transmitting IEC60958 linear PCM audio, these registers allow to + * configure the channel status information of all the channel status + * bits in the IEC60958 frame. For the moment this configuration is only + * used when the I2S audio interface, General Purpose Audio (GPA), + * or AHB audio DMA (AHBAUDDMA) interface is active + * (for S/PDIF interface this information comes from the stream). + */ +void dw_hdmi_set_channel_status(struct dw_hdmi *hdmi, + unsigned int sample_width) +{ + u8 aud_schnl_samplerate; + u8 aud_schnl_8; + u8 word_length_bits; + + switch (hdmi->sample_rate) { + case 32000: + aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_32K; + break; + case 44100: + aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_44K1; + break; + case 48000: + aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_48K; + break; + case 88200: + aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_88K2; + break; + case 96000: + aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_96K; + break; + case 176400: + aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_176K4; + break; + case 192000: + aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_192K; + break; + case 768000: + aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_768K; + break; + default: + dev_warn(hdmi->dev, "Unsupported audio sample rate (%u)\n", + hdmi->sample_rate); + return; + } + + /* set channel status register */ + hdmi_modb(hdmi, aud_schnl_samplerate, HDMI_FC_AUDSCHNLS7_SMPRATE_MASK, + HDMI_FC_AUDSCHNLS7); + + /* + * Set original frequency to be the same as frequency. + * Use one-complement value as stated in IEC60958-3 page 13. + */ + aud_schnl_8 = (~aud_schnl_samplerate) << + HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_OFFSET; + + /* + * Refer to IEC60958-3 page 12. We can accept 16 bits or 24 bits. + * Otherwise, set the register to 0t o indicate using default value. + */ + word_length_bits = (sample_width == 16) ? 0x2 : + ((sample_width == 24) ? 0xb : 0); + + aud_schnl_8 |= word_length_bits << HDMI_FC_AUDSCHNLS8_WORDLEGNTH_OFFSET; + + hdmi_writeb(hdmi, aud_schnl_8, HDMI_FC_AUDSCHNLS8); +} +EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_status); + static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi, unsigned long pixel_clk, unsigned int sample_rate) { diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h index 6988f12d89d9..619ebc1c8354 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h @@ -158,6 +158,17 @@ #define HDMI_FC_SPDDEVICEINF 0x1062 #define HDMI_FC_AUDSCONF 0x1063 #define HDMI_FC_AUDSSTAT 0x1064 +#define HDMI_FC_AUDSV 0x1065 +#define HDMI_FC_AUDSU 0x1066 +#define HDMI_FC_AUDSCHNLS0 0x1067 +#define HDMI_FC_AUDSCHNLS1 0x1068 +#define HDMI_FC_AUDSCHNLS2 0x1069 +#define HDMI_FC_AUDSCHNLS3 0x106a +#define HDMI_FC_AUDSCHNLS4 0x106b +#define HDMI_FC_AUDSCHNLS5 0x106c +#define HDMI_FC_AUDSCHNLS6 0x106d +#define HDMI_FC_AUDSCHNLS7 0x106e +#define HDMI_FC_AUDSCHNLS8 0x106f #define HDMI_FC_DATACH0FILL 0x1070 #define HDMI_FC_DATACH1FILL 0x1071 #define HDMI_FC_DATACH2FILL 0x1072 @@ -706,6 +717,15 @@ enum { /* HDMI_FC_AUDSCHNLS7 field values */ HDMI_FC_AUDSCHNLS7_ACCURACY_OFFSET = 4, HDMI_FC_AUDSCHNLS7_ACCURACY_MASK = 0x30, + HDMI_FC_AUDSCHNLS7_SMPRATE_MASK = 0x0f, + HDMI_FC_AUDSCHNLS7_SMPRATE_192K = 0xe, + HDMI_FC_AUDSCHNLS7_SMPRATE_176K4 = 0xc, + HDMI_FC_AUDSCHNLS7_SMPRATE_96K = 0xa, + HDMI_FC_AUDSCHNLS7_SMPRATE_768K = 0x9, + HDMI_FC_AUDSCHNLS7_SMPRATE_88K2 = 0x8, + HDMI_FC_AUDSCHNLS7_SMPRATE_32K = 0x3, + HDMI_FC_AUDSCHNLS7_SMPRATE_48K = 0x2, + HDMI_FC_AUDSCHNLS7_SMPRATE_44K1 = 0x0,
/* HDMI_FC_AUDSCHNLS8 field values */ HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_MASK = 0xf0, diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h index cf528c289857..12144d2f80f4 100644 --- a/include/drm/bridge/dw_hdmi.h +++ b/include/drm/bridge/dw_hdmi.h @@ -156,6 +156,8 @@ void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense);
void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate); void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt); +void dw_hdmi_set_channel_status(struct dw_hdmi *hdmi, + unsigned int sample_width); void dw_hdmi_set_channel_allocation(struct dw_hdmi *hdmi, unsigned int ca); void dw_hdmi_audio_enable(struct dw_hdmi *hdmi); void dw_hdmi_audio_disable(struct dw_hdmi *hdmi);
Sorry for the noise. Removed original author ykk@rock-chips.com from the thread because that mail is obsolete. Yakir is now using kuankuan.y@gmail.com.
On Thu, Sep 5, 2019 at 5:43 PM Cheng-Yi Chiang cychiang@chromium.org wrote:
From: Yakir Yang ykk@rock-chips.com
When transmitting IEC60985 linear PCM audio, we configure the Aduio Sample Channel Status information of all the channel status bits in the IEC60958 frame. Refer to 60958-3 page 10 for frequency, original frequency, and wordlength setting.
This fix the issue that audio does not come out on some monitors (e.g. LG 22CV241)
Note that these registers are only for interfaces: I2S audio interface, General Purpose Audio (GPA), or AHB audio DMA (AHBAUDDMA). For S/PDIF interface this information comes from the stream.
Currently this function dw_hdmi_set_channel_status is only called from dw-hdmi-i2s-audio in I2S setup.
Signed-off-by: Yakir Yang ykk@rock-chips.com Signed-off-by: Cheng-Yi Chiang cychiang@chromium.org
Original patch by Yakir Yang is at
https://lore.kernel.org/patchwork/patch/539653/
Change from v1 to v2:
- Remove the version check because this will only be called by dw-hdmi-i2s-audio, and the registers are available in I2S setup.
- Set these registers in dw_hdmi_i2s_hw_params.
- Fix the sample width setting so it can use 16 or 24 bits.
.../drm/bridge/synopsys/dw-hdmi-i2s-audio.c | 1 + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 70 +++++++++++++++++++ drivers/gpu/drm/bridge/synopsys/dw-hdmi.h | 20 ++++++ include/drm/bridge/dw_hdmi.h | 2 + 4 files changed, 93 insertions(+)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c index 34d8e837555f..b801a28b0f17 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c @@ -102,6 +102,7 @@ static int dw_hdmi_i2s_hw_params(struct device *dev, void *data, }
dw_hdmi_set_sample_rate(hdmi, hparms->sample_rate);
dw_hdmi_set_channel_status(hdmi, hparms->sample_width); dw_hdmi_set_channel_count(hdmi, hparms->channels); dw_hdmi_set_channel_allocation(hdmi, hparms->cea.channel_allocation);diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c index bd65d0479683..d1daa369c8ae 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -582,6 +582,76 @@ static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk) return n; }
+/*
- When transmitting IEC60958 linear PCM audio, these registers allow to
- configure the channel status information of all the channel status
- bits in the IEC60958 frame. For the moment this configuration is only
- used when the I2S audio interface, General Purpose Audio (GPA),
- or AHB audio DMA (AHBAUDDMA) interface is active
- (for S/PDIF interface this information comes from the stream).
- */
+void dw_hdmi_set_channel_status(struct dw_hdmi *hdmi,
unsigned int sample_width)+{
u8 aud_schnl_samplerate;u8 aud_schnl_8;u8 word_length_bits;switch (hdmi->sample_rate) {case 32000:aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_32K;break;case 44100:aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_44K1;break;case 48000:aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_48K;break;case 88200:aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_88K2;break;case 96000:aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_96K;break;case 176400:aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_176K4;break;case 192000:aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_192K;break;case 768000:aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_768K;break;default:dev_warn(hdmi->dev, "Unsupported audio sample rate (%u)\n",hdmi->sample_rate);return;}/* set channel status register */hdmi_modb(hdmi, aud_schnl_samplerate, HDMI_FC_AUDSCHNLS7_SMPRATE_MASK,HDMI_FC_AUDSCHNLS7);/** Set original frequency to be the same as frequency.* Use one-complement value as stated in IEC60958-3 page 13.*/aud_schnl_8 = (~aud_schnl_samplerate) <<HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_OFFSET;/** Refer to IEC60958-3 page 12. We can accept 16 bits or 24 bits.* Otherwise, set the register to 0t o indicate using default value.*/word_length_bits = (sample_width == 16) ? 0x2 :((sample_width == 24) ? 0xb : 0);aud_schnl_8 |= word_length_bits << HDMI_FC_AUDSCHNLS8_WORDLEGNTH_OFFSET;hdmi_writeb(hdmi, aud_schnl_8, HDMI_FC_AUDSCHNLS8);+} +EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_status);
static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi, unsigned long pixel_clk, unsigned int sample_rate) { diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h index 6988f12d89d9..619ebc1c8354 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h @@ -158,6 +158,17 @@ #define HDMI_FC_SPDDEVICEINF 0x1062 #define HDMI_FC_AUDSCONF 0x1063 #define HDMI_FC_AUDSSTAT 0x1064 +#define HDMI_FC_AUDSV 0x1065 +#define HDMI_FC_AUDSU 0x1066 +#define HDMI_FC_AUDSCHNLS0 0x1067 +#define HDMI_FC_AUDSCHNLS1 0x1068 +#define HDMI_FC_AUDSCHNLS2 0x1069 +#define HDMI_FC_AUDSCHNLS3 0x106a +#define HDMI_FC_AUDSCHNLS4 0x106b +#define HDMI_FC_AUDSCHNLS5 0x106c +#define HDMI_FC_AUDSCHNLS6 0x106d +#define HDMI_FC_AUDSCHNLS7 0x106e +#define HDMI_FC_AUDSCHNLS8 0x106f #define HDMI_FC_DATACH0FILL 0x1070 #define HDMI_FC_DATACH1FILL 0x1071 #define HDMI_FC_DATACH2FILL 0x1072 @@ -706,6 +717,15 @@ enum { /* HDMI_FC_AUDSCHNLS7 field values */ HDMI_FC_AUDSCHNLS7_ACCURACY_OFFSET = 4, HDMI_FC_AUDSCHNLS7_ACCURACY_MASK = 0x30,
HDMI_FC_AUDSCHNLS7_SMPRATE_MASK = 0x0f,HDMI_FC_AUDSCHNLS7_SMPRATE_192K = 0xe,HDMI_FC_AUDSCHNLS7_SMPRATE_176K4 = 0xc,HDMI_FC_AUDSCHNLS7_SMPRATE_96K = 0xa,HDMI_FC_AUDSCHNLS7_SMPRATE_768K = 0x9,HDMI_FC_AUDSCHNLS7_SMPRATE_88K2 = 0x8,HDMI_FC_AUDSCHNLS7_SMPRATE_32K = 0x3,HDMI_FC_AUDSCHNLS7_SMPRATE_48K = 0x2,HDMI_FC_AUDSCHNLS7_SMPRATE_44K1 = 0x0,/* HDMI_FC_AUDSCHNLS8 field values */ HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_MASK = 0xf0, diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h index cf528c289857..12144d2f80f4 100644 --- a/include/drm/bridge/dw_hdmi.h +++ b/include/drm/bridge/dw_hdmi.h @@ -156,6 +156,8 @@ void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense);
void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate); void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt); +void dw_hdmi_set_channel_status(struct dw_hdmi *hdmi,
unsigned int sample_width);void dw_hdmi_set_channel_allocation(struct dw_hdmi *hdmi, unsigned int ca); void dw_hdmi_audio_enable(struct dw_hdmi *hdmi); void dw_hdmi_audio_disable(struct dw_hdmi *hdmi); -- 2.23.0.187.g17f5b7556c-goog
Dne četrtek, 05. september 2019 ob 11:43:25 CEST je Cheng-Yi Chiang napisal(a):
From: Yakir Yang ykk@rock-chips.com
When transmitting IEC60985 linear PCM audio, we configure the Aduio Sample Channel Status information of all the channel status bits in the IEC60958 frame. Refer to 60958-3 page 10 for frequency, original frequency, and wordlength setting.
This fix the issue that audio does not come out on some monitors (e.g. LG 22CV241)
Note that these registers are only for interfaces: I2S audio interface, General Purpose Audio (GPA), or AHB audio DMA (AHBAUDDMA). For S/PDIF interface this information comes from the stream.
Currently this function dw_hdmi_set_channel_status is only called from dw-hdmi-i2s-audio in I2S setup.
Signed-off-by: Yakir Yang ykk@rock-chips.com Signed-off-by: Cheng-Yi Chiang cychiang@chromium.org
Original patch by Yakir Yang is at
https://lore.kernel.org/patchwork/patch/539653/
Change from v1 to v2:
- Remove the version check because this will only be called by dw-hdmi-i2s-audio, and the registers are available in I2S setup.
- Set these registers in dw_hdmi_i2s_hw_params.
- Fix the sample width setting so it can use 16 or 24 bits.
.../drm/bridge/synopsys/dw-hdmi-i2s-audio.c | 1 + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 70 +++++++++++++++++++ drivers/gpu/drm/bridge/synopsys/dw-hdmi.h | 20 ++++++ include/drm/bridge/dw_hdmi.h | 2 + 4 files changed, 93 insertions(+)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c index 34d8e837555f..b801a28b0f17 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c @@ -102,6 +102,7 @@ static int dw_hdmi_i2s_hw_params(struct device *dev, void *data, }
dw_hdmi_set_sample_rate(hdmi, hparms->sample_rate);
- dw_hdmi_set_channel_status(hdmi, hparms->sample_width); dw_hdmi_set_channel_count(hdmi, hparms->channels); dw_hdmi_set_channel_allocation(hdmi, hparms-
cea.channel_allocation);
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c index bd65d0479683..d1daa369c8ae 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -582,6 +582,76 @@ static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk) return n; }
+/*
- When transmitting IEC60958 linear PCM audio, these registers allow to
- configure the channel status information of all the channel status
- bits in the IEC60958 frame. For the moment this configuration is only
- used when the I2S audio interface, General Purpose Audio (GPA),
- or AHB audio DMA (AHBAUDDMA) interface is active
- (for S/PDIF interface this information comes from the stream).
- */
+void dw_hdmi_set_channel_status(struct dw_hdmi *hdmi,
unsigned int sample_width)+{
- u8 aud_schnl_samplerate;
- u8 aud_schnl_8;
- u8 word_length_bits;
- switch (hdmi->sample_rate) {
- case 32000:
aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_32K;break;- case 44100:
aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_44K1;break;- case 48000:
aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_48K;break;- case 88200:
aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_88K2;break;- case 96000:
aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_96K;break;- case 176400:
aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_176K4;break;- case 192000:
aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_192K;break;- case 768000:
aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_768K;break;- default:
dev_warn(hdmi->dev, "Unsupported audio sample rate (%u)
\n",
hdmi->sample_rate);return;- }
- /* set channel status register */
- hdmi_modb(hdmi, aud_schnl_samplerate,
HDMI_FC_AUDSCHNLS7_SMPRATE_MASK,
HDMI_FC_AUDSCHNLS7);- /*
* Set original frequency to be the same as frequency.* Use one-complement value as stated in IEC60958-3 page 13.*/- aud_schnl_8 = (~aud_schnl_samplerate) <<
HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_OFFSET;- /*
* Refer to IEC60958-3 page 12. We can accept 16 bits or 24 bits.* Otherwise, set the register to 0t o indicate using default
value.
Nit: "0t 0" -> "0 to"
With that fixed, this patch is: Reviewed-by: Jernej Skrabec jernej.skrabec@siol.net
Best regards, Jernej
*/- word_length_bits = (sample_width == 16) ? 0x2 :
((sample_width == 24) ? 0xb : 0);- aud_schnl_8 |= word_length_bits <<
HDMI_FC_AUDSCHNLS8_WORDLEGNTH_OFFSET;
- hdmi_writeb(hdmi, aud_schnl_8, HDMI_FC_AUDSCHNLS8);
+} +EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_status);
static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi, unsigned long pixel_clk, unsigned int sample_rate) { diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h index 6988f12d89d9..619ebc1c8354 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h @@ -158,6 +158,17 @@ #define HDMI_FC_SPDDEVICEINF 0x1062 #define HDMI_FC_AUDSCONF 0x1063 #define HDMI_FC_AUDSSTAT 0x1064 +#define HDMI_FC_AUDSV 0x1065 +#define HDMI_FC_AUDSU 0x1066 +#define HDMI_FC_AUDSCHNLS0 0x1067 +#define HDMI_FC_AUDSCHNLS1 0x1068 +#define HDMI_FC_AUDSCHNLS2 0x1069 +#define HDMI_FC_AUDSCHNLS3 0x106a +#define HDMI_FC_AUDSCHNLS4 0x106b +#define HDMI_FC_AUDSCHNLS5 0x106c +#define HDMI_FC_AUDSCHNLS6 0x106d +#define HDMI_FC_AUDSCHNLS7 0x106e +#define HDMI_FC_AUDSCHNLS8 0x106f #define HDMI_FC_DATACH0FILL 0x1070 #define HDMI_FC_DATACH1FILL 0x1071 #define HDMI_FC_DATACH2FILL 0x1072 @@ -706,6 +717,15 @@ enum { /* HDMI_FC_AUDSCHNLS7 field values */ HDMI_FC_AUDSCHNLS7_ACCURACY_OFFSET = 4, HDMI_FC_AUDSCHNLS7_ACCURACY_MASK = 0x30,
- HDMI_FC_AUDSCHNLS7_SMPRATE_MASK = 0x0f,
- HDMI_FC_AUDSCHNLS7_SMPRATE_192K = 0xe,
- HDMI_FC_AUDSCHNLS7_SMPRATE_176K4 = 0xc,
- HDMI_FC_AUDSCHNLS7_SMPRATE_96K = 0xa,
- HDMI_FC_AUDSCHNLS7_SMPRATE_768K = 0x9,
- HDMI_FC_AUDSCHNLS7_SMPRATE_88K2 = 0x8,
- HDMI_FC_AUDSCHNLS7_SMPRATE_32K = 0x3,
- HDMI_FC_AUDSCHNLS7_SMPRATE_48K = 0x2,
- HDMI_FC_AUDSCHNLS7_SMPRATE_44K1 = 0x0,
/* HDMI_FC_AUDSCHNLS8 field values */ HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_MASK = 0xf0, diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h index cf528c289857..12144d2f80f4 100644 --- a/include/drm/bridge/dw_hdmi.h +++ b/include/drm/bridge/dw_hdmi.h @@ -156,6 +156,8 @@ void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense);
void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate); void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt); +void dw_hdmi_set_channel_status(struct dw_hdmi *hdmi,
unsigned int sample_width);void dw_hdmi_set_channel_allocation(struct dw_hdmi *hdmi, unsigned int ca); void dw_hdmi_audio_enable(struct dw_hdmi *hdmi); void dw_hdmi_audio_disable(struct dw_hdmi *hdmi);
On Mon, Sep 9, 2019 at 2:18 AM Jernej Škrabec jernej.skrabec@siol.net wrote:
Dne četrtek, 05. september 2019 ob 11:43:25 CEST je Cheng-Yi Chiang napisal(a):
From: Yakir Yang ykk@rock-chips.com
When transmitting IEC60985 linear PCM audio, we configure the Aduio Sample Channel Status information of all the channel status bits in the IEC60958 frame. Refer to 60958-3 page 10 for frequency, original frequency, and wordlength setting.
This fix the issue that audio does not come out on some monitors (e.g. LG 22CV241)
Note that these registers are only for interfaces: I2S audio interface, General Purpose Audio (GPA), or AHB audio DMA (AHBAUDDMA). For S/PDIF interface this information comes from the stream.
Currently this function dw_hdmi_set_channel_status is only called from dw-hdmi-i2s-audio in I2S setup.
Signed-off-by: Yakir Yang ykk@rock-chips.com Signed-off-by: Cheng-Yi Chiang cychiang@chromium.org
Original patch by Yakir Yang is at
https://lore.kernel.org/patchwork/patch/539653/
Change from v1 to v2:
- Remove the version check because this will only be called by dw-hdmi-i2s-audio, and the registers are available in I2S setup.
- Set these registers in dw_hdmi_i2s_hw_params.
- Fix the sample width setting so it can use 16 or 24 bits.
.../drm/bridge/synopsys/dw-hdmi-i2s-audio.c | 1 + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 70 +++++++++++++++++++ drivers/gpu/drm/bridge/synopsys/dw-hdmi.h | 20 ++++++ include/drm/bridge/dw_hdmi.h | 2 + 4 files changed, 93 insertions(+)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c index 34d8e837555f..b801a28b0f17 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c @@ -102,6 +102,7 @@ static int dw_hdmi_i2s_hw_params(struct device *dev, void *data, }
dw_hdmi_set_sample_rate(hdmi, hparms->sample_rate);
dw_hdmi_set_channel_status(hdmi, hparms->sample_width); dw_hdmi_set_channel_count(hdmi, hparms->channels); dw_hdmi_set_channel_allocation(hdmi, hparms-cea.channel_allocation);
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c index bd65d0479683..d1daa369c8ae 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -582,6 +582,76 @@ static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk) return n; }
+/*
- When transmitting IEC60958 linear PCM audio, these registers allow to
- configure the channel status information of all the channel status
- bits in the IEC60958 frame. For the moment this configuration is only
- used when the I2S audio interface, General Purpose Audio (GPA),
- or AHB audio DMA (AHBAUDDMA) interface is active
- (for S/PDIF interface this information comes from the stream).
- */
+void dw_hdmi_set_channel_status(struct dw_hdmi *hdmi,
unsigned int sample_width)+{
u8 aud_schnl_samplerate;u8 aud_schnl_8;u8 word_length_bits;switch (hdmi->sample_rate) {case 32000:aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_32K;break;case 44100:aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_44K1;break;case 48000:aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_48K;break;case 88200:aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_88K2;break;case 96000:aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_96K;break;case 176400:aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_176K4;break;case 192000:aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_192K;break;case 768000:aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_768K;break;default:dev_warn(hdmi->dev, "Unsupported audio sample rate (%u)\n",
hdmi->sample_rate);return;}/* set channel status register */hdmi_modb(hdmi, aud_schnl_samplerate,HDMI_FC_AUDSCHNLS7_SMPRATE_MASK,
HDMI_FC_AUDSCHNLS7);/** Set original frequency to be the same as frequency.* Use one-complement value as stated in IEC60958-3 page 13.*/aud_schnl_8 = (~aud_schnl_samplerate) <<HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_OFFSET;/** Refer to IEC60958-3 page 12. We can accept 16 bits or 24 bits.* Otherwise, set the register to 0t o indicate using defaultvalue.
Nit: "0t 0" -> "0 to"
With that fixed, this patch is: Reviewed-by: Jernej Skrabec jernej.skrabec@siol.net
Best regards, Jernej
Hi Jernej, Thank you for reviewing the patch. But as Russell pointed in the next mail, I will update in v3 to make this patch much more simpler.
*/word_length_bits = (sample_width == 16) ? 0x2 :((sample_width == 24) ? 0xb : 0);aud_schnl_8 |= word_length_bits <<HDMI_FC_AUDSCHNLS8_WORDLEGNTH_OFFSET;
hdmi_writeb(hdmi, aud_schnl_8, HDMI_FC_AUDSCHNLS8);+} +EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_status);
static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi, unsigned long pixel_clk, unsigned int sample_rate) { diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h index 6988f12d89d9..619ebc1c8354 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h @@ -158,6 +158,17 @@ #define HDMI_FC_SPDDEVICEINF 0x1062 #define HDMI_FC_AUDSCONF 0x1063 #define HDMI_FC_AUDSSTAT 0x1064 +#define HDMI_FC_AUDSV 0x1065 +#define HDMI_FC_AUDSU 0x1066 +#define HDMI_FC_AUDSCHNLS0 0x1067 +#define HDMI_FC_AUDSCHNLS1 0x1068 +#define HDMI_FC_AUDSCHNLS2 0x1069 +#define HDMI_FC_AUDSCHNLS3 0x106a +#define HDMI_FC_AUDSCHNLS4 0x106b +#define HDMI_FC_AUDSCHNLS5 0x106c +#define HDMI_FC_AUDSCHNLS6 0x106d +#define HDMI_FC_AUDSCHNLS7 0x106e +#define HDMI_FC_AUDSCHNLS8 0x106f #define HDMI_FC_DATACH0FILL 0x1070 #define HDMI_FC_DATACH1FILL 0x1071 #define HDMI_FC_DATACH2FILL 0x1072 @@ -706,6 +717,15 @@ enum { /* HDMI_FC_AUDSCHNLS7 field values */ HDMI_FC_AUDSCHNLS7_ACCURACY_OFFSET = 4, HDMI_FC_AUDSCHNLS7_ACCURACY_MASK = 0x30,
HDMI_FC_AUDSCHNLS7_SMPRATE_MASK = 0x0f,HDMI_FC_AUDSCHNLS7_SMPRATE_192K = 0xe,HDMI_FC_AUDSCHNLS7_SMPRATE_176K4 = 0xc,HDMI_FC_AUDSCHNLS7_SMPRATE_96K = 0xa,HDMI_FC_AUDSCHNLS7_SMPRATE_768K = 0x9,HDMI_FC_AUDSCHNLS7_SMPRATE_88K2 = 0x8,HDMI_FC_AUDSCHNLS7_SMPRATE_32K = 0x3,HDMI_FC_AUDSCHNLS7_SMPRATE_48K = 0x2,HDMI_FC_AUDSCHNLS7_SMPRATE_44K1 = 0x0,/* HDMI_FC_AUDSCHNLS8 field values */ HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_MASK = 0xf0, diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h index cf528c289857..12144d2f80f4 100644 --- a/include/drm/bridge/dw_hdmi.h +++ b/include/drm/bridge/dw_hdmi.h @@ -156,6 +156,8 @@ void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense);
void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate); void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt); +void dw_hdmi_set_channel_status(struct dw_hdmi *hdmi,
unsigned int sample_width);void dw_hdmi_set_channel_allocation(struct dw_hdmi *hdmi, unsigned int ca); void dw_hdmi_audio_enable(struct dw_hdmi *hdmi); void dw_hdmi_audio_disable(struct dw_hdmi *hdmi);
On Thu, Sep 05, 2019 at 05:43:25PM +0800, Cheng-Yi Chiang wrote:
From: Yakir Yang ykk@rock-chips.com
When transmitting IEC60985 linear PCM audio, we configure the Aduio Sample Channel Status information of all the channel status bits in the IEC60958 frame. Refer to 60958-3 page 10 for frequency, original frequency, and wordlength setting.
This fix the issue that audio does not come out on some monitors (e.g. LG 22CV241)
Note that these registers are only for interfaces: I2S audio interface, General Purpose Audio (GPA), or AHB audio DMA (AHBAUDDMA). For S/PDIF interface this information comes from the stream.
Currently this function dw_hdmi_set_channel_status is only called from dw-hdmi-i2s-audio in I2S setup.
Signed-off-by: Yakir Yang ykk@rock-chips.com Signed-off-by: Cheng-Yi Chiang cychiang@chromium.org
Original patch by Yakir Yang is at
https://lore.kernel.org/patchwork/patch/539653/
Change from v1 to v2:
- Remove the version check because this will only be called by dw-hdmi-i2s-audio, and the registers are available in I2S setup.
- Set these registers in dw_hdmi_i2s_hw_params.
- Fix the sample width setting so it can use 16 or 24 bits.
.../drm/bridge/synopsys/dw-hdmi-i2s-audio.c | 1 + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 70 +++++++++++++++++++ drivers/gpu/drm/bridge/synopsys/dw-hdmi.h | 20 ++++++ include/drm/bridge/dw_hdmi.h | 2 + 4 files changed, 93 insertions(+)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c index 34d8e837555f..b801a28b0f17 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c @@ -102,6 +102,7 @@ static int dw_hdmi_i2s_hw_params(struct device *dev, void *data, }
dw_hdmi_set_sample_rate(hdmi, hparms->sample_rate);
- dw_hdmi_set_channel_status(hdmi, hparms->sample_width); dw_hdmi_set_channel_count(hdmi, hparms->channels); dw_hdmi_set_channel_allocation(hdmi, hparms->cea.channel_allocation);
dw_hdmi_i2s_hw_params() is passed the channel status data in hparams->iec.status Rather than re-creating it afresh in the driver, I'd recommend programming the already supplied channel status data into the registers.
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c index bd65d0479683..d1daa369c8ae 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -582,6 +582,76 @@ static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk) return n; }
+/*
- When transmitting IEC60958 linear PCM audio, these registers allow to
- configure the channel status information of all the channel status
- bits in the IEC60958 frame. For the moment this configuration is only
- used when the I2S audio interface, General Purpose Audio (GPA),
- or AHB audio DMA (AHBAUDDMA) interface is active
- (for S/PDIF interface this information comes from the stream).
- */
+void dw_hdmi_set_channel_status(struct dw_hdmi *hdmi,
unsigned int sample_width)+{
- u8 aud_schnl_samplerate;
- u8 aud_schnl_8;
- u8 word_length_bits;
- switch (hdmi->sample_rate) {
- case 32000:
aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_32K;break;- case 44100:
aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_44K1;break;- case 48000:
aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_48K;break;- case 88200:
aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_88K2;break;- case 96000:
aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_96K;break;- case 176400:
aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_176K4;break;- case 192000:
aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_192K;break;- case 768000:
aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_768K;break;- default:
dev_warn(hdmi->dev, "Unsupported audio sample rate (%u)\n",hdmi->sample_rate);return;- }
- /* set channel status register */
- hdmi_modb(hdmi, aud_schnl_samplerate, HDMI_FC_AUDSCHNLS7_SMPRATE_MASK,
HDMI_FC_AUDSCHNLS7);- /*
* Set original frequency to be the same as frequency.* Use one-complement value as stated in IEC60958-3 page 13.*/- aud_schnl_8 = (~aud_schnl_samplerate) <<
HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_OFFSET;- /*
* Refer to IEC60958-3 page 12. We can accept 16 bits or 24 bits.* Otherwise, set the register to 0t o indicate using default value.*/- word_length_bits = (sample_width == 16) ? 0x2 :
((sample_width == 24) ? 0xb : 0);- aud_schnl_8 |= word_length_bits << HDMI_FC_AUDSCHNLS8_WORDLEGNTH_OFFSET;
- hdmi_writeb(hdmi, aud_schnl_8, HDMI_FC_AUDSCHNLS8);
+} +EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_status);
As mentioned above, the channel status data is actually already provided - so we don't really need the above at all. It just needs the data programmed into the registers.
static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi, unsigned long pixel_clk, unsigned int sample_rate) { diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h index 6988f12d89d9..619ebc1c8354 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h @@ -158,6 +158,17 @@ #define HDMI_FC_SPDDEVICEINF 0x1062 #define HDMI_FC_AUDSCONF 0x1063 #define HDMI_FC_AUDSSTAT 0x1064 +#define HDMI_FC_AUDSV 0x1065 +#define HDMI_FC_AUDSU 0x1066 +#define HDMI_FC_AUDSCHNLS0 0x1067 +#define HDMI_FC_AUDSCHNLS1 0x1068 +#define HDMI_FC_AUDSCHNLS2 0x1069 +#define HDMI_FC_AUDSCHNLS3 0x106a +#define HDMI_FC_AUDSCHNLS4 0x106b +#define HDMI_FC_AUDSCHNLS5 0x106c +#define HDMI_FC_AUDSCHNLS6 0x106d +#define HDMI_FC_AUDSCHNLS7 0x106e +#define HDMI_FC_AUDSCHNLS8 0x106f #define HDMI_FC_DATACH0FILL 0x1070 #define HDMI_FC_DATACH1FILL 0x1071 #define HDMI_FC_DATACH2FILL 0x1072 @@ -706,6 +717,15 @@ enum { /* HDMI_FC_AUDSCHNLS7 field values */ HDMI_FC_AUDSCHNLS7_ACCURACY_OFFSET = 4, HDMI_FC_AUDSCHNLS7_ACCURACY_MASK = 0x30,
- HDMI_FC_AUDSCHNLS7_SMPRATE_MASK = 0x0f,
- HDMI_FC_AUDSCHNLS7_SMPRATE_192K = 0xe,
- HDMI_FC_AUDSCHNLS7_SMPRATE_176K4 = 0xc,
- HDMI_FC_AUDSCHNLS7_SMPRATE_96K = 0xa,
- HDMI_FC_AUDSCHNLS7_SMPRATE_768K = 0x9,
- HDMI_FC_AUDSCHNLS7_SMPRATE_88K2 = 0x8,
- HDMI_FC_AUDSCHNLS7_SMPRATE_32K = 0x3,
- HDMI_FC_AUDSCHNLS7_SMPRATE_48K = 0x2,
- HDMI_FC_AUDSCHNLS7_SMPRATE_44K1 = 0x0,
These look very much like the IEC958_AES* consumer definitions in include/sound/asoundef.h.
/* HDMI_FC_AUDSCHNLS8 field values */ HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_MASK = 0xf0, diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h index cf528c289857..12144d2f80f4 100644 --- a/include/drm/bridge/dw_hdmi.h +++ b/include/drm/bridge/dw_hdmi.h @@ -156,6 +156,8 @@ void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense);
void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate); void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt); +void dw_hdmi_set_channel_status(struct dw_hdmi *hdmi,
unsigned int sample_width);void dw_hdmi_set_channel_allocation(struct dw_hdmi *hdmi, unsigned int ca); void dw_hdmi_audio_enable(struct dw_hdmi *hdmi); void dw_hdmi_audio_disable(struct dw_hdmi *hdmi); -- 2.23.0.187.g17f5b7556c-goog
linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
On Mon, Sep 9, 2019 at 2:38 AM Russell King - ARM Linux admin linux@armlinux.org.uk wrote:
On Thu, Sep 05, 2019 at 05:43:25PM +0800, Cheng-Yi Chiang wrote:
From: Yakir Yang ykk@rock-chips.com
When transmitting IEC60985 linear PCM audio, we configure the Aduio Sample Channel Status information of all the channel status bits in the IEC60958 frame. Refer to 60958-3 page 10 for frequency, original frequency, and wordlength setting.
This fix the issue that audio does not come out on some monitors (e.g. LG 22CV241)
Note that these registers are only for interfaces: I2S audio interface, General Purpose Audio (GPA), or AHB audio DMA (AHBAUDDMA). For S/PDIF interface this information comes from the stream.
Currently this function dw_hdmi_set_channel_status is only called from dw-hdmi-i2s-audio in I2S setup.
Signed-off-by: Yakir Yang ykk@rock-chips.com Signed-off-by: Cheng-Yi Chiang cychiang@chromium.org
Original patch by Yakir Yang is at
https://lore.kernel.org/patchwork/patch/539653/
Change from v1 to v2:
- Remove the version check because this will only be called by dw-hdmi-i2s-audio, and the registers are available in I2S setup.
- Set these registers in dw_hdmi_i2s_hw_params.
- Fix the sample width setting so it can use 16 or 24 bits.
.../drm/bridge/synopsys/dw-hdmi-i2s-audio.c | 1 + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 70 +++++++++++++++++++ drivers/gpu/drm/bridge/synopsys/dw-hdmi.h | 20 ++++++ include/drm/bridge/dw_hdmi.h | 2 + 4 files changed, 93 insertions(+)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c index 34d8e837555f..b801a28b0f17 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c @@ -102,6 +102,7 @@ static int dw_hdmi_i2s_hw_params(struct device *dev, void *data, }
dw_hdmi_set_sample_rate(hdmi, hparms->sample_rate);
dw_hdmi_set_channel_status(hdmi, hparms->sample_width); dw_hdmi_set_channel_count(hdmi, hparms->channels); dw_hdmi_set_channel_allocation(hdmi, hparms->cea.channel_allocation);dw_hdmi_i2s_hw_params() is passed the channel status data in hparams->iec.status Rather than re-creating it afresh in the driver, I'd recommend programming the already supplied channel status data into the registers.
Hi Russell, Thank you for pointing this out. I did not realize that the status data is already set. I will fix in v3 to make this patch much simpler.
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c index bd65d0479683..d1daa369c8ae 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -582,6 +582,76 @@ static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk) return n; }
+/*
- When transmitting IEC60958 linear PCM audio, these registers allow to
- configure the channel status information of all the channel status
- bits in the IEC60958 frame. For the moment this configuration is only
- used when the I2S audio interface, General Purpose Audio (GPA),
- or AHB audio DMA (AHBAUDDMA) interface is active
- (for S/PDIF interface this information comes from the stream).
- */
+void dw_hdmi_set_channel_status(struct dw_hdmi *hdmi,
unsigned int sample_width)+{
u8 aud_schnl_samplerate;u8 aud_schnl_8;u8 word_length_bits;switch (hdmi->sample_rate) {case 32000:aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_32K;break;case 44100:aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_44K1;break;case 48000:aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_48K;break;case 88200:aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_88K2;break;case 96000:aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_96K;break;case 176400:aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_176K4;break;case 192000:aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_192K;break;case 768000:aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_768K;break;default:dev_warn(hdmi->dev, "Unsupported audio sample rate (%u)\n",hdmi->sample_rate);return;}/* set channel status register */hdmi_modb(hdmi, aud_schnl_samplerate, HDMI_FC_AUDSCHNLS7_SMPRATE_MASK,HDMI_FC_AUDSCHNLS7);/** Set original frequency to be the same as frequency.* Use one-complement value as stated in IEC60958-3 page 13.*/aud_schnl_8 = (~aud_schnl_samplerate) <<HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_OFFSET;/** Refer to IEC60958-3 page 12. We can accept 16 bits or 24 bits.* Otherwise, set the register to 0t o indicate using default value.*/word_length_bits = (sample_width == 16) ? 0x2 :((sample_width == 24) ? 0xb : 0);aud_schnl_8 |= word_length_bits << HDMI_FC_AUDSCHNLS8_WORDLEGNTH_OFFSET;hdmi_writeb(hdmi, aud_schnl_8, HDMI_FC_AUDSCHNLS8);+} +EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_status);
As mentioned above, the channel status data is actually already provided - so we don't really need the above at all. It just needs the data programmed into the registers.
ACK
static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi, unsigned long pixel_clk, unsigned int sample_rate) { diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h index 6988f12d89d9..619ebc1c8354 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h @@ -158,6 +158,17 @@ #define HDMI_FC_SPDDEVICEINF 0x1062 #define HDMI_FC_AUDSCONF 0x1063 #define HDMI_FC_AUDSSTAT 0x1064 +#define HDMI_FC_AUDSV 0x1065 +#define HDMI_FC_AUDSU 0x1066 +#define HDMI_FC_AUDSCHNLS0 0x1067 +#define HDMI_FC_AUDSCHNLS1 0x1068 +#define HDMI_FC_AUDSCHNLS2 0x1069 +#define HDMI_FC_AUDSCHNLS3 0x106a +#define HDMI_FC_AUDSCHNLS4 0x106b +#define HDMI_FC_AUDSCHNLS5 0x106c +#define HDMI_FC_AUDSCHNLS6 0x106d +#define HDMI_FC_AUDSCHNLS7 0x106e +#define HDMI_FC_AUDSCHNLS8 0x106f #define HDMI_FC_DATACH0FILL 0x1070 #define HDMI_FC_DATACH1FILL 0x1071 #define HDMI_FC_DATACH2FILL 0x1072 @@ -706,6 +717,15 @@ enum { /* HDMI_FC_AUDSCHNLS7 field values */ HDMI_FC_AUDSCHNLS7_ACCURACY_OFFSET = 4, HDMI_FC_AUDSCHNLS7_ACCURACY_MASK = 0x30,
HDMI_FC_AUDSCHNLS7_SMPRATE_MASK = 0x0f,HDMI_FC_AUDSCHNLS7_SMPRATE_192K = 0xe,HDMI_FC_AUDSCHNLS7_SMPRATE_176K4 = 0xc,HDMI_FC_AUDSCHNLS7_SMPRATE_96K = 0xa,HDMI_FC_AUDSCHNLS7_SMPRATE_768K = 0x9,HDMI_FC_AUDSCHNLS7_SMPRATE_88K2 = 0x8,HDMI_FC_AUDSCHNLS7_SMPRATE_32K = 0x3,HDMI_FC_AUDSCHNLS7_SMPRATE_48K = 0x2,HDMI_FC_AUDSCHNLS7_SMPRATE_44K1 = 0x0,These look very much like the IEC958_AES* consumer definitions in include/sound/asoundef.h.
ACK. Will remove in v3.
/* HDMI_FC_AUDSCHNLS8 field values */ HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_MASK = 0xf0, diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h index cf528c289857..12144d2f80f4 100644 --- a/include/drm/bridge/dw_hdmi.h +++ b/include/drm/bridge/dw_hdmi.h @@ -156,6 +156,8 @@ void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense);
void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate); void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt); +void dw_hdmi_set_channel_status(struct dw_hdmi *hdmi,
unsigned int sample_width);void dw_hdmi_set_channel_allocation(struct dw_hdmi *hdmi, unsigned int ca); void dw_hdmi_audio_enable(struct dw_hdmi *hdmi); void dw_hdmi_audio_disable(struct dw_hdmi *hdmi); -- 2.23.0.187.g17f5b7556c-goog
linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
-- RMK's Patch system: https://www.armlinux.org.uk/developer/patches/ FTTC broadband for 0.8mile line in suburbia: sync at 12.1Mbps down 622kbps up According to speedtest.net: 11.9Mbps down 500kbps up
participants (3)
-
Cheng-Yi Chiang -
Jernej Škrabec -
Russell King - ARM Linux admin