On Wed, Jul 12, 2023 at 8:53 PM Matus Gajdos matuszpd@gmail.com wrote:

Otherwise bit clock remains running writing invalid data to the DAC.

Signed-off-by: Matus Gajdos matuszpd@gmail.com

Acked-by: Shengjiu Wang shengjiu.wang@gmail.com

Best regards Wang Shengjiu

---

sound/soc/fsl/fsl_sai.c | 2 +- sound/soc/fsl/fsl_sai.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c index 5e09f634c61b..dcc7fbe7acac 100644 --- a/sound/soc/fsl/fsl_sai.c +++ b/sound/soc/fsl/fsl_sai.c @@ -719,7 +719,7 @@ static void fsl_sai_config_disable(struct fsl_sai *sai, int dir) u32 xcsr, count = 100;

    regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),

•                      FSL_SAI_CSR_TERE, 0);
  

•                      FSL_SAI_CSR_TERE | FSL_SAI_CSR_BCE, 0);
  
    /* TERE will remain set till the end of current frame */
    do {
  

diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h index 8254c3547b87..550df87b6a06 100644 --- a/sound/soc/fsl/fsl_sai.h +++ b/sound/soc/fsl/fsl_sai.h @@ -91,6 +91,7 @@ /* SAI Transmit/Receive Control Register */ #define FSL_SAI_CSR_TERE BIT(31) #define FSL_SAI_CSR_SE BIT(30) +#define FSL_SAI_CSR_BCE BIT(28) #define FSL_SAI_CSR_FR BIT(25) #define FSL_SAI_CSR_SR BIT(24)

#define FSL_SAI_CSR_xF_SHIFT 16

2.25.1