[alsa-devel] [asoc:for-4.21 167/168] sound/soc//meson/axg-spdifin.c:152:8: note: in expansion of macro 'do_div'

13 Dec 2018


      tree:   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-4.21
head:   1b46ed96961db1a826b3e5cadac18c7c4857f054
commit: 5ce5658375e6de2468c4884f7ae474c4ed40a13f [167/168] ASoC: meson: add axg spdif input
config: arm-allmodconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        git checkout 5ce5658375e6de2468c4884f7ae474c4ed40a13f
        # save the attached .config to linux build tree
        GCC_VERSION=7.2.0 make.cross ARCH=arm
All warnings (new ones prefixed by >>):
In file included from arch/arm/include/asm/div64.h:127:0,
                    from include/linux/kernel.h:207,
                    from include/linux/clk.h:16,
                    from sound/soc//meson/axg-spdifin.c:7:
   sound/soc//meson/axg-spdifin.c: In function 'axg_spdifin_write_mode_param':
   include/asm-generic/div64.h:222:28: warning: comparison of distinct pointer types lacks a cast
     (void)(((typeof((n)) *)0) == ((uint64_t *)0)); \
                               ^
...
...
sound/soc//meson/axg-spdifin.c:152:8: note: in expansion of macro 'do_div'
rem = do_div(offset, num_per_reg);
           ^~~~~~
   In file included from include/linux/build_bug.h:5:0,
                    from include/linux/bitfield.h:18,
                    from sound/soc//meson/axg-spdifin.c:6:
   include/asm-generic/div64.h:235:25: warning: right shift count >= width of type [-Wshift-count-overflow]
     } else if (likely(((n) >> 32) == 0)) {  \
                            ^
   include/linux/compiler.h:76:40: note: in definition of macro 'likely'
    # define likely(x) __builtin_expect(!!(x), 1)
                                           ^
...
...
sound/soc//meson/axg-spdifin.c:152:8: note: in expansion of macro 'do_div'
rem = do_div(offset, num_per_reg);
           ^~~~~~
   In file included from arch/arm/include/asm/div64.h:127:0,
                    from include/linux/kernel.h:207,
                    from include/linux/clk.h:16,
                    from sound/soc//meson/axg-spdifin.c:7:
   include/asm-generic/div64.h:239:22: error: passing argument 1 of '__div64_32' from incompatible pointer type [-Werror=incompatible-pointer-types]
      __rem = __div64_32(&(n), __base); \
                         ^
...
...
sound/soc//meson/axg-spdifin.c:152:8: note: in expansion of macro 'do_div'
rem = do_div(offset, num_per_reg);
           ^~~~~~
   In file included from include/linux/kernel.h:207:0,
                    from include/linux/clk.h:16,
                    from sound/soc//meson/axg-spdifin.c:7:
   arch/arm/include/asm/div64.h:33:24: note: expected 'uint64_t * {aka long long unsigned int *}' but argument is of type 'unsigned int *'
    static inline uint32_t __div64_32(uint64_t *n, uint32_t base)
                           ^~~~~~~~~~
   cc1: some warnings being treated as errors
vim +/do_div +152 sound/soc//meson/axg-spdifin.c
5	
     6	#include <linux/bitfield.h>
...
7	#include <linux/clk.h>
8	#include <linux/module.h>
     9	#include <linux/of_platform.h>
    10	#include <linux/regmap.h>
    11	#include <sound/soc.h>
    12	#include <sound/soc-dai.h>
    13	#include <sound/pcm_params.h>
    14	
    15	#define SPDIFIN_CTRL0			0x00
    16	#define  SPDIFIN_CTRL0_EN		BIT(31)
    17	#define  SPDIFIN_CTRL0_RST_OUT		BIT(29)
    18	#define  SPDIFIN_CTRL0_RST_IN		BIT(28)
    19	#define  SPDIFIN_CTRL0_WIDTH_SEL	BIT(24)
    20	#define  SPDIFIN_CTRL0_STATUS_CH_SHIFT	11
    21	#define  SPDIFIN_CTRL0_STATUS_SEL	GENMASK(10, 8)
    22	#define  SPDIFIN_CTRL0_SRC_SEL		GENMASK(5, 4)
    23	#define  SPDIFIN_CTRL0_CHK_VALID	BIT(3)
    24	#define SPDIFIN_CTRL1			0x04
    25	#define  SPDIFIN_CTRL1_BASE_TIMER	GENMASK(19, 0)
    26	#define  SPDIFIN_CTRL1_IRQ_MASK		GENMASK(27, 20)
    27	#define SPDIFIN_CTRL2			0x08
    28	#define  SPDIFIN_THRES_PER_REG		3
    29	#define  SPDIFIN_THRES_WIDTH		10
    30	#define SPDIFIN_CTRL3			0x0c
    31	#define SPDIFIN_CTRL4			0x10
    32	#define  SPDIFIN_TIMER_PER_REG		4
    33	#define  SPDIFIN_TIMER_WIDTH		8
    34	#define SPDIFIN_CTRL5			0x14
    35	#define SPDIFIN_CTRL6			0x18
    36	#define SPDIFIN_STAT0			0x1c
    37	#define  SPDIFIN_STAT0_MODE		GENMASK(30, 28)
    38	#define  SPDIFIN_STAT0_MAXW		GENMASK(17, 8)
    39	#define  SPDIFIN_STAT0_IRQ		GENMASK(7, 0)
    40	#define  SPDIFIN_IRQ_MODE_CHANGED	BIT(2)
    41	#define SPDIFIN_STAT1			0x20
    42	#define SPDIFIN_STAT2			0x24
    43	#define SPDIFIN_MUTE_VAL		0x28
    44	
    45	#define SPDIFIN_MODE_NUM		7
    46	
    47	struct axg_spdifin_cfg {
    48		const unsigned int *mode_rates;
    49		unsigned int ref_rate;
    50	};
    51	
    52	struct axg_spdifin {
    53		const struct axg_spdifin_cfg *conf;
    54		struct regmap *map;
    55		struct clk *refclk;
    56		struct clk *pclk;
    57	};
    58	
    59	/*
    60	 * TODO:
    61	 * It would have been nice to check the actual rate against the sample rate
    62	 * requested in hw_params(). Unfortunately, I was not able to make the mode
    63	 * detection and IRQ work reliably:
    64	 *
    65	 * 1. IRQs are generated on mode change only, so there is no notification
    66	 *    on transition between no signal and mode 0 (32kHz).
    67	 * 2. Mode detection very often has glitches, and may detects the
    68	 *    lowest or the highest mode before zeroing in on the actual mode.
    69	 *
    70	 * This makes calling snd_pcm_stop() difficult to get right. Even notifying
    71	 * the kcontrol would be very unreliable at this point.
    72	 * Let's keep things simple until the magic spell that makes this work is
    73	 * found.
    74	 */
    75	
    76	static unsigned int axg_spdifin_get_rate(struct axg_spdifin *priv)
    77	{
    78		unsigned int stat, mode, rate = 0;
    79	
    80		regmap_read(priv->map, SPDIFIN_STAT0, &stat);
    81		mode = FIELD_GET(SPDIFIN_STAT0_MODE, stat);
    82	
    83		/*
    84		 * If max width is zero, we are not capturing anything.
    85		 * Also Sometimes, when the capture is on but there is no data,
    86		 * mode is SPDIFIN_MODE_NUM, but not always ...
    87		 */
    88		if (FIELD_GET(SPDIFIN_STAT0_MAXW, stat) &&
    89		    mode < SPDIFIN_MODE_NUM)
    90			rate = priv->conf->mode_rates[mode];
    91	
    92		return rate;
    93	}
    94	
    95	static int axg_spdifin_prepare(struct snd_pcm_substream *substream,
    96				       struct snd_soc_dai *dai)
    97	{
    98		struct axg_spdifin *priv = snd_soc_dai_get_drvdata(dai);
    99	
   100		/* Apply both reset */
   101		regmap_update_bits(priv->map, SPDIFIN_CTRL0,
   102				   SPDIFIN_CTRL0_RST_OUT |
   103				   SPDIFIN_CTRL0_RST_IN,
   104				   0);
   105	
   106		/* Clear out reset before in reset */
   107		regmap_update_bits(priv->map, SPDIFIN_CTRL0,
   108				   SPDIFIN_CTRL0_RST_OUT, SPDIFIN_CTRL0_RST_OUT);
   109		regmap_update_bits(priv->map, SPDIFIN_CTRL0,
   110				   SPDIFIN_CTRL0_RST_IN,  SPDIFIN_CTRL0_RST_IN);
   111	
   112		return 0;
   113	}
   114	
   115	static int axg_spdifin_startup(struct snd_pcm_substream *substream,
   116				       struct snd_soc_dai *dai)
   117	{
   118		struct axg_spdifin *priv = snd_soc_dai_get_drvdata(dai);
   119		int ret;
   120	
   121		ret = clk_prepare_enable(priv->refclk);
   122		if (ret) {
   123			dev_err(dai->dev,
   124				"failed to enable spdifin reference clock\n");
   125			return ret;
   126		}
   127	
   128		regmap_update_bits(priv->map, SPDIFIN_CTRL0, SPDIFIN_CTRL0_EN,
   129				   SPDIFIN_CTRL0_EN);
   130	
   131		return 0;
   132	}
   133	
   134	static void axg_spdifin_shutdown(struct snd_pcm_substream *substream,
   135					 struct snd_soc_dai *dai)
   136	{
   137		struct axg_spdifin *priv = snd_soc_dai_get_drvdata(dai);
   138	
   139		regmap_update_bits(priv->map, SPDIFIN_CTRL0, SPDIFIN_CTRL0_EN, 0);
   140		clk_disable_unprepare(priv->refclk);
   141	}
   142	
   143	static void axg_spdifin_write_mode_param(struct regmap *map, int mode,
   144						 unsigned int val,
   145						 unsigned int num_per_reg,
   146						 unsigned int base_reg,
   147						 unsigned int width)
   148	{
   149		unsigned int offset = mode, rem;
   150		unsigned int reg, shift;
   151
...
152		rem = do_div(offset, num_per_reg);
153	
   154		reg = offset * regmap_get_reg_stride(map) + base_reg;
   155		shift = width * (num_per_reg - 1 - rem);
   156	
   157		regmap_update_bits(map, reg, GENMASK(width - 1, 0) << shift,
   158				   val << shift);
   159	}
   160
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