On 12/3/2021 6:58 PM, Srinivas Kandagatla wrote: Thanks for your time Srini!!!

On 02/12/2021 15:43, Srinivasa Rao Mandadapu wrote:

...

From: Srinivasa Rao Mandadapu srivasam@codeaurora.org

This patch adds register definitions for codec read dma and write dma lpass interface.

Signed-off-by: Srinivasa Rao Mandadapu srivasam@codeaurora.org Co-developed-by: Venkata Prasad Potturu potturu@codeaurora.org Signed-off-by: Venkata Prasad Potturu potturu@codeaurora.org

Overall the patch LGTM, but for bisectablity reasons, pleas make sure these macros

is_rxtx_cdc_dma_port() is_cdc_dma_port()

to be avaiable in this patch.

Okay. Will change accordingly.

Once that is fixed you could add my

Reviewed-by: Srinivas Kandagatla srinivas.kandagatla@linaro.org

--srini

...

---

sound/soc/qcom/lpass-lpaif-reg.h | 127 +++++++++++++++++++++++++++++++++++++--   1 file changed, 121 insertions(+), 6 deletions(-)

diff --git a/sound/soc/qcom/lpass-lpaif-reg.h b/sound/soc/qcom/lpass-lpaif-reg.h index 2eb03ad..6d9d9d1 100644 --- a/sound/soc/qcom/lpass-lpaif-reg.h +++ b/sound/soc/qcom/lpass-lpaif-reg.h @@ -74,6 +74,21 @@   #define LPAIF_IRQSTAT_REG(v, port)    LPAIF_IRQ_REG_ADDR(v, 0x4, (port))   #define LPAIF_IRQCLEAR_REG(v, port)    LPAIF_IRQ_REG_ADDR(v, 0xC, (port))   +/* LPAIF RXTX IRQ */ +#define LPAIF_RXTX_IRQ_REG_ADDR(v, addr, port) \ +        (v->rxtx_irq_reg_base + (addr) + v->rxtx_irq_reg_stride * (port))

+#define LPAIF_RXTX_IRQEN_REG(v, port) LPAIF_RXTX_IRQ_REG_ADDR(v, 0x0, port) +#define LPAIF_RXTX_IRQSTAT_REG(v, port) LPAIF_RXTX_IRQ_REG_ADDR(v, 0x4, port) +#define LPAIF_RXTX_IRQCLEAR_REG(v, port) LPAIF_RXTX_IRQ_REG_ADDR(v, 0xC, port)

+/* LPAIF VA IRQ */ +#define LPAIF_VA_IRQ_REG_ADDR(v, addr, port) \ +        (v->va_irq_reg_base + (addr) + v->va_irq_reg_stride * (port))

+#define LPAIF_VA_IRQEN_REG(v, port) LPAIF_VA_IRQ_REG_ADDR(v, 0x0, port) +#define LPAIF_VA_IRQSTAT_REG(v, port) LPAIF_VA_IRQ_REG_ADDR(v, 0x4, port) +#define LPAIF_VA_IRQCLEAR_REG(v, port) LPAIF_VA_IRQ_REG_ADDR(v, 0xC, port)     #define LPASS_HDMITX_APP_IRQ_REG_ADDR(v, addr)  \       ((v->hdmi_irq_reg_base) + (addr)) @@ -139,12 +154,112 @@           (LPAIF_INTFDMA_REG(v, chan, reg, dai_id)) : \           LPAIF_WRDMA##reg##_REG(v, chan))   -#define LPAIF_DMACTL_REG(v, chan, dir, dai_id) __LPAIF_DMA_REG(v, chan, dir, CTL, dai_id) -#define LPAIF_DMABASE_REG(v, chan, dir, dai_id) __LPAIF_DMA_REG(v, chan, dir, BASE, dai_id) -#define    LPAIF_DMABUFF_REG(v, chan, dir, dai_id) __LPAIF_DMA_REG(v, chan, dir, BUFF, dai_id) -#define LPAIF_DMACURR_REG(v, chan, dir, dai_id) __LPAIF_DMA_REG(v, chan, dir, CURR, dai_id) -#define    LPAIF_DMAPER_REG(v, chan, dir, dai_id) __LPAIF_DMA_REG(v, chan, dir, PER, dai_id) -#define    LPAIF_DMAPERCNT_REG(v, chan, dir, dai_id) __LPAIF_DMA_REG(v, chan, dir, PERCNT, dai_id) +#define LPAIF_DMACTL_REG(v, chan, dir, dai_id) \ +    (is_cdc_dma_port(dai_id) ? \ +    __LPAIF_CDC_DMA_REG(v, chan, dir, CTL, dai_id) : \ +    __LPAIF_DMA_REG(v, chan, dir, CTL, dai_id)) +#define LPAIF_DMABASE_REG(v, chan, dir, dai_id) \ +    (is_cdc_dma_port(dai_id) ? \ +    __LPAIF_CDC_DMA_REG(v, chan, dir, BASE, dai_id) : \ +    __LPAIF_DMA_REG(v, chan, dir, BASE, dai_id)) +#define LPAIF_DMABUFF_REG(v, chan, dir, dai_id) \ +    (is_cdc_dma_port(dai_id) ? \ +    __LPAIF_CDC_DMA_REG(v, chan, dir, BUFF, dai_id) : \ +    __LPAIF_DMA_REG(v, chan, dir, BUFF, dai_id)) +#define LPAIF_DMACURR_REG(v, chan, dir, dai_id) \ +    (is_cdc_dma_port(dai_id) ? \ +    __LPAIF_CDC_DMA_REG(v, chan, dir, CURR, dai_id) : \ +    __LPAIF_DMA_REG(v, chan, dir, CURR, dai_id)) +#define LPAIF_DMAPER_REG(v, chan, dir, dai_id)  \ +    (is_cdc_dma_port(dai_id) ? \ +    __LPAIF_CDC_DMA_REG(v, chan, dir, PER, dai_id) : \ +    __LPAIF_DMA_REG(v, chan, dir, PER, dai_id)) +#define LPAIF_DMAPERCNT_REG(v, chan, dir, dai_id) \ +    (is_cdc_dma_port(dai_id) ? \ +    __LPAIF_CDC_DMA_REG(v, chan, dir, PERCNT, dai_id) : \ +    __LPAIF_DMA_REG(v, chan, dir, PERCNT, dai_id))

+#define LPAIF_CDC_RDMA_REG_ADDR(v, addr, chan, dai_id) \ +    (is_rxtx_cdc_dma_port(dai_id) ? \ +    (v->rxtx_rdma_reg_base + (addr) + v->rxtx_rdma_reg_stride * (chan)) : \ +    (v->va_rdma_reg_base + (addr) + v->va_rdma_reg_stride * (chan)))

+#define LPAIF_CDC_RXTX_RDMACTL_REG(v, chan, dai_id) \ +        LPAIF_CDC_RDMA_REG_ADDR(v, 0x00, (chan), dai_id) +#define LPAIF_CDC_RXTX_RDMABASE_REG(v, chan, dai_id) \ +        LPAIF_CDC_RDMA_REG_ADDR(v, 0x04, (chan), dai_id) +#define LPAIF_CDC_RXTX_RDMABUFF_REG(v, chan, dai_id) \ +        LPAIF_CDC_RDMA_REG_ADDR(v, 0x08, (chan), dai_id) +#define LPAIF_CDC_RXTX_RDMACURR_REG(v, chan, dai_id) \ +        LPAIF_CDC_RDMA_REG_ADDR(v, 0x0C, (chan), dai_id) +#define LPAIF_CDC_RXTX_RDMAPER_REG(v, chan, dai_id) \ +        LPAIF_CDC_RDMA_REG_ADDR(v, 0x10, (chan), dai_id) +#define LPAIF_CDC_RXTX_RDMA_INTF_REG(v, chan, dai_id) \ +    LPAIF_CDC_RDMA_REG_ADDR(v, 0x50, (chan), dai_id)

+#define LPAIF_CDC_VA_RDMACTL_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x00, (chan), dai_id) +#define LPAIF_CDC_VA_RDMABASE_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x04, (chan), dai_id) +#define LPAIF_CDC_VA_RDMABUFF_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x08, (chan), dai_id) +#define LPAIF_CDC_VA_RDMACURR_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x0C, (chan), dai_id) +#define LPAIF_CDC_VA_RDMAPER_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x10, (chan), dai_id) +#define LPAIF_CDC_VA_RDMA_INTF_REG(v, chan, dai_id) \ +    LPAIF_CDC_RDMA_REG_ADDR(v, 0x50, (chan), dai_id)

+#define LPAIF_CDC_WRDMA_REG_ADDR(v, addr, chan, dai_id) \ +    (is_rxtx_cdc_dma_port(dai_id) ? \ +    (v->rxtx_wrdma_reg_base + (addr) + \ +        v->rxtx_wrdma_reg_stride * (chan - v->rxtx_wrdma_channel_start)) : \ +    (v->va_wrdma_reg_base + (addr) + \ +        v->va_wrdma_reg_stride * (chan - v->va_wrdma_channel_start)))

+#define LPAIF_CDC_RXTX_WRDMACTL_REG(v, chan, dai_id) \ +    LPAIF_CDC_WRDMA_REG_ADDR(v, 0x00, (chan), dai_id) +#define LPAIF_CDC_RXTX_WRDMABASE_REG(v, chan, dai_id) \ +    LPAIF_CDC_WRDMA_REG_ADDR(v, 0x04, (chan), dai_id) +#define LPAIF_CDC_RXTX_WRDMABUFF_REG(v, chan, dai_id) \ +    LPAIF_CDC_WRDMA_REG_ADDR(v, 0x08, (chan), dai_id) +#define LPAIF_CDC_RXTX_WRDMACURR_REG(v, chan, dai_id) \ +    LPAIF_CDC_WRDMA_REG_ADDR(v, 0x0C, (chan), dai_id) +#define LPAIF_CDC_RXTX_WRDMAPER_REG(v, chan, dai_id) \ +    LPAIF_CDC_WRDMA_REG_ADDR(v, 0x10, (chan), dai_id) +#define LPAIF_CDC_RXTX_WRDMA_INTF_REG(v, chan, dai_id) \ +    LPAIF_CDC_WRDMA_REG_ADDR(v, 0x50, (chan), dai_id)

+#define LPAIF_CDC_VA_WRDMACTL_REG(v, chan, dai_id) \ +    LPAIF_CDC_WRDMA_REG_ADDR(v, 0x00, (chan), dai_id) +#define LPAIF_CDC_VA_WRDMABASE_REG(v, chan, dai_id) \ +    LPAIF_CDC_WRDMA_REG_ADDR(v, 0x04, (chan), dai_id) +#define LPAIF_CDC_VA_WRDMABUFF_REG(v, chan, dai_id) \ +    LPAIF_CDC_WRDMA_REG_ADDR(v, 0x08, (chan), dai_id) +#define LPAIF_CDC_VA_WRDMACURR_REG(v, chan, dai_id) \ +    LPAIF_CDC_WRDMA_REG_ADDR(v, 0x0C, (chan), dai_id) +#define LPAIF_CDC_VA_WRDMAPER_REG(v, chan, dai_id) \ +    LPAIF_CDC_WRDMA_REG_ADDR(v, 0x10, (chan), dai_id) +#define LPAIF_CDC_VA_WRDMA_INTF_REG(v, chan, dai_id) \ +    LPAIF_CDC_WRDMA_REG_ADDR(v, 0x50, (chan), dai_id)

+#define __LPAIF_CDC_RDDMA_REG(v, chan, dir, reg, dai_id) \ +        (is_rxtx_cdc_dma_port(dai_id) ? LPAIF_CDC_RXTX_RDMA##reg##_REG(v, chan, dai_id) : \ +            LPAIF_CDC_VA_RDMA##reg##_REG(v, chan, dai_id))

+#define __LPAIF_CDC_WRDMA_REG(v, chan, dir, reg, dai_id) \ +        (is_rxtx_cdc_dma_port(dai_id) ? LPAIF_CDC_RXTX_WRDMA##reg##_REG(v, chan, dai_id) : \ +            LPAIF_CDC_VA_WRDMA##reg##_REG(v, chan, dai_id))

+#define __LPAIF_CDC_DMA_REG(v, chan, dir, reg, dai_id) \ +        ((dir ==  SNDRV_PCM_STREAM_PLAYBACK) ? \ +            __LPAIF_CDC_RDDMA_REG(v, chan, dir, reg, dai_id) : \ +            __LPAIF_CDC_WRDMA_REG(v, chan, dir, reg, dai_id))

+#define LPAIF_CDC_INTF_REG(v, chan, dir, dai_id) \ +        ((dir ==  SNDRV_PCM_STREAM_PLAYBACK) ? \ +        LPAIF_CDC_RDMA_INTF_REG(v, chan, dai_id) : \ +        LPAIF_CDC_WRDMA_INTF_REG(v, chan, dai_id))

+#define LPAIF_INTF_REG(v, chan, dir, dai_id) \ +        (is_cdc_dma_port(dai_id) ? \ +        LPAIF_CDC_INTF_REG(v, chan, dir, dai_id) : \ +        LPAIF_DMACTL_REG(v, chan, dir, dai_id))     #define LPAIF_DMACTL_BURSTEN_SINGLE    0   #define LPAIF_DMACTL_BURSTEN_INCR4    1

On 02/12/2021 15:43, Srinivasa Rao Mandadapu wrote:

From: Srinivasa Rao Mandadapu srivasam@codeaurora.org

Add lpass cpu driver to support audio over codec dma for ADSP bypass usecase.

Signed-off-by: Srinivasa Rao Mandadapu srivasam@codeaurora.org Co-developed-by: Venkata Prasad Potturu potturu@codeaurora.org Signed-off-by: Venkata Prasad Potturu potturu@codeaurora.org

LGTM,

Reviewed-by: Srinivas Kandagatla srinivas.kandagatla@linaro.org

---

sound/soc/qcom/lpass-cdc-dma.c | 275 +++++++++++++++++++++++++++++++++++++++++ sound/soc/qcom/lpass.h | 1 + 2 files changed, 276 insertions(+) create mode 100644 sound/soc/qcom/lpass-cdc-dma.c

diff --git a/sound/soc/qcom/lpass-cdc-dma.c b/sound/soc/qcom/lpass-cdc-dma.c new file mode 100644 index 0000000..51cd7ea --- /dev/null +++ b/sound/soc/qcom/lpass-cdc-dma.c @@ -0,0 +1,275 @@ +// SPDX-License-Identifier: GPL-2.0-only +/*

• • Copyright (c) 2021 The Linux Foundation. All rights reserved.
• • lpass-cdc-dma.c -- ALSA SoC CDC DMA CPU DAI driver for QTi LPASS
• */

+#include <linux/clk.h> +#include <linux/module.h> +#include <sound/soc.h> +#include <sound/soc-dai.h>

+#include "lpass-lpaif-reg.h" +#include "lpass.h"

+enum codec_dma_interfaces {

• LPASS_CDC_DMA_INTERFACE1 = 1,
• LPASS_CDC_DMA_INTERFACE2,
• LPASS_CDC_DMA_INTERFACE3,
• LPASS_CDC_DMA_INTERFACE4,
• LPASS_CDC_DMA_INTERFACE5,
• LPASS_CDC_DMA_INTERFACE6,
• LPASS_CDC_DMA_INTERFACE7,
• LPASS_CDC_DMA_INTERFACE8,
• LPASS_CDC_DMA_INTERFACE9,
• LPASS_CDC_DMA_INTERFACE10,

+};

+static void __lpass_get_dmactl_handle(struct snd_pcm_substream *substream, struct snd_soc_dai *dai,

• 		      struct lpaif_dmactl **dmactl, int *id)
  

+{

• struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
• struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_runtime, 0);
• struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
• struct snd_pcm_runtime *rt = substream->runtime;
• struct lpass_pcm_data *pcm_data = rt->private_data;
• struct lpass_variant *v = drvdata->variant;
• unsigned int dai_id = cpu_dai->driver->id;
• switch (dai_id) {
• case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9:

• *dmactl = drvdata->rxtx_rd_dmactl;
  

• *id = pcm_data->dma_ch;
  

• break;
  

• case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8:

• *dmactl = drvdata->rxtx_wr_dmactl;
  

• *id = pcm_data->dma_ch - v->rxtx_wrdma_channel_start;
  

• break;
  

• case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX8:

• *dmactl = drvdata->va_wr_dmactl;
  

• *id = pcm_data->dma_ch - v->va_wrdma_channel_start;
  

• break;
  

• default:

• dev_err(soc_runtime->dev, "invalid dai id for dma ctl: %d\n", dai_id);
  

• break;
  

• }

+}

+static int __lpass_get_codec_dma_intf_type(int dai_id) +{

• int ret;
• switch (dai_id) {
• case LPASS_CDC_DMA_RX0:
• case LPASS_CDC_DMA_TX0:
• case LPASS_CDC_DMA_VA_TX0:

• ret = LPASS_CDC_DMA_INTERFACE1;
  

• break;
  

• case LPASS_CDC_DMA_RX1:
• case LPASS_CDC_DMA_TX1:
• case LPASS_CDC_DMA_VA_TX1:

• ret = LPASS_CDC_DMA_INTERFACE2;
  

• break;
  

• case LPASS_CDC_DMA_RX2:
• case LPASS_CDC_DMA_TX2:
• case LPASS_CDC_DMA_VA_TX2:

• ret = LPASS_CDC_DMA_INTERFACE3;
  

• break;
  

• case LPASS_CDC_DMA_RX3:
• case LPASS_CDC_DMA_TX3:
• case LPASS_CDC_DMA_VA_TX3:

• ret = LPASS_CDC_DMA_INTERFACE4;
  

• break;
  

• case LPASS_CDC_DMA_RX4:
• case LPASS_CDC_DMA_TX4:
• case LPASS_CDC_DMA_VA_TX4:

• ret = LPASS_CDC_DMA_INTERFACE5;
  

• break;
  

• case LPASS_CDC_DMA_RX5:
• case LPASS_CDC_DMA_TX5:
• case LPASS_CDC_DMA_VA_TX5:

• ret = LPASS_CDC_DMA_INTERFACE6;
  

• break;
  

• case LPASS_CDC_DMA_RX6:
• case LPASS_CDC_DMA_TX6:
• case LPASS_CDC_DMA_VA_TX6:

• ret = LPASS_CDC_DMA_INTERFACE7;
  

• break;
  

• case LPASS_CDC_DMA_RX7:
• case LPASS_CDC_DMA_TX7:
• case LPASS_CDC_DMA_VA_TX7:

• ret = LPASS_CDC_DMA_INTERFACE8;
  

• break;
  

• case LPASS_CDC_DMA_RX8:
• case LPASS_CDC_DMA_TX8:
• case LPASS_CDC_DMA_VA_TX8:

• ret = LPASS_CDC_DMA_INTERFACE9;
  

• break;
  

• case LPASS_CDC_DMA_RX9:

• ret  = LPASS_CDC_DMA_INTERFACE10;
  

• break;
  

• default:

• ret = -EINVAL;
  

• break;
  

• }
• return ret;

+}

+static int __lpass_platform_codec_intf_init(struct snd_soc_dai *dai,

• 			    struct snd_pcm_substream *substream)
  

+{

• struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
• struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_runtime, 0);
• struct lpaif_dmactl *dmactl = NULL;
• struct device *dev = soc_runtime->dev;
• int ret, id, codec_intf;
• unsigned int dai_id = cpu_dai->driver->id;
• codec_intf = __lpass_get_codec_dma_intf_type(dai_id);
• if (codec_intf < 0) {

• dev_err(dev, "failed to get codec_intf: %d\n", codec_intf);
  

• return codec_intf;
  

• }
• __lpass_get_dmactl_handle(substream, dai, &dmactl, &id);
• if (!dmactl) {

• dev_err(dev, "failed to get dmactl handle for dai_id: %d\n", dai_id);
  

• return -EINVAL;
  

• }
• ret = regmap_fields_write(dmactl->codec_intf, id, codec_intf);
• if (ret) {

• dev_err(dev, "error writing to dmactl codec_intf reg field: %d\n", ret);
  

• return ret;
  

• }
• ret = regmap_fields_write(dmactl->codec_fs_sel, id, 0x0);
• if (ret) {

• dev_err(dev, "error writing to dmactl codec_fs_sel reg field: %d\n", ret);
  

• return ret;
  

• }
• ret = regmap_fields_write(dmactl->codec_fs_delay, id, 0x0);
• if (ret) {

• dev_err(dev, "error writing to dmactl codec_fs_delay reg field: %d\n", ret);
  

• return ret;
  

• }
• ret = regmap_fields_write(dmactl->codec_pack, id, 0x1);
• if (ret) {

• dev_err(dev, "error writing to dmactl codec_pack reg field: %d\n", ret);
  

• return ret;
  

• }
• ret = regmap_fields_write(dmactl->codec_enable, id, LPAIF_DMACTL_ENABLE_ON);
• if (ret) {

• dev_err(dev, "error writing to dmactl codec_enable reg field: %d\n", ret);
  

• return ret;
  

• }
• return 0;

+}

+static int lpass_cdc_dma_daiops_startup(struct snd_pcm_substream *substream,

• 		    struct snd_soc_dai *dai)
  

+{

• struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
• return clk_bulk_prepare_enable(drvdata->cdc_num_clks, drvdata->cdc_clks);

+}

+static void lpass_cdc_dma_daiops_shutdown(struct snd_pcm_substream *substream,

• 		      struct snd_soc_dai *dai)
  

+{

• struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
• clk_bulk_disable_unprepare(drvdata->cdc_num_clks, drvdata->cdc_clks);

+}

+static int lpass_cdc_dma_daiops_hw_params(struct snd_pcm_substream *substream,

• 		      struct snd_pcm_hw_params *params,
  

• 		      struct snd_soc_dai *dai)
  

+{

• struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
• struct lpaif_dmactl *dmactl = NULL;
• unsigned int ret, regval;
• unsigned int channels = params_channels(params);
• int id;
• switch (channels) {
• case 1:

• regval = LPASS_CDC_DMA_INTF_ONE_CHANNEL;
  

• break;
  

• case 2:

• regval = LPASS_CDC_DMA_INTF_TWO_CHANNEL;
  

• break;
  

• case 4:

• regval = LPASS_CDC_DMA_INTF_FOUR_CHANNEL;
  

• break;
  

• case 6:

• regval = LPASS_CDC_DMA_INTF_SIX_CHANNEL;
  

• break;
  

• case 8:

• regval = LPASS_CDC_DMA_INTF_EIGHT_CHANNEL;
  

• break;
  

• default:

• dev_err(soc_runtime->dev, "invalid PCM config\n");
  

• return -EINVAL;
  

• }
• __lpass_get_dmactl_handle(substream, dai, &dmactl, &id);
• if (!dmactl) {

• dev_err(soc_runtime->dev, "failed to get dmactl handle\n");
  

• return -EINVAL;
  

• }
• ret = regmap_fields_write(dmactl->codec_channel, id, regval);
• if (ret) {

• dev_err(soc_runtime->dev,
  

• 	"error writing to dmactl codec_channel reg field: %d\n", ret);
  

• return ret;
  

• }
• return 0;

+}

+static int lpass_cdc_dma_daiops_trigger(struct snd_pcm_substream *substream,

• 		    int cmd, struct snd_soc_dai *dai)
  

+{

• struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
• struct lpaif_dmactl *dmactl;
• int ret = 0, id;
• switch (cmd) {
• case SNDRV_PCM_TRIGGER_START:
• case SNDRV_PCM_TRIGGER_RESUME:
• case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:

• __lpass_platform_codec_intf_init(dai, substream);
  

• break;
  

• case SNDRV_PCM_TRIGGER_STOP:
• case SNDRV_PCM_TRIGGER_SUSPEND:
• case SNDRV_PCM_TRIGGER_PAUSE_PUSH:

• __lpass_get_dmactl_handle(substream, dai, &dmactl, &id);
  

• if (!dmactl) {
  

• 	dev_err(soc_runtime->dev, "failed to get dmactl handle\n");
  

• 	return -EINVAL;
  

• }
  

• ret = regmap_fields_write(dmactl->codec_enable, id, LPAIF_DMACTL_ENABLE_OFF);
  

• if (ret) {
  

• 	dev_err(soc_runtime->dev,
  

• 		"error writing to dmactl codec_enable reg: %d\n", ret);
  

• 	return ret;
  

• }
  

• break;
  

• default:

• ret = -EINVAL;
  

• dev_err(soc_runtime->dev, "%s: invalid %d interface\n", __func__, cmd);
  

• break;
  

• }
• return ret;

+}

+const struct snd_soc_dai_ops asoc_qcom_lpass_cdc_dma_dai_ops = {

• .startup = lpass_cdc_dma_daiops_startup,
• .shutdown = lpass_cdc_dma_daiops_shutdown,
• .hw_params = lpass_cdc_dma_daiops_hw_params,
• .trigger = lpass_cdc_dma_daiops_trigger,

+}; +EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cdc_dma_dai_ops);

+MODULE_DESCRIPTION("QTi LPASS CDC DMA Driver"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/qcom/lpass.h b/sound/soc/qcom/lpass.h index 4142f12..413cead 100644 --- a/sound/soc/qcom/lpass.h +++ b/sound/soc/qcom/lpass.h @@ -403,5 +403,6 @@ int asoc_qcom_lpass_cpu_dai_probe(struct snd_soc_dai *dai); extern const struct snd_soc_dai_ops asoc_qcom_lpass_cpu_dai_ops; int lpass_cpu_pcm_new(struct snd_soc_pcm_runtime *rtd, struct snd_soc_dai *dai); +extern const struct snd_soc_dai_ops asoc_qcom_lpass_cdc_dma_dai_ops;

#endif /* __LPASS_H__ */

On 12/3/2021 6:59 PM, Srinivas Kandagatla wrote: Thanks for your time Srini!!!

On 02/12/2021 15:43, Srinivasa Rao Mandadapu wrote:

...

From: Srinivasa Rao Mandadapu srivasam@codeaurora.org

Upadate lpass cpu and platform driver to support audio over codec dma in ADSP bypass use case.

Signed-off-by: Srinivasa Rao Mandadapu srivasam@codeaurora.org Co-developed-by: Venkata Prasad Potturu potturu@codeaurora.org Signed-off-by: Venkata Prasad Potturu potturu@codeaurora.org

---

sound/soc/qcom/lpass-cpu.c      |  59 ++++-   sound/soc/qcom/lpass-platform.c | 499 ++++++++++++++++++++++++++++++++++++++--   sound/soc/qcom/lpass.h          |  23 ++   3 files changed, 560 insertions(+), 21 deletions(-)

diff --git a/sound/soc/qcom/lpass-cpu.c b/sound/soc/qcom/lpass-cpu.c index 3bd9eb3..81818f0 100644 --- a/sound/soc/qcom/lpass-cpu.c +++ b/sound/soc/qcom/lpass-cpu.c @@ -857,7 +857,9 @@ static void of_lpass_cpu_parse_dai_data(struct device *dev,           }           if (id == LPASS_DP_RX) {               data->hdmi_port_enable = 1; -        } else { +        } else if (is_cdc_dma_port(id)) +            data->codec_dma_enable = 1; +        else {               data->mi2s_playback_sd_mode[id] =                   of_lpass_cpu_parse_sd_lines(dev, node,                                   "qcom,playback-sd-lines"); @@ -872,6 +874,7 @@ int asoc_qcom_lpass_cpu_platform_probe(struct platform_device *pdev)   {       struct lpass_data *drvdata;       struct device_node *dsp_of_node; +    struct resource *res;       struct lpass_variant *variant;       struct device *dev = &pdev->dev;       const struct of_device_id *match; @@ -897,6 +900,58 @@ int asoc_qcom_lpass_cpu_platform_probe(struct platform_device *pdev)         of_lpass_cpu_parse_dai_data(dev, drvdata);   +    drvdata->num_clks =  variant->num_clks; +    if (drvdata->codec_dma_enable) { +        drvdata->rxtx_lpaif = +                devm_platform_ioremap_resource_byname(pdev, "lpass-rxtx-lpaif"); +        if (IS_ERR(drvdata->rxtx_lpaif)) +            return PTR_ERR(drvdata->rxtx_lpaif);

+        drvdata->va_lpaif = devm_platform_ioremap_resource_byname(pdev, "lpass-va-lpaif"); +        if (IS_ERR(drvdata->va_lpaif)) +            return PTR_ERR(drvdata->va_lpaif);

+        lpass_rxtx_regmap_config.max_register = LPAIF_CDC_RXTX_WRDMAPER_REG(variant, +                    variant->rxtx_wrdma_channels + +                    variant->rxtx_wrdma_channel_start, LPASS_CDC_DMA_TX3);

lpass_rxtx_regmap_config is added in patch  07/10, so build will fail after applying this patch, so the bisectablity.

Please make sure the patches are bisectable.

Okay. Will order accordingly.

...

+        drvdata->rxtx_lpaif_map = devm_regmap_init_mmio(dev, drvdata->rxtx_lpaif, +                    &lpass_rxtx_regmap_config); +        if (IS_ERR(drvdata->rxtx_lpaif_map)) { +            dev_err(dev, "error initializing rxtx regmap: %ld\n", +                PTR_ERR(drvdata->rxtx_lpaif_map)); +            return PTR_ERR(drvdata->rxtx_lpaif_map); +        } +        lpass_va_regmap_config.max_register = LPAIF_CDC_VA_WRDMAPER_REG(variant, +                    variant->va_wrdma_channels + +                    variant->va_wrdma_channel_start, LPASS_CDC_DMA_VA_TX0);

+        drvdata->va_lpaif_map = devm_regmap_init_mmio(dev, drvdata->va_lpaif, +                    &lpass_va_regmap_config); +        if (IS_ERR(drvdata->va_lpaif_map)) { +            dev_err(dev, "error initializing va regmap: %ld\n", +                PTR_ERR(drvdata->va_lpaif_map)); +            return PTR_ERR(drvdata->va_lpaif_map); +        } +        drvdata->cdc_clks = devm_kcalloc(dev, variant->cdc_dma_num_clks, +                    sizeof(*drvdata->cdc_clks), GFP_KERNEL); +        drvdata->cdc_num_clks = variant->cdc_dma_num_clks;

+        for (i = 0; i < drvdata->cdc_num_clks; i++) +            drvdata->cdc_clks[i].id = variant->cdc_dma_clk_names[i];

+        ret = devm_clk_bulk_get(dev, drvdata->cdc_num_clks, drvdata->cdc_clks); +        if (ret) { +            dev_err(dev, "Failed to get clocks %d\n", ret); +            return ret; +        }

+        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lpass-rxtx-cdc-dma-lpm"); +        drvdata->rxtx_cdc_dma_lpm_buf = res->start;

+        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lpass-va-cdc-dma-lpm"); +        drvdata->va_cdc_dma_lpm_buf = res->start; +    }       drvdata->lpaif = devm_platform_ioremap_resource_byname(pdev, "lpass-lpaif");       if (IS_ERR(drvdata->lpaif))           return PTR_ERR(drvdata->lpaif); @@ -939,7 +994,7 @@ int asoc_qcom_lpass_cpu_platform_probe(struct platform_device *pdev)         for (i = 0; i < variant->num_dai; i++) {           dai_id = variant->dai_driver[i].id; -        if (dai_id == LPASS_DP_RX) +        if (dai_id == LPASS_DP_RX || is_cdc_dma_port(dai_id))               continue;             drvdata->mi2s_osr_clk[dai_id] = devm_clk_get_optional(dev, diff --git a/sound/soc/qcom/lpass-platform.c b/sound/soc/qcom/lpass-platform.c index 5d77240..acf10ae 100644 --- a/sound/soc/qcom/lpass-platform.c +++ b/sound/soc/qcom/lpass-platform.c @@ -20,6 +20,9 @@     #define LPASS_PLATFORM_BUFFER_SIZE    (24 *  2 * 1024)   #define LPASS_PLATFORM_PERIODS        2 +#define LPASS_RXTX_CDC_DMA_LPM_BUFF_SIZE (24 * 1024) +#define LPASS_VA_CDC_DMA_LPM_BUFF_SIZE (12 * 1024) +#define LPASS_CDC_DMA_REGISTER_FIELDS_MAX 15     static const struct snd_pcm_hardware lpass_platform_pcm_hardware = {       .info            =    SNDRV_PCM_INFO_MMAP | @@ -45,6 +48,99 @@ static const struct snd_pcm_hardware lpass_platform_pcm_hardware = {       .fifo_size        =    0,   };   +static const struct snd_pcm_hardware lpass_platform_rxtx_hardware = { +    .info            =    SNDRV_PCM_INFO_MMAP | +                    SNDRV_PCM_INFO_MMAP_VALID | +                    SNDRV_PCM_INFO_INTERLEAVED | +                    SNDRV_PCM_INFO_PAUSE | +                    SNDRV_PCM_INFO_RESUME, +    .formats        =    SNDRV_PCM_FMTBIT_S16 | +                    SNDRV_PCM_FMTBIT_S24 | +                    SNDRV_PCM_FMTBIT_S32, +    .rates            =    SNDRV_PCM_RATE_8000_192000, +    .rate_min        =    8000, +    .rate_max        =    192000, +    .channels_min        =    1, +    .channels_max        =    8, +    .buffer_bytes_max    =    LPASS_RXTX_CDC_DMA_LPM_BUFF_SIZE, +    .period_bytes_max    =    LPASS_RXTX_CDC_DMA_LPM_BUFF_SIZE / +                        LPASS_PLATFORM_PERIODS, +    .period_bytes_min    =    LPASS_RXTX_CDC_DMA_LPM_BUFF_SIZE / +                        LPASS_PLATFORM_PERIODS, +    .periods_min        =    LPASS_PLATFORM_PERIODS, +    .periods_max        =    LPASS_PLATFORM_PERIODS, +    .fifo_size        =    0, +};

+static const struct snd_pcm_hardware lpass_platform_va_hardware = { +    .info            =    SNDRV_PCM_INFO_MMAP | +                    SNDRV_PCM_INFO_MMAP_VALID | +                    SNDRV_PCM_INFO_INTERLEAVED | +                    SNDRV_PCM_INFO_PAUSE | +                    SNDRV_PCM_INFO_RESUME, +    .formats        =    SNDRV_PCM_FMTBIT_S16 | +                    SNDRV_PCM_FMTBIT_S24 | +                    SNDRV_PCM_FMTBIT_S32, +    .rates            =    SNDRV_PCM_RATE_8000_192000, +    .rate_min        =    8000, +    .rate_max        =    192000, +    .channels_min        =    1, +    .channels_max        =    8, +    .buffer_bytes_max    =    LPASS_VA_CDC_DMA_LPM_BUFF_SIZE, +    .period_bytes_max    =    LPASS_VA_CDC_DMA_LPM_BUFF_SIZE / +                        LPASS_PLATFORM_PERIODS, +    .period_bytes_min    =    LPASS_VA_CDC_DMA_LPM_BUFF_SIZE / +                        LPASS_PLATFORM_PERIODS, +    .periods_min        =    LPASS_PLATFORM_PERIODS, +    .periods_max        =    LPASS_PLATFORM_PERIODS, +    .fifo_size        =    0, +};

+static int lpass_platform_alloc_rxtx_dmactl_fields(struct device *dev, +                     struct regmap *map) +{ +    struct lpass_data *drvdata = dev_get_drvdata(dev); +    struct lpass_variant *v = drvdata->variant; +    struct lpaif_dmactl *rd_dmactl, *wr_dmactl; +    int rval;

+    rd_dmactl = devm_kzalloc(dev, sizeof(*rd_dmactl), GFP_KERNEL); +    if (rd_dmactl == NULL) +        return -ENOMEM;

+    wr_dmactl = devm_kzalloc(dev, sizeof(*wr_dmactl), GFP_KERNEL); +    if (wr_dmactl == NULL) +        return -ENOMEM;

+    drvdata->rxtx_rd_dmactl = rd_dmactl; +    drvdata->rxtx_wr_dmactl = wr_dmactl;

+    rval = devm_regmap_field_bulk_alloc(dev, map, &rd_dmactl->intf, +                        &v->rxtx_rdma_intf, LPASS_CDC_DMA_REGISTER_FIELDS_MAX); +    if (rval) +        return rval;

+    return devm_regmap_field_bulk_alloc(dev, map, &wr_dmactl->intf, +                        &v->rxtx_wrdma_intf, LPASS_CDC_DMA_REGISTER_FIELDS_MAX); +}

+static int lpass_platform_alloc_va_dmactl_fields(struct device *dev, +                     struct regmap *map) +{ +    struct lpass_data *drvdata = dev_get_drvdata(dev); +    struct lpass_variant *v = drvdata->variant; +    struct lpaif_dmactl *wr_dmactl;

+    wr_dmactl = devm_kzalloc(dev, sizeof(*wr_dmactl), GFP_KERNEL); +    if (wr_dmactl == NULL) +        return -ENOMEM;

+    drvdata->va_wr_dmactl = wr_dmactl; +    return devm_regmap_field_bulk_alloc(dev, map, &wr_dmactl->intf, +                        &v->va_wrdma_intf, LPASS_CDC_DMA_REGISTER_FIELDS_MAX); +}

static int lpass_platform_alloc_dmactl_fields(struct device *dev,                        struct regmap *map)   { @@ -123,25 +219,55 @@ static int lpass_platform_pcmops_open(struct snd_soc_component *component,           return dma_ch;       }   -    if (cpu_dai->driver->id == LPASS_DP_RX) { -        map = drvdata->hdmiif_map; -        drvdata->hdmi_substream[dma_ch] = substream; -    } else { +    switch (dai_id) { +    case MI2S_PRIMARY ... MI2S_QUINARY:           map = drvdata->lpaif_map;           drvdata->substream[dma_ch] = substream; +        break; +    case LPASS_DP_RX: +        map = drvdata->hdmiif_map; +        drvdata->hdmi_substream[dma_ch] = substream; +        break; +    case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9: +    case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8: +        map = drvdata->rxtx_lpaif_map; +        drvdata->rxtx_substream[dma_ch] = substream; +        break; +    case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX8: +        map = drvdata->va_lpaif_map; +        drvdata->va_substream[dma_ch] = substream; +        break; +    default: +        break;       }

data->dma_ch = dma_ch; -    ret = regmap_write(map, -            LPAIF_DMACTL_REG(v, dma_ch, dir, data->i2s_port), 0); -    if (ret) { -        dev_err(soc_runtime->dev, -            "error writing to rdmactl reg: %d\n", ret); -        return ret; +    switch (dai_id) { +    case MI2S_PRIMARY ... MI2S_QUINARY: +    case LPASS_DP_RX: +        ret = regmap_write(map, LPAIF_DMACTL_REG(v, dma_ch, dir, data->i2s_port), 0); +        if (ret) { +            kfree(data); +            dev_err(soc_runtime->dev, "error writing to rdmactl reg: %d\n", ret); +            return ret; +        } +        snd_soc_set_runtime_hwparams(substream, &lpass_platform_pcm_hardware); +        runtime->dma_bytes = lpass_platform_pcm_hardware.buffer_bytes_max; +        break; +    case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9: +    case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8: +        snd_soc_set_runtime_hwparams(substream, &lpass_platform_rxtx_hardware); +        runtime->dma_bytes = lpass_platform_rxtx_hardware.buffer_bytes_max; +        snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer); +        break; +    case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX8: +        snd_soc_set_runtime_hwparams(substream, &lpass_platform_va_hardware); +        runtime->dma_bytes = lpass_platform_va_hardware.buffer_bytes_max; +        snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer); +        break; +    default: +        break;       } -    snd_soc_set_runtime_hwparams(substream, &lpass_platform_pcm_hardware);

-    runtime->dma_bytes = lpass_platform_pcm_hardware.buffer_bytes_max;

ret = snd_pcm_hw_constraint_integer(runtime,               SNDRV_PCM_HW_PARAM_PERIODS);       if (ret < 0) { @@ -166,10 +292,25 @@ static int lpass_platform_pcmops_close(struct snd_soc_component *component,       unsigned int dai_id = cpu_dai->driver->id;         data = runtime->private_data; -    if (dai_id == LPASS_DP_RX) -        drvdata->hdmi_substream[data->dma_ch] = NULL; -    else

+    switch (dai_id) { +    case MI2S_PRIMARY ... MI2S_QUINARY:           drvdata->substream[data->dma_ch] = NULL; +        break; +    case LPASS_DP_RX: +        drvdata->hdmi_substream[data->dma_ch] = NULL; +        break; +    case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9: +    case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8: +        drvdata->rxtx_substream[data->dma_ch] = NULL; +        break; +    case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX8: +        drvdata->va_substream[data->dma_ch] = NULL; +        break; +    default: +        break; +    }

if (v->free_dma_channel)           v->free_dma_channel(drvdata, data->dma_ch, dai_id);   @@ -209,9 +350,25 @@ static void __lpass_get_lpaif_handle(struct snd_pcm_substream *substream,           l_dmactl = drvdata->hdmi_rd_dmactl;           l_map = drvdata->hdmiif_map;           break; +    case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9: +        l_id = pcm_data->dma_ch; +        l_dmactl = drvdata->rxtx_rd_dmactl; +        l_map = drvdata->rxtx_lpaif_map; +        break; +    case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8: +        l_id = pcm_data->dma_ch - v->rxtx_wrdma_channel_start; +        l_dmactl = drvdata->rxtx_wr_dmactl; +        l_map = drvdata->rxtx_lpaif_map; +        break; +    case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX8: +        l_id = pcm_data->dma_ch - v->va_wrdma_channel_start; +        l_dmactl = drvdata->va_wr_dmactl; +        l_map = drvdata->va_lpaif_map; +        break;       default:           break;       }

if (dmactl)           *dmactl = l_dmactl;       if (id) @@ -299,6 +456,10 @@ static int lpass_platform_pcmops_hw_params(struct snd_soc_component *component,           }             break; +    case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9: +    case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8: +    case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX0: +        break;       default:           dev_err(soc_runtime->dev, "%s: invalid  interface: %d\n", __func__, dai_id);           break; @@ -387,6 +548,9 @@ static int lpass_platform_pcmops_hw_free(struct snd_soc_component *component,       struct regmap *map;       unsigned int dai_id = cpu_dai->driver->id;   +    if (is_cdc_dma_port(dai_id))

simillar comment about bisectablity and this macro.

Okay. Will do accordingly.

...

+        return 0;

__lpass_get_lpaif_handle(substream, component, NULL, NULL, &map);       if (!map) {           dev_err(soc_runtime->dev, "failed to get dmactl handle\n"); @@ -449,6 +613,14 @@ static int lpass_platform_pcmops_prepare(struct snd_soc_component *component,           return ret;       }   +    if (is_cdc_dma_port(dai_id)) { +        ret = regmap_fields_write(dmactl->fifowm, id, LPAIF_DMACTL_FIFOWM_8); +        if (ret) { +            dev_err(soc_runtime->dev, "error writing fifowm field to dmactl reg: %d, id: %d\n", +                ret, id); +            return ret; +        } +    }       ret = regmap_fields_write(dmactl->enable, id, LPAIF_DMACTL_ENABLE_ON);       if (ret) {           dev_err(soc_runtime->dev, "error writing to rdmactl reg: %d\n", @@ -532,6 +704,35 @@ static int lpass_platform_pcmops_trigger(struct snd_soc_component *component,               val_mask = LPAIF_IRQ_ALL(ch);               val_irqen = LPAIF_IRQ_ALL(ch);               break; +        case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9: +        case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8: +            ret = regmap_fields_write(dmactl->dyncclk, id, LPAIF_DMACTL_DYNCLK_ON); +            if (ret) { +                dev_err(soc_runtime->dev, +                    "error writing to rdmactl reg field: %d\n", ret); +                return ret; +            } +            reg_irqclr = LPAIF_RXTX_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST); +            val_irqclr = LPAIF_IRQ_ALL(ch);

+            reg_irqen = LPAIF_RXTX_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST); +            val_mask = LPAIF_IRQ_ALL(ch); +            val_irqen = LPAIF_IRQ_ALL(ch); +            break; +        case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX8: +            ret = regmap_fields_write(dmactl->dyncclk, id, LPAIF_DMACTL_DYNCLK_ON); +            if (ret) { +                dev_err(soc_runtime->dev, +                    "error writing to rdmactl reg field: %d\n", ret); +                return ret; +            } +            reg_irqclr = LPAIF_VA_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST); +            val_irqclr = LPAIF_IRQ_ALL(ch);

+            reg_irqen = LPAIF_VA_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST); +            val_mask = LPAIF_IRQ_ALL(ch); +            val_irqen = LPAIF_IRQ_ALL(ch); +            break;           default:               dev_err(soc_runtime->dev, "%s: invalid %d interface\n", __func__, dai_id);               return -EINVAL; @@ -583,6 +784,37 @@ static int lpass_platform_pcmops_trigger(struct snd_soc_component *component,               val_mask = LPAIF_IRQ_ALL(ch);               val_irqen = 0;               break; +        case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9: +        case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8: +            ret = regmap_fields_write(dmactl->dyncclk, id, LPAIF_DMACTL_DYNCLK_OFF); +            if (ret) { +                dev_err(soc_runtime->dev, +                    "error writing to rdmactl reg field: %d\n", ret); +                return ret; +            }

+            reg_irqclr = LPAIF_RXTX_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST); +            val_irqclr = LPAIF_IRQ_ALL(ch);

+            reg_irqen = LPAIF_RXTX_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST); +            val_mask = LPAIF_IRQ_ALL(ch); +            val_irqen = LPAIF_IRQ_ALL(ch); +            break; +        case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX8: +            ret = regmap_fields_write(dmactl->dyncclk, id, LPAIF_DMACTL_DYNCLK_OFF); +            if (ret) { +                dev_err(soc_runtime->dev, +                    "error writing to rdmactl reg field: %d\n", ret); +                return ret; +            }

+            reg_irqclr = LPAIF_VA_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST); +            val_irqclr = LPAIF_IRQ_ALL(ch);

+            reg_irqen = LPAIF_VA_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST); +            val_mask = LPAIF_IRQ_ALL(ch); +            val_irqen = LPAIF_IRQ_ALL(ch); +            break;           default:               dev_err(soc_runtime->dev, "%s: invalid %d interface\n", __func__, dai_id);               return -EINVAL; @@ -642,6 +874,39 @@ static snd_pcm_uframes_t lpass_platform_pcmops_pointer(       return bytes_to_frames(substream->runtime, curr_addr - base_addr);   }   +static int lpass_platform_cdc_dma_mmap(struct snd_soc_component *component, +            struct snd_pcm_substream *substream, +            struct vm_area_struct *vma)

indentiation looks bit off. Please recheck this in all the other instances too.

Okay.

...

+{ +    struct snd_pcm_runtime *runtime = substream->runtime; +    unsigned long size, offset;

+    vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); +    size = vma->vm_end - vma->vm_start; +    offset = vma->vm_pgoff << PAGE_SHIFT; +    return io_remap_pfn_range(vma, vma->vm_start, +            (runtime->dma_addr + offset) >> PAGE_SHIFT, +            size, vma->vm_page_prot);

+}

+static int lpass_platform_pcmops_mmap(struct snd_soc_component *component, +                      struct snd_pcm_substream *substream, +                      struct vm_area_struct *vma) +{ +    struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream); +    struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_runtime, 0); +    unsigned int dai_id = cpu_dai->driver->id; +    int err;

+    if (is_cdc_dma_port(dai_id)) +        err = lpass_platform_cdc_dma_mmap(component, substream, vma); +    else +        err = snd_pcm_lib_default_mmap(substream, vma);

+    return err; +}

static irqreturn_t lpass_dma_interrupt_handler(               struct snd_pcm_substream *substream,               struct lpass_data *drvdata, @@ -674,6 +939,17 @@ static irqreturn_t lpass_dma_interrupt_handler(           reg = LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST);           val = 0;       break; +    case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9: +    case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8: +        map = drvdata->rxtx_lpaif_map; +        reg = LPAIF_RXTX_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST); +        val = 0; +    break; +    case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX8: +        map = drvdata->va_lpaif_map; +        reg = LPAIF_VA_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST); +        val = 0; +    break;       default:       dev_err(soc_runtime->dev, "%s: invalid  %d interface\n", __func__, dai_id);       return -EINVAL; @@ -781,18 +1057,122 @@ static irqreturn_t lpass_platform_hdmiif_irq(int irq, void *data)                   return rv;           }       } +    return IRQ_HANDLED; +}

+static irqreturn_t lpass_platform_rxtxif_irq(int irq, void *data) +{ +    struct lpass_data *drvdata = data; +    struct lpass_variant *v = drvdata->variant; +    unsigned int irqs; +    int rv, chan;

+    rv = regmap_read(drvdata->rxtx_lpaif_map, +            LPAIF_RXTX_IRQSTAT_REG(v, LPAIF_IRQ_PORT_HOST), &irqs); +    if (rv) +        return IRQ_NONE; +    /* Handle per channel interrupts */ +    for (chan = 0; chan < LPASS_MAX_CDC_DMA_CHANNELS; chan++) { +        if (irqs & LPAIF_IRQ_ALL(chan) && drvdata->rxtx_substream[chan]) { +            rv = lpass_dma_interrupt_handler( +                        drvdata->rxtx_substream[chan], +                        drvdata, chan, irqs); +            if (rv != IRQ_HANDLED) +                return rv; +        } +    }         return IRQ_HANDLED;   }   +static irqreturn_t lpass_platform_vaif_irq(int irq, void *data) +{ +    struct lpass_data *drvdata = data; +    struct lpass_variant *v = drvdata->variant; +    unsigned int irqs; +    int rv, chan;

+    rv = regmap_read(drvdata->va_lpaif_map, +            LPAIF_VA_IRQSTAT_REG(v, LPAIF_IRQ_PORT_HOST), &irqs); +    if (rv) +        return IRQ_NONE; +    /* Handle per channel interrupts */ +    for (chan = 0; chan < LPASS_MAX_VA_CDC_DMA_CHANNELS; chan++) { +        if (irqs & LPAIF_IRQ_ALL(chan) && drvdata->va_substream[chan]) { +            rv = lpass_dma_interrupt_handler( +                        drvdata->va_substream[chan], +                        drvdata, chan, irqs); +            if (rv != IRQ_HANDLED) +                return rv; +        } +    } +    return IRQ_HANDLED; +}

+static int lpass_platform_prealloc_cdc_dma_buffer(struct snd_soc_component *component, +            struct snd_pcm *pcm, int dai_id) +{ +    struct lpass_data *drvdata = snd_soc_component_get_drvdata(component); +    struct snd_pcm_substream *substream; +    struct snd_dma_buffer *buf; +    int ret;

+    if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream) +        substream = pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream; +    else +        substream = pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream;

+    ret = dma_coerce_mask_and_coherent(pcm->card->dev, DMA_BIT_MASK(64)); +    if (ret) +        return ret;

+    buf = &substream->dma_buffer; +    buf->dev.dev = pcm->card->dev; +    buf->private_data = NULL;

+    /* Assign Codec DMA buffer pointers */ +    buf->dev.type = SNDRV_DMA_TYPE_CONTINUOUS;

+    switch (dai_id) { +    case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9: +        buf->bytes = lpass_platform_rxtx_hardware.buffer_bytes_max; +        buf->addr = drvdata->rxtx_cdc_dma_lpm_buf; +        break; +    case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8: +        buf->bytes = lpass_platform_rxtx_hardware.buffer_bytes_max; +        buf->addr = drvdata->rxtx_cdc_dma_lpm_buf + LPASS_RXTX_CDC_DMA_LPM_BUFF_SIZE; +        break; +    case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX8: +        buf->bytes = lpass_platform_va_hardware.buffer_bytes_max; +        buf->addr = drvdata->va_cdc_dma_lpm_buf; +        break; +    default: +        break; +    }

+    buf->area = (unsigned char * __force)ioremap(buf->addr, buf->bytes);

+    return 0; +}

static int lpass_platform_pcm_new(struct snd_soc_component *component,                     struct snd_soc_pcm_runtime *soc_runtime)   {       struct snd_pcm *pcm = soc_runtime->pcm; +    struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_runtime, 0); +    unsigned int dai_id = cpu_dai->driver->id;

size_t size = lpass_platform_pcm_hardware.buffer_bytes_max;   -    return snd_pcm_set_fixed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, -                        component->dev, size); +    /* +     * Lpass codec dma can access only lpass lpm hardware memory. +     * ioremap is for HLOS to access hardware memory. +     */ +    if (is_cdc_dma_port(dai_id)) +        return lpass_platform_prealloc_cdc_dma_buffer(component, pcm, dai_id); +    else +        return snd_pcm_set_fixed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, +                        component->dev, size);   }     static int lpass_platform_pcmops_suspend(struct snd_soc_component *component) @@ -827,6 +1207,31 @@ static int lpass_platform_pcmops_resume(struct snd_soc_component *component)       return regcache_sync(map);   }   +int lpass_platform_copy(struct snd_soc_component *component, +            struct snd_pcm_substream *substream, int channel, +            unsigned long pos, void __user *buf, unsigned long bytes)

static function?

Okay.

...

+{ +    struct snd_pcm_runtime *rt = substream->runtime; +    unsigned int dai_id = component->id; +    int ret = 0;

+    unsigned char *dma_buf = rt->dma_area + pos + +                channel * (rt->dma_bytes / rt->channels);

+    if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { +        if (is_cdc_dma_port(dai_id)) +            ret = copy_from_user_toio(dma_buf, buf, bytes);

May be a typecast (void __force *)dma_buf  here like other parts of the code

Okay.

...

+        else +            ret = copy_from_user((void __force *)dma_buf, buf, bytes); +    } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { +        if (is_cdc_dma_port(dai_id)) +            ret = copy_to_user_fromio(buf, dma_buf, bytes); +        else +            ret = copy_to_user(buf, dma_buf, bytes); +    }

+    return ret; +}     static const struct snd_soc_component_driver lpass_component_driver = {       .name        = DRV_NAME, @@ -837,9 +1242,11 @@ static const struct snd_soc_component_driver lpass_component_driver = {       .prepare    = lpass_platform_pcmops_prepare,       .trigger    = lpass_platform_pcmops_trigger,       .pointer    = lpass_platform_pcmops_pointer, +    .mmap        = lpass_platform_pcmops_mmap,       .pcm_construct    = lpass_platform_pcm_new,       .suspend        = lpass_platform_pcmops_suspend,       .resume            = lpass_platform_pcmops_resume, +    .copy_user        = lpass_platform_copy,     };   @@ -877,6 +1284,60 @@ int asoc_qcom_lpass_platform_register(struct platform_device *pdev)           return ret;       }   +    if (drvdata->codec_dma_enable) { +        ret = regmap_write(drvdata->rxtx_lpaif_map, +            LPAIF_RXTX_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST), 0x0); +        if (ret) { +            dev_err(&pdev->dev, "error writing to rxtx irqen reg: %d\n", ret); +            return ret; +        } +        ret = regmap_write(drvdata->va_lpaif_map, +            LPAIF_VA_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST), 0x0); +        if (ret) { +            dev_err(&pdev->dev, "error writing to rxtx irqen reg: %d\n", ret); +            return ret; +        } +        drvdata->rxtxif_irq = platform_get_irq_byname(pdev, "lpass-irq-rxtxif"); +        if (drvdata->rxtxif_irq < 0) +            return -ENODEV;

+        ret = devm_request_irq(&pdev->dev, drvdata->rxtxif_irq, +                lpass_platform_rxtxif_irq, IRQF_TRIGGER_RISING, +                "lpass-irq-rxtxif", drvdata); +        if (ret) { +            dev_err(&pdev->dev, "rxtx irq request failed: %d\n", ret); +            return ret; +        }

+        ret = lpass_platform_alloc_rxtx_dmactl_fields(&pdev->dev, +                         drvdata->rxtx_lpaif_map); +        if (ret) { +            dev_err(&pdev->dev, +                "error initializing rxtx dmactl fields: %d\n", ret); +            return ret; +        }

+        drvdata->vaif_irq = platform_get_irq_byname(pdev, "lpass-irq-vaif"); +        if (drvdata->vaif_irq < 0) +            return -ENODEV;

+        ret = devm_request_irq(&pdev->dev, drvdata->vaif_irq, +                lpass_platform_vaif_irq, IRQF_TRIGGER_RISING, +                "lpass-irq-vaif", drvdata); +        if (ret) { +            dev_err(&pdev->dev, "va irq request failed: %d\n", ret); +            return ret; +        }

+        ret = lpass_platform_alloc_va_dmactl_fields(&pdev->dev, +                         drvdata->va_lpaif_map); +        if (ret) { +            dev_err(&pdev->dev, +                "error initializing va dmactl fields: %d\n", ret); +            return ret; +        } +    }

if (drvdata->hdmi_port_enable) {           drvdata->hdmiif_irq = platform_get_irq_byname(pdev, "lpass-irq-hdmi");           if (drvdata->hdmiif_irq < 0) diff --git a/sound/soc/qcom/lpass.h b/sound/soc/qcom/lpass.h index 413cead..43f7ff4 100644 --- a/sound/soc/qcom/lpass.h +++ b/sound/soc/qcom/lpass.h @@ -38,6 +38,29 @@               return -EINVAL;         \       } while (0)   +static inline bool is_cdc_dma_port(int dai_id) +{ +    switch (dai_id) { +    case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9: +    case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8: +    case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX8: +        return true; +    default: +        return false; +    } +}

+static inline bool is_rxtx_cdc_dma_port(int dai_id) +{ +    switch (dai_id) { +    case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9: +    case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8: +        return true; +    default: +        return false; +    } +}

struct lpaif_i2sctl {       struct regmap_field *loopback;       struct regmap_field *spken;

On 02/12/2021 15:43, Srinivasa Rao Mandadapu wrote:

From: Srinivasa Rao Mandadapu srivasam@codeaurora.org

Update regmap configuration for supporting headset playback and capture and DMIC capture using codec dma interface

Signed-off-by: Srinivasa Rao Mandadapu srivasam@codeaurora.org Co-developed-by: Venkata Prasad Potturu potturu@codeaurora.org Signed-off-by: Venkata Prasad Potturu potturu@codeaurora.org

LGTM,

Reviewed-by: Srinivas Kandagatla srinivas.kandagatla@linaro.org

---

sound/soc/qcom/lpass-cpu.c | 185 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 185 insertions(+)

diff --git a/sound/soc/qcom/lpass-cpu.c b/sound/soc/qcom/lpass-cpu.c index 81818f0..a5a46bc 100644 --- a/sound/soc/qcom/lpass-cpu.c +++ b/sound/soc/qcom/lpass-cpu.c @@ -28,6 +28,8 @@ #define LPASS_CPU_I2S_SD2_3_MASK GENMASK(3, 2) #define LPASS_CPU_I2S_SD0_1_2_MASK GENMASK(2, 0) #define LPASS_CPU_I2S_SD0_1_2_3_MASK GENMASK(3, 0) +#define LPASS_REG_READ 1 +#define LPASS_REG_WRITE 0

/*

• Channel maps for Quad channel playbacks on MI2S Secondary

@@ -798,6 +800,189 @@ static struct regmap_config lpass_hdmi_regmap_config = { .cache_type = REGCACHE_FLAT, };

+static bool __lpass_rxtx_regmap_accessible(struct device *dev, unsigned int reg, bool rw) +{

• struct lpass_data *drvdata = dev_get_drvdata(dev);
• struct lpass_variant *v = drvdata->variant;
• int i;
• for (i = 0; i < v->rxtx_irq_ports; ++i) {

• if (reg == LPAIF_RXTX_IRQCLEAR_REG(v, i))
  

• 	return true;
  

• if (reg == LPAIF_RXTX_IRQEN_REG(v, i))
  

• 	return true;
  

• if (reg == LPAIF_RXTX_IRQSTAT_REG(v, i))
  

• 	return true;
  

• }
• for (i = 0; i < v->rxtx_rdma_channels; ++i) {

• if (reg == LPAIF_CDC_RXTX_RDMACTL_REG(v, i, LPASS_CDC_DMA_RX0))
  

• 	return true;
  

• if (reg == LPAIF_CDC_RXTX_RDMABASE_REG(v, i, LPASS_CDC_DMA_RX0))
  

• 	return true;
  

• if (reg == LPAIF_CDC_RXTX_RDMABUFF_REG(v, i, LPASS_CDC_DMA_RX0))
  

• 	return true;
  

• if (rw == LPASS_REG_READ) {
  

• 	if (reg == LPAIF_CDC_RXTX_RDMACURR_REG(v, i, LPASS_CDC_DMA_RX0))
  

• 		return true;
  

• }
  

• if (reg == LPAIF_CDC_RXTX_RDMAPER_REG(v, i, LPASS_CDC_DMA_RX0))
  

• 	return true;
  

• if (reg == LPAIF_CDC_RXTX_RDMA_INTF_REG(v, i, LPASS_CDC_DMA_RX0))
  

• 	return true;
  

• }
• for (i = 0; i < v->rxtx_wrdma_channels; ++i) {

• if (reg == LPAIF_CDC_RXTX_WRDMACTL_REG(v, i + v->rxtx_wrdma_channel_start,
  

• 					LPASS_CDC_DMA_TX3))
  

• 	return true;
  

• if (reg == LPAIF_CDC_RXTX_WRDMABASE_REG(v, i + v->rxtx_wrdma_channel_start,
  

• 					LPASS_CDC_DMA_TX3))
  

• 	return true;
  

• if (reg == LPAIF_CDC_RXTX_WRDMABUFF_REG(v, i + v->rxtx_wrdma_channel_start,
  

• 					LPASS_CDC_DMA_TX3))
  

• 	return true;
  

• if (rw == LPASS_REG_READ) {
  

• 	if (reg == LPAIF_CDC_RXTX_WRDMACURR_REG(v, i, LPASS_CDC_DMA_RX0))
  

• 		return true;
  

• }
  

• if (reg == LPAIF_CDC_RXTX_WRDMAPER_REG(v, i + v->rxtx_wrdma_channel_start,
  

• 					LPASS_CDC_DMA_TX3))
  

• 	return true;
  

• if (reg == LPAIF_CDC_RXTX_WRDMA_INTF_REG(v, i + v->rxtx_wrdma_channel_start,
  

• 					LPASS_CDC_DMA_TX3))
  

• 	return true;
  

• }
• return false;

+}

+static bool lpass_rxtx_regmap_writeable(struct device *dev, unsigned int reg) +{

• return __lpass_rxtx_regmap_accessible(dev, reg, LPASS_REG_WRITE);

+}

+static bool lpass_rxtx_regmap_readable(struct device *dev, unsigned int reg) +{

• return __lpass_rxtx_regmap_accessible(dev, reg, LPASS_REG_READ);

+}

+static bool lpass_rxtx_regmap_volatile(struct device *dev, unsigned int reg) +{

• struct lpass_data *drvdata = dev_get_drvdata(dev);
• struct lpass_variant *v = drvdata->variant;
• int i;
• for (i = 0; i < v->rxtx_irq_ports; ++i) {

• if (reg == LPAIF_RXTX_IRQCLEAR_REG(v, i))
  

• 	return true;
  

• if (reg == LPAIF_RXTX_IRQSTAT_REG(v, i))
  

• 	return true;
  

• }
• for (i = 0; i < v->rxtx_rdma_channels; ++i)

• if (reg == LPAIF_CDC_RXTX_RDMACURR_REG(v, i, LPASS_CDC_DMA_RX0))
  

• 	return true;
  

• for (i = 0; i < v->rxtx_wrdma_channels; ++i)

• if (reg == LPAIF_CDC_RXTX_WRDMACURR_REG(v, i + v->rxtx_wrdma_channel_start,
  

• 					LPASS_CDC_DMA_TX3))
  

• 	return true;
  

• return false;

+}

+static bool __lpass_va_regmap_accessible(struct device *dev, unsigned int reg, bool rw) +{

• struct lpass_data *drvdata = dev_get_drvdata(dev);
• struct lpass_variant *v = drvdata->variant;
• int i;
• for (i = 0; i < v->va_irq_ports; ++i) {

• if (reg == LPAIF_VA_IRQCLEAR_REG(v, i))
  

• 	return true;
  

• if (reg == LPAIF_VA_IRQEN_REG(v, i))
  

• 	return true;
  

• if (reg == LPAIF_VA_IRQSTAT_REG(v, i))
  

• 	return true;
  

• }
• for (i = 0; i < v->va_wrdma_channels; ++i) {

• if (reg == LPAIF_CDC_VA_WRDMACTL_REG(v, i + v->va_wrdma_channel_start,
  

• 					LPASS_CDC_DMA_VA_TX0))
  

• 	return true;
  

• if (reg == LPAIF_CDC_VA_WRDMABASE_REG(v, i + v->va_wrdma_channel_start,
  

• 					LPASS_CDC_DMA_VA_TX0))
  

• 	return true;
  

• if (reg == LPAIF_CDC_VA_WRDMABUFF_REG(v, i + v->va_wrdma_channel_start,
  

• 					LPASS_CDC_DMA_VA_TX0))
  

• 	return true;
  

• if (rw == LPASS_REG_READ) {
  

• 	if (reg == LPAIF_CDC_VA_WRDMACURR_REG(v, i + v->va_wrdma_channel_start,
  

• 					LPASS_CDC_DMA_VA_TX0))
  

• 		return true;
  

• }
  

• if (reg == LPAIF_CDC_VA_WRDMAPER_REG(v, i + v->va_wrdma_channel_start,
  

• 					LPASS_CDC_DMA_VA_TX0))
  

• 	return true;
  

• if (reg == LPAIF_CDC_VA_WRDMA_INTF_REG(v, i + v->va_wrdma_channel_start,
  

• 					LPASS_CDC_DMA_VA_TX0))
  

• 	return true;
  

• }
• return false;

+}

+static bool lpass_va_regmap_writeable(struct device *dev, unsigned int reg) +{

• return __lpass_va_regmap_accessible(dev, reg, LPASS_REG_WRITE);

+}

+static bool lpass_va_regmap_readable(struct device *dev, unsigned int reg) +{

• return __lpass_va_regmap_accessible(dev, reg, LPASS_REG_READ);

+}

+static bool lpass_va_regmap_volatile(struct device *dev, unsigned int reg) +{

• struct lpass_data *drvdata = dev_get_drvdata(dev);
• struct lpass_variant *v = drvdata->variant;
• int i;
• for (i = 0; i < v->va_irq_ports; ++i) {

• if (reg == LPAIF_VA_IRQCLEAR_REG(v, i))
  

• 	return true;
  

• if (reg == LPAIF_VA_IRQSTAT_REG(v, i))
  

• 	return true;
  

• }
• for (i = 0; i < v->va_wrdma_channels; ++i) {

• if (reg == LPAIF_CDC_VA_WRDMACURR_REG(v, i + v->va_wrdma_channel_start,
  

• 					LPASS_CDC_DMA_VA_TX0))
  

• 	return true;
  

• }
• return false;

+}

+static struct regmap_config lpass_rxtx_regmap_config = {

• .reg_bits = 32,
• .reg_stride = 4,
• .val_bits = 32,
• .writeable_reg = lpass_rxtx_regmap_writeable,
• .readable_reg = lpass_rxtx_regmap_readable,
• .volatile_reg = lpass_rxtx_regmap_volatile,
• .cache_type = REGCACHE_FLAT,

+};

+static struct regmap_config lpass_va_regmap_config = {

• .reg_bits = 32,
• .reg_stride = 4,
• .val_bits = 32,
• .writeable_reg = lpass_va_regmap_writeable,
• .readable_reg = lpass_va_regmap_readable,
• .volatile_reg = lpass_va_regmap_volatile,
• .cache_type = REGCACHE_FLAT,

+};

• static unsigned int of_lpass_cpu_parse_sd_lines(struct device *dev, struct device_node *node, const char *name)

On 02/12/2021 15:43, Srinivasa Rao Mandadapu wrote:

From: Srinivasa Rao Mandadapu srivasam@codeaurora.org

Add platform driver for configuring sc7280 lpass core I2S and DMA configuration to support playback & capture to external codecs connected over secondary MI2S interface and soundwire interface.

Signed-off-by: Srinivasa Rao Mandadapu srivasam@codeaurora.org Co-developed-by: Venkata Prasad Potturu potturu@codeaurora.org Signed-off-by: Venkata Prasad Potturu potturu@codeaurora.org

overall the patch LGTM, but some indentation seems to be off once that are addressed you can add my

Reviewed-by: Srinivas Kandagatla srinivas.kandagatla@linaro.org

---

sound/soc/qcom/lpass-sc7280.c | 441 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 441 insertions(+) create mode 100644 sound/soc/qcom/lpass-sc7280.c

diff --git a/sound/soc/qcom/lpass-sc7280.c b/sound/soc/qcom/lpass-sc7280.c new file mode 100644 index 0000000..302a112 --- /dev/null +++ b/sound/soc/qcom/lpass-sc7280.c @@ -0,0 +1,441 @@ +// SPDX-License-Identifier: GPL-2.0-only +/*

• • Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
• • lpass-sc7180.c -- ALSA SoC platform-machine driver for QTi LPASS
• */

+#include <linux/module.h> +#include <sound/pcm.h> +#include <sound/soc.h> +#include <linux/pm_runtime.h>

+#include <dt-bindings/sound/sc7180-lpass.h>

+#include "lpass-lpaif-reg.h" +#include "lpass.h"

+static struct snd_soc_dai_driver sc7280_lpass_cpu_dai_driver[] = {

• {

• .id = MI2S_PRIMARY,
  

• .name = "Primary MI2S",
  

• .playback = {
  

• 	.stream_name = "Primary Playback",
  

• 	.formats	= SNDRV_PCM_FMTBIT_S16,
  

• 	.rates = SNDRV_PCM_RATE_48000,
  

• 	.rate_min	= 48000,
  

• 	.rate_max	= 48000,
  

• 	.channels_min	= 2,
  

• 	.channels_max	= 2,
  

• },
  

• .capture = {
  

• 	.stream_name = "Primary Capture",
  

• 	.formats = SNDRV_PCM_FMTBIT_S16 |
  

• 		SNDRV_PCM_FMTBIT_S32,
  

• 	.rates = SNDRV_PCM_RATE_48000,
  

• 	.rate_min	= 48000,
  

• 	.rate_max	= 48000,
  

• 	.channels_min	= 2,
  

• 	.channels_max	= 2,
  

• },
  

• .probe	= &asoc_qcom_lpass_cpu_dai_probe,
  

• .ops    = &asoc_qcom_lpass_cpu_dai_ops,
  

• }, {

• .id = MI2S_SECONDARY,
  

• .name = "Secondary MI2S",
  

• .playback = {
  

• 	.stream_name = "Secondary MI2S Playback",
  

• 	.formats = SNDRV_PCM_FMTBIT_S16,
  

• 	.rates = SNDRV_PCM_RATE_48000,
  

• 	.rate_min	= 48000,
  

• 	.rate_max	= 48000,
  

• 	.channels_min	= 2,
  

• 	.channels_max	= 2,
  

• },
  

• .probe	= &asoc_qcom_lpass_cpu_dai_probe,
  

• .ops	= &asoc_qcom_lpass_cpu_dai_ops,
  

• }, {

• .id = LPASS_DP_RX,
  

• .name = "Hdmi",
  

• .playback = {
  

• 	.stream_name = "DP Playback",
  

• 	.formats = SNDRV_PCM_FMTBIT_S24,
  

• 	.rates = SNDRV_PCM_RATE_48000,
  

• 	.rate_min	= 48000,
  

• 	.rate_max	= 48000,
  

• 	.channels_min	= 2,
  

• 	.channels_max	= 2,
  

• },
  

• .ops	= &asoc_qcom_lpass_hdmi_dai_ops,
  

• }, {

• .id = LPASS_CDC_DMA_RX0,
  

• .name = "CDC DMA RX",
  

• .playback = {
  

• 	.stream_name = "WCD Playback",
  

• 	.formats = SNDRV_PCM_FMTBIT_S16,
  

• 	.rates = SNDRV_PCM_RATE_48000,
  

• 	.rate_min	= 48000,
  

• 	.rate_max	= 48000,
  

• 	.channels_min	= 2,
  

• 	.channels_max	= 2,
  

• },
  

• .ops	= &asoc_qcom_lpass_cdc_dma_dai_ops,
  

• }, {

• .id = LPASS_CDC_DMA_TX3,
  

• .name = "CDC DMA TX",
  

• .capture = {
  

• 	.stream_name = "WCD Capture",
  

• 	.formats = SNDRV_PCM_FMTBIT_S16,
  

• 	.rates = SNDRV_PCM_RATE_48000,
  

• 	.rate_min	= 48000,
  

• 	.rate_max	= 48000,
  

• 	.channels_min	= 1,
  

• 	.channels_max	= 2,
  

• },
  

• .ops	= &asoc_qcom_lpass_cdc_dma_dai_ops,
  

• }, {

• .id = LPASS_CDC_DMA_VA_TX0,
  

• .name = "CDC DMA VA",
  

• .capture = {
  

• 	.stream_name = "DMIC Capture",
  

• 	.formats = SNDRV_PCM_FMTBIT_S16,
  

• 	.rates = SNDRV_PCM_RATE_48000,
  

• 	.rate_min	= 48000,
  

• 	.rate_max	= 48000,
  

• 	.channels_min	= 2,
  

• 	.channels_max	= 4,
  

• },
  

• .ops	= &asoc_qcom_lpass_cdc_dma_dai_ops,
  

• },

+};

+static int sc7280_lpass_alloc_dma_channel(struct lpass_data *drvdata,

• 			  int direction, unsigned int dai_id)
  

+{

• struct lpass_variant *v = drvdata->variant;
• int chan = 0;
• switch (dai_id) {
• case MI2S_PRIMARY ... MI2S_QUINARY:

• if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
  

• 	chan = find_first_zero_bit(&drvdata->dma_ch_bit_map,
  

• 							v->rdma_channels);
  

Indentation is really off, take some time to fix such instances.

• 	if (chan >= v->rdma_channels)
  

• 		return -EBUSY;
  

• } else {
  

• 	chan = find_next_zero_bit(&drvdata->dma_ch_bit_map,
  

• 					v->wrdma_channel_start +
  

• 					v->wrdma_channels,
  

• 					v->wrdma_channel_start);
  

• 	if (chan >= v->wrdma_channel_start + v->wrdma_channels)
  

• 		return -EBUSY;
  

• }
  

• set_bit(chan, &drvdata->dma_ch_bit_map);
  

• break;
  

• case LPASS_DP_RX:

• chan = find_first_zero_bit(&drvdata->hdmi_dma_ch_bit_map,
  

• 						v->hdmi_rdma_channels);
  

• if (chan >= v->hdmi_rdma_channels)
  

• 	return -EBUSY;
  

• set_bit(chan, &drvdata->hdmi_dma_ch_bit_map);
  

• break;
  

• case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9:

• chan = find_first_zero_bit(&drvdata->rxtx_dma_ch_bit_map,
  

• 							v->rxtx_rdma_channels);
  

• if (chan >= v->rxtx_rdma_channels)
  

• 	return -EBUSY;
  

• break;
  

• case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8:

• chan = find_next_zero_bit(&drvdata->rxtx_dma_ch_bit_map,
  

• 				v->rxtx_wrdma_channel_start +
  

• 				v->rxtx_wrdma_channels,
  

• 				v->rxtx_wrdma_channel_start);
  

• if (chan >= v->rxtx_wrdma_channel_start + v->rxtx_wrdma_channels)
  

• 	return -EBUSY;
  

• set_bit(chan, &drvdata->rxtx_dma_ch_bit_map);
  

• break;
  

• case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX8:

• chan = find_next_zero_bit(&drvdata->va_dma_ch_bit_map,
  

• 				v->va_wrdma_channel_start +
  

• 				v->va_wrdma_channels,
  

• 				v->va_wrdma_channel_start);
  

• if (chan >= v->va_wrdma_channel_start + v->va_wrdma_channels)
  

• 	return -EBUSY;
  

• set_bit(chan, &drvdata->va_dma_ch_bit_map);
  

• break;
  

• default:

• break;
  

• }
• return chan;

+}

+static int sc7280_lpass_free_dma_channel(struct lpass_data *drvdata, int chan, unsigned int dai_id) +{

• switch (dai_id) {
• case MI2S_PRIMARY ... MI2S_QUINARY:

• clear_bit(chan, &drvdata->dma_ch_bit_map);
  

• break;
  

• case LPASS_DP_RX:

• clear_bit(chan, &drvdata->hdmi_dma_ch_bit_map);
  

• break;
  

• case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9:
• case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8:

• clear_bit(chan, &drvdata->rxtx_dma_ch_bit_map);
  

• break;
  

• case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX8:

• clear_bit(chan, &drvdata->va_dma_ch_bit_map);
  

• break;
  

• default:

• break;
  

• }
• return 0;

+}

+static int sc7280_lpass_init(struct platform_device *pdev) +{

• struct lpass_data *drvdata = platform_get_drvdata(pdev);
• struct lpass_variant *variant = drvdata->variant;
• struct device *dev = &pdev->dev;
• drvdata->clks = devm_kcalloc(dev, variant->num_clks,

• 			sizeof(*drvdata->clks), GFP_KERNEL);
  

• if (!drvdata->clks)

• return -ENOMEM;
  

• drvdata->num_clks = variant->num_clks;
• drvdata->aon_cc_audio_hm_h = devm_clk_get(dev, "lpass_aon_cc_audio_hm_h_clk");
• if (IS_ERR(drvdata->aon_cc_audio_hm_h))

• return PTR_ERR(drvdata->aon_cc_audio_hm_h);
  

• drvdata->core_cc_sysnoc_mport_core = devm_clk_get(dev,

• 			"lpass_core_cc_sysnoc_mport_core_clk");
  

• if (IS_ERR(drvdata->core_cc_sysnoc_mport_core))

• return PTR_ERR(drvdata->core_cc_sysnoc_mport_core);
  

• clk_prepare_enable(drvdata->aon_cc_audio_hm_h);
• clk_prepare_enable(drvdata->core_cc_sysnoc_mport_core);
• return 0;

+}

+static int sc7280_lpass_exit(struct platform_device *pdev) +{

• struct lpass_data *drvdata = platform_get_drvdata(pdev);
• clk_disable_unprepare(drvdata->core_cc_sysnoc_mport_core);
• clk_disable_unprepare(drvdata->aon_cc_audio_hm_h);
• return 0;

+}

+static struct lpass_variant sc7280_data = {

• .i2sctrl_reg_base = 0x1000,
• .i2sctrl_reg_stride = 0x1000,
• .i2s_ports = 3,
• .irq_reg_base = 0x9000,
• .irq_reg_stride = 0x1000,
• .irq_ports = 3,
• .rdma_reg_base = 0xC000,
• .rdma_reg_stride = 0x1000,
• .rdma_channels = 5,
• .rxtx_rdma_reg_base = 0xC000,
• .rxtx_rdma_reg_stride = 0x1000,
• .rxtx_rdma_channels = 8,
• .hdmi_rdma_reg_base = 0x64000,
• .hdmi_rdma_reg_stride = 0x1000,
• .hdmi_rdma_channels = 4,
• .dmactl_audif_start = 1,
• .wrdma_reg_base = 0x18000,
• .wrdma_reg_stride = 0x1000,
• .wrdma_channel_start = 5,
• .wrdma_channels = 4,
• .rxtx_irq_reg_base = 0x9000,
• .rxtx_irq_reg_stride = 0x1000,
• .rxtx_irq_ports = 3,
• .rxtx_wrdma_reg_base = 0x18000,
• .rxtx_wrdma_reg_stride = 0x1000,
• .rxtx_wrdma_channel_start = 5,
• .rxtx_wrdma_channels = 6,
• .va_wrdma_reg_base = 0x18000,
• .va_wrdma_reg_stride = 0x1000,
• .va_wrdma_channel_start = 5,
• .va_wrdma_channels = 3,
• .va_irq_reg_base = 0x9000,
• .va_irq_reg_stride = 0x1000,
• .va_irq_ports = 3,
• .loopback = REG_FIELD_ID(0x1000, 17, 17, 3, 0x1000),
• .spken = REG_FIELD_ID(0x1000, 16, 16, 3, 0x1000),
• .spkmode = REG_FIELD_ID(0x1000, 11, 15, 3, 0x1000),
• .spkmono = REG_FIELD_ID(0x1000, 10, 10, 3, 0x1000),
• .micen = REG_FIELD_ID(0x1000, 9, 9, 3, 0x1000),
• .micmode = REG_FIELD_ID(0x1000, 4, 8, 3, 0x1000),
• .micmono = REG_FIELD_ID(0x1000, 3, 3, 3, 0x1000),
• .wssrc = REG_FIELD_ID(0x1000, 2, 2, 3, 0x1000),
• .bitwidth = REG_FIELD_ID(0x1000, 0, 1, 3, 0x1000),
• .rdma_dyncclk = REG_FIELD_ID(0xC000, 21, 21, 5, 0x1000),
• .rdma_bursten = REG_FIELD_ID(0xC000, 20, 20, 5, 0x1000),
• .rdma_wpscnt = REG_FIELD_ID(0xC000, 16, 19, 5, 0x1000),
• .rdma_intf = REG_FIELD_ID(0xC000, 12, 15, 5, 0x1000),
• .rdma_fifowm = REG_FIELD_ID(0xC000, 1, 5, 5, 0x1000),
• .rdma_enable = REG_FIELD_ID(0xC000, 0, 0, 5, 0x1000),
• .wrdma_dyncclk = REG_FIELD_ID(0x18000, 22, 22, 4, 0x1000),
• .wrdma_bursten = REG_FIELD_ID(0x18000, 21, 21, 4, 0x1000),
• .wrdma_wpscnt = REG_FIELD_ID(0x18000, 17, 20, 4, 0x1000),
• .wrdma_intf = REG_FIELD_ID(0x18000, 12, 16, 4, 0x1000),
• .wrdma_fifowm = REG_FIELD_ID(0x18000, 1, 5, 4, 0x1000),
• .wrdma_enable = REG_FIELD_ID(0x18000, 0, 0, 4, 0x1000),
• .rxtx_rdma_enable = REG_FIELD_ID(0xC000, 0, 0, 7, 0x1000),
• .rxtx_rdma_fifowm = REG_FIELD_ID(0xC000, 1, 11, 7, 0x1000),
• .rxtx_rdma_intf = REG_FIELD_ID(0xC000, 12, 15, 7, 0x1000),
• .rxtx_rdma_wpscnt = REG_FIELD_ID(0xC000, 16, 19, 7, 0x1000),
• .rxtx_rdma_bursten = REG_FIELD_ID(0xC000, 20, 20, 7, 0x1000),
• .rxtx_rdma_dyncclk = REG_FIELD_ID(0xC000, 21, 21, 7, 0x1000),
• .rxtx_rdma_codec_ch = REG_FIELD_ID(0xC050, 0, 7, 7, 0x1000),
• .rxtx_rdma_codec_intf = REG_FIELD_ID(0xC050, 16, 19, 7, 0x1000),
• .rxtx_rdma_codec_fs_delay = REG_FIELD_ID(0xC050, 21, 24, 7, 0x1000),
• .rxtx_rdma_codec_fs_sel = REG_FIELD_ID(0xC050, 25, 27, 7, 0x1000),
• .rxtx_rdma_codec_pack = REG_FIELD_ID(0xC050, 29, 29, 5, 0x1000),
• .rxtx_rdma_codec_enable = REG_FIELD_ID(0xC050, 30, 30, 7, 0x1000),
• .rxtx_wrdma_enable = REG_FIELD_ID(0x18000, 0, 0, 5, 0x1000),
• .rxtx_wrdma_fifowm = REG_FIELD_ID(0x18000, 1, 11, 5, 0x1000),
• .rxtx_wrdma_intf = REG_FIELD_ID(0x18000, 12, 16, 5, 0x1000),
• .rxtx_wrdma_wpscnt = REG_FIELD_ID(0x18000, 17, 20, 5, 0x1000),
• .rxtx_wrdma_bursten = REG_FIELD_ID(0x18000, 21, 21, 5, 0x1000),
• .rxtx_wrdma_dyncclk = REG_FIELD_ID(0x18000, 22, 22, 5, 0x1000),
• .rxtx_wrdma_codec_ch = REG_FIELD_ID(0x18050, 0, 7, 5, 0x1000),
• .rxtx_wrdma_codec_intf = REG_FIELD_ID(0x18050, 16, 19, 5, 0x1000),
• .rxtx_wrdma_codec_fs_delay = REG_FIELD_ID(0x18050, 21, 24, 5, 0x1000),
• .rxtx_wrdma_codec_fs_sel = REG_FIELD_ID(0x18050, 25, 27, 5, 0x1000),
• .rxtx_wrdma_codec_pack = REG_FIELD_ID(0x18050, 29, 29, 5, 0x1000),
• .rxtx_wrdma_codec_enable = REG_FIELD_ID(0x18050, 30, 30, 5, 0x1000),
• .va_wrdma_enable = REG_FIELD_ID(0x18000, 0, 0, 5, 0x1000),
• .va_wrdma_fifowm = REG_FIELD_ID(0x18000, 1, 11, 5, 0x1000),
• .va_wrdma_intf = REG_FIELD_ID(0x18000, 12, 16, 5, 0x1000),
• .va_wrdma_wpscnt = REG_FIELD_ID(0x18000, 17, 20, 5, 0x1000),
• .va_wrdma_bursten = REG_FIELD_ID(0x18000, 21, 21, 5, 0x1000),
• .va_wrdma_dyncclk = REG_FIELD_ID(0x18000, 22, 22, 5, 0x1000),
• .va_wrdma_codec_ch = REG_FIELD_ID(0x18050, 0, 7, 5, 0x1000),
• .va_wrdma_codec_intf = REG_FIELD_ID(0x18050, 16, 19, 5, 0x1000),
• .va_wrdma_codec_fs_delay = REG_FIELD_ID(0x18050, 21, 24, 5, 0x1000),
• .va_wrdma_codec_fs_sel = REG_FIELD_ID(0x18050, 25, 27, 5, 0x1000),
• .va_wrdma_codec_pack = REG_FIELD_ID(0x18050, 29, 29, 5, 0x1000),
• .va_wrdma_codec_enable = REG_FIELD_ID(0x18050, 30, 30, 5, 0x1000),
• .hdmi_tx_ctl_addr = 0x1000,
• .hdmi_legacy_addr = 0x1008,
• .hdmi_vbit_addr = 0x610c0,
• .hdmi_ch_lsb_addr = 0x61048,
• .hdmi_ch_msb_addr = 0x6104c,
• .ch_stride = 0x8,
• .hdmi_parity_addr = 0x61034,
• .hdmi_dmactl_addr = 0x61038,
• .hdmi_dma_stride = 0x4,
• .hdmi_DP_addr = 0x610c8,
• .hdmi_sstream_addr = 0x6101c,
• .hdmi_irq_reg_base = 0x63000,
• .hdmi_irq_ports = 1,
• .hdmi_rdma_dyncclk = REG_FIELD_ID(0x64000, 14, 14, 4, 0x1000),
• .hdmi_rdma_bursten = REG_FIELD_ID(0x64000, 13, 13, 4, 0x1000),
• .hdmi_rdma_burst8 = REG_FIELD_ID(0x64000, 15, 15, 4, 0x1000),
• .hdmi_rdma_burst16 = REG_FIELD_ID(0x64000, 16, 16, 4, 0x1000),
• .hdmi_rdma_dynburst = REG_FIELD_ID(0x64000, 18, 18, 4, 0x1000),
• .hdmi_rdma_wpscnt = REG_FIELD_ID(0x64000, 10, 12, 4, 0x1000),
• .hdmi_rdma_fifowm = REG_FIELD_ID(0x64000, 1, 5, 4, 0x1000),
• .hdmi_rdma_enable = REG_FIELD_ID(0x64000, 0, 0, 4, 0x1000),
• .sstream_en = REG_FIELD(0x6101c, 0, 0),
• .dma_sel = REG_FIELD(0x6101c, 1, 2),
• .auto_bbit_en = REG_FIELD(0x6101c, 3, 3),
• .layout = REG_FIELD(0x6101c, 4, 4),
• .layout_sp = REG_FIELD(0x6101c, 5, 8),
• .set_sp_on_en = REG_FIELD(0x6101c, 10, 10),
• .dp_audio = REG_FIELD(0x6101c, 11, 11),
• .dp_staffing_en = REG_FIELD(0x6101c, 12, 12),
• .dp_sp_b_hw_en = REG_FIELD(0x6101c, 13, 13),
• .mute = REG_FIELD(0x610c8, 0, 0),
• .as_sdp_cc = REG_FIELD(0x610c8, 1, 3),
• .as_sdp_ct = REG_FIELD(0x610c8, 4, 7),
• .aif_db4 = REG_FIELD(0x610c8, 8, 15),
• .frequency = REG_FIELD(0x610c8, 16, 21),
• .mst_index = REG_FIELD(0x610c8, 28, 29),
• .dptx_index = REG_FIELD(0x610c8, 30, 31),
• .soft_reset = REG_FIELD(0x1000, 31, 31),
• .force_reset = REG_FIELD(0x1000, 30, 30),
• .use_hw_chs = REG_FIELD(0x61038, 0, 0),
• .use_hw_usr = REG_FIELD(0x61038, 1, 1),
• .hw_chs_sel = REG_FIELD(0x61038, 2, 4),
• .hw_usr_sel = REG_FIELD(0x61038, 5, 6),
• .replace_vbit = REG_FIELD(0x610c0, 0, 0),
• .vbit_stream = REG_FIELD(0x610c0, 1, 1),
• .legacy_en = REG_FIELD(0x1008, 0, 0),
• .calc_en = REG_FIELD(0x61034, 0, 0),
• .lsb_bits = REG_FIELD(0x61048, 0, 31),
• .msb_bits = REG_FIELD(0x6104c, 0, 31),
• .clk_name = (const char*[]) {

• 					"lpass_aon_cc_audio_hm_h_clk",
  

• 					"lpass_core_cc_sysnoc_mport_core_clk"
  

• 				},
  

• .num_clks = 2,
• .cdc_dma_clk_names = (const char*[]) {

• 					"lpass_audio_cc_codec_mem0_clk",
  

• 					"lpass_audio_cc_codec_mem1_clk",
  

• 					"lpass_audio_cc_codec_mem2_clk",
  

• 					"lpass_aon_cc_va_mem0_clk"
  

• 					},
  

• .cdc_dma_num_clks = 4,
• .dai_driver = sc7280_lpass_cpu_dai_driver,
• .num_dai = ARRAY_SIZE(sc7280_lpass_cpu_dai_driver),
• .dai_osr_clk_names = (const char *[]) {

• 					"null",
  

• 					"null"
  

• 					},
  

• .dai_bit_clk_names = (const char *[]) {

• 					"lpass_core_cc_ext_if0_ibit_clk",
  

• 					"lpass_core_cc_ext_if1_ibit_clk"
  

• 					},
  

• .init = sc7280_lpass_init,
• .exit = sc7280_lpass_exit,
• .alloc_dma_channel = sc7280_lpass_alloc_dma_channel,
• .free_dma_channel = sc7280_lpass_free_dma_channel,

+};

+static const struct of_device_id sc7280_lpass_cpu_device_id[] = {

• {.compatible = "qcom,sc7280-lpass-cpu", .data = &sc7280_data},
• {}

+}; +MODULE_DEVICE_TABLE(of, sc7280_lpass_cpu_device_id);

+static struct platform_driver sc7280_lpass_cpu_platform_driver = {

• .driver = {

• .name = "sc7280-lpass-cpu",
  

• .of_match_table = of_match_ptr(sc7280_lpass_cpu_device_id),
  

• },
• .probe = asoc_qcom_lpass_cpu_platform_probe,
• .remove = asoc_qcom_lpass_cpu_platform_remove,
• .shutdown = asoc_qcom_lpass_cpu_platform_shutdown,

+};

+module_platform_driver(sc7280_lpass_cpu_platform_driver);

+MODULE_DESCRIPTION("SC7280 LPASS CPU DRIVER"); +MODULE_LICENSE("GPL");