I am currently working with an AD1939 being driven by an AT91SAM9263 and currently configured for 4 channels. The AT91 is successfully sending data to to the CODEC but the DMA transfer is not correctly synchronized to the LRCLK frame sync. So, the data for channel 0 might show up in slot 1, 2, 3 - or sometimes slot 0 where it belongs! Can anyone give me a suggestion as to where I might look in the drivers to debug this frame sync problem? My hardware engineer assures me that the AT91 SSC and AD1939 are configured correctly which regard to LRCLK and BCLK.

Thanks!

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