[alsa-devel] [PATCH] ASoC: fsl_sai: Fix Bit Clock Polarity configurations
The BCP bit in TCR4/RCR4 register rules as followings: 0 Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge. 1 Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge.
For all formats currently supported in the fsl_sai driver, they're exactly sending data on the falling edge and sampling on the rising edge.
However, the driver clears this BCP bit for all of them which results click noise when working with SGTL5000 and big noise with WM8962.
Thus this patch corrects the BCP settings for all the formats here to fix the nosie issue.
Signed-off-by: Nicolin Chen Guangyu.Chen@freescale.com --- sound/soc/fsl/fsl_sai.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c index 99051c7..9bbebea 100644 --- a/sound/soc/fsl/fsl_sai.c +++ b/sound/soc/fsl/fsl_sai.c @@ -180,7 +180,7 @@ static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai, * that is, together with the last bit of the previous * data word. */ - val_cr2 &= ~FSL_SAI_CR2_BCP; + val_cr2 |= FSL_SAI_CR2_BCP; val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP; break; case SND_SOC_DAIFMT_LEFT_J: @@ -188,7 +188,7 @@ static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai, * Frame high, one word length for frame sync, * frame sync asserts with the first bit of the frame. */ - val_cr2 &= ~FSL_SAI_CR2_BCP; + val_cr2 |= FSL_SAI_CR2_BCP; val_cr4 &= ~(FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP); break; case SND_SOC_DAIFMT_DSP_A: @@ -198,7 +198,7 @@ static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai, * that is, together with the last bit of the previous * data word. */ - val_cr2 &= ~FSL_SAI_CR2_BCP; + val_cr2 |= FSL_SAI_CR2_BCP; val_cr4 &= ~FSL_SAI_CR4_FSP; val_cr4 |= FSL_SAI_CR4_FSE; sai->is_dsp_mode = true; @@ -208,7 +208,7 @@ static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai, * Frame high, one bit for frame sync, * frame sync asserts with the first bit of the frame. */ - val_cr2 &= ~FSL_SAI_CR2_BCP; + val_cr2 |= FSL_SAI_CR2_BCP; val_cr4 &= ~(FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP); sai->is_dsp_mode = true; break;
Subject: [PATCH] ASoC: fsl_sai: Fix Bit Clock Polarity configurations
The BCP bit in TCR4/RCR4 register rules as followings: 0 Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge. 1 Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge.
For all formats currently supported in the fsl_sai driver, they're exactly sending data on the falling edge and sampling on the rising edge.
However, the driver clears this BCP bit for all of them which results click noise when working with SGTL5000 and big noise with WM8962.
Thus this patch corrects the BCP settings for all the formats here to fix the nosie issue.
Signed-off-by: Nicolin Chen Guangyu.Chen@freescale.com
Good catch.
Acked-by: Xiubo Li Li.Xiubo@freescale.com
Thanks, --
BRs, Xiubo
sound/soc/fsl/fsl_sai.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c index 99051c7..9bbebea 100644 --- a/sound/soc/fsl/fsl_sai.c +++ b/sound/soc/fsl/fsl_sai.c @@ -180,7 +180,7 @@ static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai, * that is, together with the last bit of the previous * data word. */
val_cr2 &= ~FSL_SAI_CR2_BCP;
val_cr2 |= FSL_SAI_CR2_BCP;@@ -188,7 +188,7 @@ static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai, * Frame high, one word length for frame sync, * frame sync asserts with the first bit of the frame. */
val_cr2 &= ~FSL_SAI_CR2_BCP;
val_cr2 |= FSL_SAI_CR2_BCP;@@ -198,7 +198,7 @@ static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai, * that is, together with the last bit of the previous * data word. */
val_cr2 &= ~FSL_SAI_CR2_BCP;
val_cr2 |= FSL_SAI_CR2_BCP;@@ -208,7 +208,7 @@ static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai, * Frame high, one bit for frame sync, * frame sync asserts with the first bit of the frame. */
val_cr2 &= ~FSL_SAI_CR2_BCP;
val_cr2 |= FSL_SAI_CR2_BCP;-- 1.8.4
Hi Xiubo,
On Fri, Apr 04, 2014 at 03:37:00PM +0800, Xiubo Li-B47053 wrote:
Subject: [PATCH] ASoC: fsl_sai: Fix Bit Clock Polarity configurations
The BCP bit in TCR4/RCR4 register rules as followings: 0 Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge. 1 Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge.
For all formats currently supported in the fsl_sai driver, they're exactly sending data on the falling edge and sampling on the rising edge.
However, the driver clears this BCP bit for all of them which results click noise when working with SGTL5000 and big noise with WM8962.
Thus this patch corrects the BCP settings for all the formats here to fix the nosie issue.
Signed-off-by: Nicolin Chen Guangyu.Chen@freescale.com
Good catch.
Acked-by: Xiubo Li Li.Xiubo@freescale.com
Thanks,
Is that possible for you to test those two clock patches for fsl_sai?
I think most of us are waiting for your reply to it. And I'd really like to move on to append clock dividing code into the driver so both of vybrid and imx can easily enable the DAI master mode.
Thank you, Nicolin
--
BRs, Xiubo
sound/soc/fsl/fsl_sai.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c index 99051c7..9bbebea 100644 --- a/sound/soc/fsl/fsl_sai.c +++ b/sound/soc/fsl/fsl_sai.c @@ -180,7 +180,7 @@ static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai, * that is, together with the last bit of the previous * data word. */
val_cr2 &= ~FSL_SAI_CR2_BCP;
val_cr2 |= FSL_SAI_CR2_BCP;@@ -188,7 +188,7 @@ static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai, * Frame high, one word length for frame sync, * frame sync asserts with the first bit of the frame. */
val_cr2 &= ~FSL_SAI_CR2_BCP;
val_cr2 |= FSL_SAI_CR2_BCP;@@ -198,7 +198,7 @@ static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai, * that is, together with the last bit of the previous * data word. */
val_cr2 &= ~FSL_SAI_CR2_BCP;
val_cr2 |= FSL_SAI_CR2_BCP;@@ -208,7 +208,7 @@ static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai, * Frame high, one bit for frame sync, * frame sync asserts with the first bit of the frame. */
val_cr2 &= ~FSL_SAI_CR2_BCP;
val_cr2 |= FSL_SAI_CR2_BCP;-- 1.8.4
Is that possible for you to test those two clock patches for fsl_sai?
I think most of us are waiting for your reply to it. And I'd really like to move on to append clock dividing code into the driver so both of vybrid and imx can easily enable the DAI master mode.
Certainly, I will test them later.
Thanks,
On Fri, Apr 04, 2014 at 03:09:47PM +0800, Nicolin Chen wrote:
The BCP bit in TCR4/RCR4 register rules as followings: 0 Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge. 1 Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge.
Applied, thanks.
On Fri, Apr 04, 2014 at 11:05:32AM +0100, Mark Brown wrote:
On Fri, Apr 04, 2014 at 03:09:47PM +0800, Nicolin Chen wrote:
The BCP bit in TCR4/RCR4 register rules as followings: 0 Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge. 1 Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge.
Applied, thanks.
Sir, I can't find this patch on any of the remote branches: for-next, topic/fsl-sai and fix/fsl-sai. Where could I find it?
Thank you, Nicolin
participants (3)
-
Li.Xiubo＠freescale.com -
Mark Brown -
Nicolin Chen