[PATCH 00/20] Add support for SATA/PCIe/USB2[3]/VIN/CSI on R8A774E1
Hi All,
This patch series adds support for the following peripherals on RZ/G2H SoC * PCIe * SATA * USB2 * USB3 * Audio * VIN * CSI
Cheers, Prabhakar
Lad Prabhakar (20): dt-bindings: pci: rcar-pci: Add device tree support for r8a774e1 arm64: dts: renesas: r8a774e1: Add PCIe device nodes dt-bindings: ata: renesas,rcar-sata: Add r8a774e1 support arm64: dts: renesas: r8a774e1: Add SATA controller node dt-bindings: phy: renesas,usb2-phy: Add r8a774e1 support arm64: dts: renesas: r8a774e1: Add USB2.0 phy and host (EHCI/OHCI) device nodes dt-bindings: usb: renesas,usb3-peri: Document r8a774e1 support dt-bindings: usb: usb-xhci: Document r8a774e1 support dt-bindings: phy: renesas,usb3-phy: Add r8a774e1 support arm64: dts: renesas: r8a774e1: Add USB3.0 device nodes dt-bindings: usb: renesas,usbhs: Add r8a774e1 support dt-bindings: dma: renesas,usb-dmac: Add binding for r8a774e1 arm64: dts: renesas: r8a774e1: Add USB-DMAC and HSUSB device nodes dt-bindings: sound: renesas,rsnd: Document r8a774e1 bindings arm64: dts: renesas: r8a774e1: Add audio support dt-bindings: media: renesas,csi2: Add R8A774E1 support dt-bindings: media: renesas,vin: Add R8A774E1 support media: rcar-csi2: Enable support for R8A774E1 media: rcar-vin: Enable support for R8A774E1 arm64: dts: renesas: r8a774e1: Add VIN and CSI-2 nodes
.../bindings/ata/renesas,rcar-sata.yaml | 1 + .../bindings/dma/renesas,usb-dmac.yaml | 1 + .../bindings/media/renesas,csi2.yaml | 1 + .../bindings/media/renesas,vin.yaml | 1 + .../devicetree/bindings/pci/rcar-pci.txt | 1 + .../bindings/phy/renesas,usb2-phy.yaml | 1 + .../bindings/phy/renesas,usb3-phy.yaml | 1 + .../bindings/sound/renesas,rsnd.txt | 1 + .../bindings/usb/renesas,usb3-peri.yaml | 1 + .../bindings/usb/renesas,usbhs.yaml | 1 + .../devicetree/bindings/usb/usb-xhci.txt | 1 + arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 989 +++++++++++++++++- drivers/media/platform/rcar-vin/rcar-core.c | 40 + drivers/media/platform/rcar-vin/rcar-csi2.c | 4 + 14 files changed, 1022 insertions(+), 22 deletions(-)
Add PCIe support for the RZ/G2H (a.k.a. R8A774E1).
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com --- Documentation/devicetree/bindings/pci/rcar-pci.txt | 1 + 1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pci/rcar-pci.txt b/Documentation/devicetree/bindings/pci/rcar-pci.txt index 1041c44a614f..64bb87e7dd06 100644 --- a/Documentation/devicetree/bindings/pci/rcar-pci.txt +++ b/Documentation/devicetree/bindings/pci/rcar-pci.txt @@ -6,6 +6,7 @@ compatible: "renesas,pcie-r8a7743" for the R8A7743 SoC; "renesas,pcie-r8a774a1" for the R8A774A1 SoC; "renesas,pcie-r8a774b1" for the R8A774B1 SoC; "renesas,pcie-r8a774c0" for the R8A774C0 SoC; + "renesas,pcie-r8a774e1" for the R8A774E1 SoC; "renesas,pcie-r8a7779" for the R8A7779 SoC; "renesas,pcie-r8a7790" for the R8A7790 SoC; "renesas,pcie-r8a7791" for the R8A7791 SoC;
On Thu, 16 Jul 2020 18:18:16 +0100, Lad Prabhakar wrote:
Add PCIe support for the RZ/G2H (a.k.a. R8A774E1).
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com
Documentation/devicetree/bindings/pci/rcar-pci.txt | 1 + 1 file changed, 1 insertion(+)
Acked-by: Rob Herring robh@kernel.org
On Thu, Jul 16, 2020 at 06:18:16PM +0100, Lad Prabhakar wrote:
Add PCIe support for the RZ/G2H (a.k.a. R8A774E1).
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com
Reviewed-by: Wolfram Sang wsa+renesas@sang-engineering.com
On Thu, Jul 16, 2020 at 7:18 PM Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com wrote:
Add PCIe support for the RZ/G2H (a.k.a. R8A774E1).
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com
Reviewed-by: Geert Uytterhoeven geert+renesas@glider.be
Gr{oetje,eeting}s,
Geert
Hi Bjorn,
On Thu, Jul 16, 2020 at 6:18 PM Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com wrote:
Add PCIe support for the RZ/G2H (a.k.a. R8A774E1).
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com
Documentation/devicetree/bindings/pci/rcar-pci.txt | 1 + 1 file changed, 1 insertion(+)
Gentle ping.
Cheers, Prabhakar
Hi Lad-san,
From: Lad, Prabhakar, Sent: Friday, August 28, 2020 2:34 AM
Hi Bjorn,
On Thu, Jul 16, 2020 at 6:18 PM Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com wrote:
Add PCIe support for the RZ/G2H (a.k.a. R8A774E1).
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com
Documentation/devicetree/bindings/pci/rcar-pci.txt | 1 + 1 file changed, 1 insertion(+)
Gentle ping.
Thank you for the ping.
Reviewed-by: Yoshihiro Shimoda yoshihiro.shimoda.uh@renesas.com
Best regards, Yoshihiro Shimoda
Hi Lorenzo,
On Thu, Jul 16, 2020 at 6:18 PM Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com wrote:
Add PCIe support for the RZ/G2H (a.k.a. R8A774E1).
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com
Documentation/devicetree/bindings/pci/rcar-pci.txt | 1 + 1 file changed, 1 insertion(+)
Could you please pick this patch.
Cheers, --Prabhakar Lad
diff --git a/Documentation/devicetree/bindings/pci/rcar-pci.txt b/Documentation/devicetree/bindings/pci/rcar-pci.txt index 1041c44a614f..64bb87e7dd06 100644 --- a/Documentation/devicetree/bindings/pci/rcar-pci.txt +++ b/Documentation/devicetree/bindings/pci/rcar-pci.txt @@ -6,6 +6,7 @@ compatible: "renesas,pcie-r8a7743" for the R8A7743 SoC; "renesas,pcie-r8a774a1" for the R8A774A1 SoC; "renesas,pcie-r8a774b1" for the R8A774B1 SoC; "renesas,pcie-r8a774c0" for the R8A774C0 SoC;
"renesas,pcie-r8a774e1" for the R8A774E1 SoC; "renesas,pcie-r8a7779" for the R8A7779 SoC; "renesas,pcie-r8a7790" for the R8A7790 SoC; "renesas,pcie-r8a7791" for the R8A7791 SoC;-- 2.17.1
Add PCIe{0,1} device nodes for R8A774E1 SoC.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com --- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 47 ++++++++++++++++++++++- 1 file changed, 46 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index 001874af8cf2..5805541b7882 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -1517,12 +1517,57 @@ };
pciec0: pcie@fe000000 { + compatible = "renesas,pcie-r8a774e1", + "renesas,pcie-rcar-gen3"; reg = <0 0xfe000000 0 0x80000>; #address-cells = <3>; #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, + <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, + <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, + <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 319>; status = "disabled"; + };
- /* placeholder */ + pciec1: pcie@ee800000 { + compatible = "renesas,pcie-r8a774e1", + "renesas,pcie-rcar-gen3"; + reg = <0 0xee800000 0 0x80000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, + <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, + <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, + <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 318>; + status = "disabled"; };
hdmi0: hdmi@fead0000 {
On Thu, Jul 16, 2020 at 06:18:17PM +0100, Lad Prabhakar wrote:
Add PCIe{0,1} device nodes for R8A774E1 SoC.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com
Hmm, doesn't apply on top of 5.8-rc6 for me. Is there a branch to pull for easier review?
On Wed, Jul 22, 2020 at 10:58:49AM +0200, Wolfram Sang wrote:
On Thu, Jul 16, 2020 at 06:18:17PM +0100, Lad Prabhakar wrote:
Add PCIe{0,1} device nodes for R8A774E1 SoC.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com
Hmm, doesn't apply on top of 5.8-rc6 for me. Is there a branch to pull for easier review?
My fault, I missed the first series. Please note such dependencies in the cover letter.
On Thu, Jul 16, 2020 at 7:18 PM Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com wrote:
Add PCIe{0,1} device nodes for R8A774E1 SoC.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com
Reviewed-by: Geert Uytterhoeven geert+renesas@glider.be i.e. will queue in renesas-devel for v5.10.
Gr{oetje,eeting}s,
Geert
Document SATA support for the RZ/G2H, no driver change required.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com --- Documentation/devicetree/bindings/ata/renesas,rcar-sata.yaml | 1 + 1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/ata/renesas,rcar-sata.yaml b/Documentation/devicetree/bindings/ata/renesas,rcar-sata.yaml index d06096a7ba4b..2ad2444f1042 100644 --- a/Documentation/devicetree/bindings/ata/renesas,rcar-sata.yaml +++ b/Documentation/devicetree/bindings/ata/renesas,rcar-sata.yaml @@ -26,6 +26,7 @@ properties: - items: - enum: - renesas,sata-r8a774b1 # RZ/G2N + - renesas,sata-r8a774e1 # RZ/G2H - renesas,sata-r8a7795 # R-Car H3 - renesas,sata-r8a77965 # R-Car M3-N - const: renesas,rcar-gen3-sata # generic R-Car Gen3 or RZ/G2
On Thu, 16 Jul 2020 18:18:18 +0100, Lad Prabhakar wrote:
Document SATA support for the RZ/G2H, no driver change required.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com
Documentation/devicetree/bindings/ata/renesas,rcar-sata.yaml | 1 + 1 file changed, 1 insertion(+)
Acked-by: Rob Herring robh@kernel.org
On Thu, Jul 16, 2020 at 7:19 PM Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com wrote:
Document SATA support for the RZ/G2H, no driver change required.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com
Reviewed-by: Geert Uytterhoeven geert+renesas@glider.be
Gr{oetje,eeting}s,
Geert
Hi Jens,
On Thu, Jul 16, 2020 at 6:19 PM Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com wrote:
Document SATA support for the RZ/G2H, no driver change required.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com
Documentation/devicetree/bindings/ata/renesas,rcar-sata.yaml | 1 + 1 file changed, 1 insertion(+)
Could you please pick this patch.
Cheers, Prabhakar
diff --git a/Documentation/devicetree/bindings/ata/renesas,rcar-sata.yaml b/Documentation/devicetree/bindings/ata/renesas,rcar-sata.yaml index d06096a7ba4b..2ad2444f1042 100644 --- a/Documentation/devicetree/bindings/ata/renesas,rcar-sata.yaml +++ b/Documentation/devicetree/bindings/ata/renesas,rcar-sata.yaml @@ -26,6 +26,7 @@ properties: - items: - enum: - renesas,sata-r8a774b1 # RZ/G2N
- renesas,sata-r8a774e1 # RZ/G2H - renesas,sata-r8a7795 # R-Car H3 - renesas,sata-r8a77965 # R-Car M3-N - const: renesas,rcar-gen3-sata # generic R-Car Gen3 or RZ/G2-- 2.17.1
Add the SATA controller node to the RZ/G2H SoC specific dtsi.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com --- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index 5805541b7882..4cd67f360cc0 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -1499,6 +1499,18 @@ status = "disabled"; };
+ sata: sata@ee300000 { + compatible = "renesas,sata-r8a774e1", + "renesas,rcar-gen3-sata"; + reg = <0 0xee300000 0 0x200000>; + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 815>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 815>; + iommus = <&ipmmu_hc 2>; + status = "disabled"; + }; + gic: interrupt-controller@f1010000 { compatible = "arm,gic-400"; #interrupt-cells = <3>;
On Thu, Jul 16, 2020 at 7:19 PM Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com wrote:
Add the SATA controller node to the RZ/G2H SoC specific dtsi.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com
Reviewed-by: Geert Uytterhoeven geert+renesas@glider.be i.e. will queue in renesas-devel for v5.10.
Gr{oetje,eeting}s,
Geert
Document SoC specific bindings for RZ/G2H (r8a774e1) SoC.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com --- Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml | 1 + 1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml index 440f09fddf93..829e8c7e467a 100644 --- a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml +++ b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml @@ -21,6 +21,7 @@ properties: - renesas,usb2-phy-r8a774a1 # RZ/G2M - renesas,usb2-phy-r8a774b1 # RZ/G2N - renesas,usb2-phy-r8a774c0 # RZ/G2E + - renesas,usb2-phy-r8a774e1 # RZ/G2H - renesas,usb2-phy-r8a7795 # R-Car H3 - renesas,usb2-phy-r8a7796 # R-Car M3-W - renesas,usb2-phy-r8a77961 # R-Car M3-W+
On Thu, Jul 16, 2020 at 7:19 PM Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com wrote:
Document SoC specific bindings for RZ/G2H (r8a774e1) SoC.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com
Reviewed-by: Geert Uytterhoeven geert+renesas@glider.be
Gr{oetje,eeting}s,
Geert
Add USB2.0 phy and host (EHCI/OHCI) device nodes on RZ/G2H SoC dtsi.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com --- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 55 ++++++++++++++++++----- 1 file changed, 43 insertions(+), 12 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index 4cd67f360cc0..6f5f82492cee 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -1406,45 +1406,76 @@ };
ohci0: usb@ee080000 { + compatible = "generic-ohci"; reg = <0 0xee080000 0 0x100>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; + phys = <&usb2_phy0 1>; + phy-names = "usb"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 703>, <&cpg 704>; status = "disabled"; - - /* placeholder */ };
ohci1: usb@ee0a0000 { + compatible = "generic-ohci"; reg = <0 0xee0a0000 0 0x100>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 702>; + phys = <&usb2_phy1 1>; + phy-names = "usb"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 702>; status = "disabled"; - - /* placeholder */ };
ehci0: usb@ee080100 { + compatible = "generic-ehci"; reg = <0 0xee080100 0 0x100>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; + phys = <&usb2_phy0 2>; + phy-names = "usb"; + companion = <&ohci0>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 703>, <&cpg 704>; status = "disabled"; - - /* placeholder */ };
ehci1: usb@ee0a0100 { + compatible = "generic-ehci"; reg = <0 0xee0a0100 0 0x100>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 702>; + phys = <&usb2_phy1 2>; + phy-names = "usb"; + companion = <&ohci1>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 702>; status = "disabled"; - - /* placeholder */ };
usb2_phy0: usb-phy@ee080200 { + compatible = "renesas,usb2-phy-r8a774e1", + "renesas,rcar-gen3-usb2-phy"; reg = <0 0xee080200 0 0x700>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 703>, <&cpg 704>; + #phy-cells = <1>; status = "disabled"; - - /* placeholder */ };
usb2_phy1: usb-phy@ee0a0200 { + compatible = "renesas,usb2-phy-r8a774e1", + "renesas,rcar-gen3-usb2-phy"; reg = <0 0xee0a0200 0 0x700>; + clocks = <&cpg CPG_MOD 702>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 702>; + #phy-cells = <1>; status = "disabled"; - - /* placeholder */ };
sdhi0: sd@ee100000 {
On Thu, Jul 16, 2020 at 7:19 PM Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com wrote:
Add USB2.0 phy and host (EHCI/OHCI) device nodes on RZ/G2H SoC dtsi.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com
Reviewed-by: Geert Uytterhoeven geert+renesas@glider.be i.e. will queue in renesas-devel for v5.10.
Gr{oetje,eeting}s,
Geert
Document RZ/G2H (R8A774E1) SoC bindings.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com --- Documentation/devicetree/bindings/usb/renesas,usb3-peri.yaml | 1 + 1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/usb/renesas,usb3-peri.yaml b/Documentation/devicetree/bindings/usb/renesas,usb3-peri.yaml index e3cdeab1199f..b9a008e8469f 100644 --- a/Documentation/devicetree/bindings/usb/renesas,usb3-peri.yaml +++ b/Documentation/devicetree/bindings/usb/renesas,usb3-peri.yaml @@ -16,6 +16,7 @@ properties: - renesas,r8a774a1-usb3-peri # RZ/G2M - renesas,r8a774b1-usb3-peri # RZ/G2N - renesas,r8a774c0-usb3-peri # RZ/G2E + - renesas,r8a774e1-usb3-peri # RZ/G2H - renesas,r8a7795-usb3-peri # R-Car H3 - renesas,r8a7796-usb3-peri # R-Car M3-W - renesas,r8a77961-usb3-peri # R-Car M3-W+
On Thu, 16 Jul 2020 18:18:22 +0100, Lad Prabhakar wrote:
Document RZ/G2H (R8A774E1) SoC bindings.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com
Documentation/devicetree/bindings/usb/renesas,usb3-peri.yaml | 1 + 1 file changed, 1 insertion(+)
Acked-by: Rob Herring robh@kernel.org
On Thu, Jul 16, 2020 at 7:19 PM Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com wrote:
Document RZ/G2H (R8A774E1) SoC bindings.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com
Reviewed-by: Geert Uytterhoeven geert+renesas@glider.be
Gr{oetje,eeting}s,
Geert
Hi Greg,
On Thu, Jul 16, 2020 at 6:19 PM Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com wrote:
Document RZ/G2H (R8A774E1) SoC bindings.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com
Documentation/devicetree/bindings/usb/renesas,usb3-peri.yaml | 1 + 1 file changed, 1 insertion(+)
Could you please pick this patch.
Cheers, Prabhakar
diff --git a/Documentation/devicetree/bindings/usb/renesas,usb3-peri.yaml b/Documentation/devicetree/bindings/usb/renesas,usb3-peri.yaml index e3cdeab1199f..b9a008e8469f 100644 --- a/Documentation/devicetree/bindings/usb/renesas,usb3-peri.yaml +++ b/Documentation/devicetree/bindings/usb/renesas,usb3-peri.yaml @@ -16,6 +16,7 @@ properties: - renesas,r8a774a1-usb3-peri # RZ/G2M - renesas,r8a774b1-usb3-peri # RZ/G2N - renesas,r8a774c0-usb3-peri # RZ/G2E
- renesas,r8a774e1-usb3-peri # RZ/G2H - renesas,r8a7795-usb3-peri # R-Car H3 - renesas,r8a7796-usb3-peri # R-Car M3-W - renesas,r8a77961-usb3-peri # R-Car M3-W+-- 2.17.1
On Sat, Sep 19, 2020 at 11:50:07AM +0100, Lad, Prabhakar wrote:
Hi Greg,
On Thu, Jul 16, 2020 at 6:19 PM Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com wrote:
Document RZ/G2H (R8A774E1) SoC bindings.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com
Documentation/devicetree/bindings/usb/renesas,usb3-peri.yaml | 1 + 1 file changed, 1 insertion(+)
Could you please pick this patch.
Don't DT patches have to be acked by a DT maintainer first?
thanks,
greg k-h
Hi Greg,
On Sun, Sep 20, 2020 at 4:08 PM Greg Kroah-Hartman gregkh@linuxfoundation.org wrote:
On Sat, Sep 19, 2020 at 11:50:07AM +0100, Lad, Prabhakar wrote:
On Thu, Jul 16, 2020 at 6:19 PM Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com wrote:
Document RZ/G2H (R8A774E1) SoC bindings.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com
Documentation/devicetree/bindings/usb/renesas,usb3-peri.yaml | 1 + 1 file changed, 1 insertion(+)
Could you please pick this patch.
Don't DT patches have to be acked by a DT maintainer first?
https://lore.kernel.org/r/20200721033508.GA3504365@bogus
Gr{oetje,eeting}s,
Geert
On Mon, Sep 21, 2020 at 09:30:39AM +0200, Geert Uytterhoeven wrote:
Hi Greg,
On Sun, Sep 20, 2020 at 4:08 PM Greg Kroah-Hartman gregkh@linuxfoundation.org wrote:
On Sat, Sep 19, 2020 at 11:50:07AM +0100, Lad, Prabhakar wrote:
On Thu, Jul 16, 2020 at 6:19 PM Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com wrote:
Document RZ/G2H (R8A774E1) SoC bindings.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com
Documentation/devicetree/bindings/usb/renesas,usb3-peri.yaml | 1 + 1 file changed, 1 insertion(+)
Could you please pick this patch.
Don't DT patches have to be acked by a DT maintainer first?
Ah, missed that, sorry. This, and patch 11/20, now queued up.
greg k-h
On Tue, Sep 22, 2020 at 9:38 AM Greg Kroah-Hartman gregkh@linuxfoundation.org wrote:
On Mon, Sep 21, 2020 at 09:30:39AM +0200, Geert Uytterhoeven wrote:
Hi Greg,
On Sun, Sep 20, 2020 at 4:08 PM Greg Kroah-Hartman gregkh@linuxfoundation.org wrote:
On Sat, Sep 19, 2020 at 11:50:07AM +0100, Lad, Prabhakar wrote:
On Thu, Jul 16, 2020 at 6:19 PM Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com wrote:
Document RZ/G2H (R8A774E1) SoC bindings.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com
Documentation/devicetree/bindings/usb/renesas,usb3-peri.yaml | 1 + 1 file changed, 1 insertion(+)
Could you please pick this patch.
Don't DT patches have to be acked by a DT maintainer first?
Ah, missed that, sorry. This, and patch 11/20, now queued up.
Thank you.
Cheers, Prabhakar
Document r8a774e1 xhci support. The driver will use the fallback compatible string "renesas,rcar-gen3-xhci", therefore no driver change is needed.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com --- Documentation/devicetree/bindings/usb/usb-xhci.txt | 1 + 1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/usb/usb-xhci.txt b/Documentation/devicetree/bindings/usb/usb-xhci.txt index b120dd6612a2..df91a0bb1eeb 100644 --- a/Documentation/devicetree/bindings/usb/usb-xhci.txt +++ b/Documentation/devicetree/bindings/usb/usb-xhci.txt @@ -13,6 +13,7 @@ Required properties: - "renesas,xhci-r8a774a1" for r8a774a1 SoC - "renesas,xhci-r8a774b1" for r8a774b1 SoC - "renesas,xhci-r8a774c0" for r8a774c0 SoC + - "renesas,xhci-r8a774e1" for r8a774e1 SoC - "renesas,xhci-r8a7790" for r8a7790 SoC - "renesas,xhci-r8a7791" for r8a7791 SoC - "renesas,xhci-r8a7793" for r8a7793 SoC
On Thu, 16 Jul 2020 18:18:23 +0100, Lad Prabhakar wrote:
Document r8a774e1 xhci support. The driver will use the fallback compatible string "renesas,rcar-gen3-xhci", therefore no driver change is needed.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com
Documentation/devicetree/bindings/usb/usb-xhci.txt | 1 + 1 file changed, 1 insertion(+)
Acked-by: Rob Herring robh@kernel.org
On Thu, Jul 16, 2020 at 7:19 PM Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com wrote:
Document r8a774e1 xhci support. The driver will use the fallback compatible string "renesas,rcar-gen3-xhci", therefore no driver change is needed.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com
Documentation/devicetree/bindings/usb/usb-xhci.txt | 1 +
In the mean time, this file has been converted to dt-schema in Rob's tree: Documentation/devicetree/bindings/usb/renesas,usb-xhci.yaml
--- a/Documentation/devicetree/bindings/usb/usb-xhci.txt +++ b/Documentation/devicetree/bindings/usb/usb-xhci.txt @@ -13,6 +13,7 @@ Required properties: - "renesas,xhci-r8a774a1" for r8a774a1 SoC - "renesas,xhci-r8a774b1" for r8a774b1 SoC - "renesas,xhci-r8a774c0" for r8a774c0 SoC
- "renesas,xhci-r8a774e1" for r8a774e1 SoC
- "renesas,xhci-r8a7790" for r8a7790 SoC
- "renesas,xhci-r8a7791" for r8a7791 SoC
- "renesas,xhci-r8a7793" for r8a7793 SoC
For the logical change: Reviewed-by: Geert Uytterhoeven geert+renesas@glider.be
Gr{oetje,eeting}s,
Geert
Hi Greg,
On Thu, Jul 16, 2020 at 6:19 PM Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com wrote:
Document r8a774e1 xhci support. The driver will use the fallback compatible string "renesas,rcar-gen3-xhci", therefore no driver change is needed.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com
Documentation/devicetree/bindings/usb/usb-xhci.txt | 1 + 1 file changed, 1 insertion(+)
Gentle ping.
Cheers, Prabhakar
Hi Lad-san,
From: Lad, Prabhakar, Sent: Friday, August 28, 2020 2:15 AM
Hi Greg,
On Thu, Jul 16, 2020 at 6:19 PM Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com wrote:
Document r8a774e1 xhci support. The driver will use the fallback compatible string "renesas,rcar-gen3-xhci", therefore no driver change is needed.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com
Documentation/devicetree/bindings/usb/usb-xhci.txt | 1 + 1 file changed, 1 insertion(+)
Gentle ping.
Thank you for the ping. However, since the latest kernel has renesas,usb-xhci.yaml, would you fix the patch?
Best regards, Yoshihiro Shimoda
Hi Shimoda-san
On Fri, Aug 28, 2020 at 2:11 AM Yoshihiro Shimoda yoshihiro.shimoda.uh@renesas.com wrote:
Hi Lad-san,
From: Lad, Prabhakar, Sent: Friday, August 28, 2020 2:15 AM
Hi Greg,
On Thu, Jul 16, 2020 at 6:19 PM Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com wrote:
Document r8a774e1 xhci support. The driver will use the fallback compatible string "renesas,rcar-gen3-xhci", therefore no driver change is needed.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com
Documentation/devicetree/bindings/usb/usb-xhci.txt | 1 + 1 file changed, 1 insertion(+)
Gentle ping.
Thank you for the ping. However, since the latest kernel has renesas,usb-xhci.yaml, would you fix the patch?
Thank you for pointing out, I have now posted a v2 [1] now. (I missed out Geert's comment earlier for this patch)
[1] https://patchwork.kernel.org/patch/11742289/
Cheers, Prabhakar
Document RZ/G2H (R8A774E1) SoC bindings.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com --- Documentation/devicetree/bindings/phy/renesas,usb3-phy.yaml | 1 + 1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/phy/renesas,usb3-phy.yaml b/Documentation/devicetree/bindings/phy/renesas,usb3-phy.yaml index 68cf9dd0390d..f3ef738a3ff6 100644 --- a/Documentation/devicetree/bindings/phy/renesas,usb3-phy.yaml +++ b/Documentation/devicetree/bindings/phy/renesas,usb3-phy.yaml @@ -15,6 +15,7 @@ properties: - enum: - renesas,r8a774a1-usb3-phy # RZ/G2M - renesas,r8a774b1-usb3-phy # RZ/G2N + - renesas,r8a774e1-usb3-phy # RZ/G2H - renesas,r8a7795-usb3-phy # R-Car H3 - renesas,r8a7796-usb3-phy # R-Car M3-W - renesas,r8a77961-usb3-phy # R-Car M3-W+
On Thu, Jul 16, 2020 at 7:19 PM Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com wrote:
Document RZ/G2H (R8A774E1) SoC bindings.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com
Reviewed-by: Geert Uytterhoeven geert+renesas@glider.be
Gr{oetje,eeting}s,
Geert
Add usb3.0 phy, host and function device nodes on RZ/G2H SoC dtsi.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com --- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 25 +++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index 6f5f82492cee..431eea1f3b97 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -845,11 +845,16 @@ };
usb3_phy0: usb-phy@e65ee000 { + compatible = "renesas,r8a774e1-usb3-phy", + "renesas,rcar-gen3-usb3-phy"; reg = <0 0xe65ee000 0 0x90>; + clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, + <&usb_extal_clk>; + clock-names = "usb3-if", "usb3s_clk", "usb_extal"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 328>; #phy-cells = <0>; status = "disabled"; - - /* placeholder */ };
dmac0: dma-controller@e6700000 { @@ -1392,17 +1397,25 @@ };
xhci0: usb@ee000000 { + compatible = "renesas,xhci-r8a774e1", + "renesas,rcar-gen3-xhci"; reg = <0 0xee000000 0 0xc00>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 328>; status = "disabled"; - - /* placeholder */ };
usb3_peri0: usb@ee020000 { + compatible = "renesas,r8a774e1-usb3-peri", + "renesas,rcar-gen3-usb3-peri"; reg = <0 0xee020000 0 0x400>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 328>; status = "disabled"; - - /* placeholder */ };
ohci0: usb@ee080000 {
On Thu, Jul 16, 2020 at 7:19 PM Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com wrote:
Add usb3.0 phy, host and function device nodes on RZ/G2H SoC dtsi.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com
Reviewed-by: Geert Uytterhoeven geert+renesas@glider.be i.e. will queue in renesas-devel for v5.10.
Gr{oetje,eeting}s,
Geert
Document RZ/G2H (R8A774E1) SoC bindings.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com --- Documentation/devicetree/bindings/usb/renesas,usbhs.yaml | 1 + 1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml b/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml index af4826fb6824..737c1f47b7de 100644 --- a/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml +++ b/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml @@ -39,6 +39,7 @@ properties: - renesas,usbhs-r8a774a1 # RZ/G2M - renesas,usbhs-r8a774b1 # RZ/G2N - renesas,usbhs-r8a774c0 # RZ/G2E + - renesas,usbhs-r8a774e1 # RZ/G2H - renesas,usbhs-r8a7795 # R-Car H3 - renesas,usbhs-r8a7796 # R-Car M3-W - renesas,usbhs-r8a77961 # R-Car M3-W+
On Thu, 16 Jul 2020 18:18:26 +0100, Lad Prabhakar wrote:
Document RZ/G2H (R8A774E1) SoC bindings.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com
Documentation/devicetree/bindings/usb/renesas,usbhs.yaml | 1 + 1 file changed, 1 insertion(+)
Acked-by: Rob Herring robh@kernel.org
On Thu, Jul 16, 2020 at 7:19 PM Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com wrote:
Document RZ/G2H (R8A774E1) SoC bindings.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com
Reviewed-by: Geert Uytterhoeven geert+renesas@glider.be
Gr{oetje,eeting}s,
Geert
Hi Greg,
On Thu, Jul 16, 2020 at 6:19 PM Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com wrote:
Document RZ/G2H (R8A774E1) SoC bindings.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com
Documentation/devicetree/bindings/usb/renesas,usbhs.yaml | 1 + 1 file changed, 1 insertion(+)
Gentle ping.
Cheers, Prabhakar
Hi Lad-san,
From: Lad, Prabhakar, Sent: Friday, August 28, 2020 2:08 AM
Hi Greg,
On Thu, Jul 16, 2020 at 6:19 PM Lad Prabhakar, wrote:
Document RZ/G2H (R8A774E1) SoC bindings.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com
Documentation/devicetree/bindings/usb/renesas,usbhs.yaml | 1 + 1 file changed, 1 insertion(+)
Gentle ping.
Thank you for the ping.
Reviewed-by: Yoshihiro Shimoda yoshihiro.shimoda.uh@renesas.com
Best regards, Yoshihiro Shimoda
Hi Greg,
On Thu, Jul 16, 2020 at 6:19 PM Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com wrote:
Document RZ/G2H (R8A774E1) SoC bindings.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com
Documentation/devicetree/bindings/usb/renesas,usbhs.yaml | 1 + 1 file changed, 1 insertion(+)
Could you please pick this patch.
Cheers, Prabhakar
diff --git a/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml b/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml index af4826fb6824..737c1f47b7de 100644 --- a/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml +++ b/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml @@ -39,6 +39,7 @@ properties: - renesas,usbhs-r8a774a1 # RZ/G2M - renesas,usbhs-r8a774b1 # RZ/G2N - renesas,usbhs-r8a774c0 # RZ/G2E
- renesas,usbhs-r8a774e1 # RZ/G2H - renesas,usbhs-r8a7795 # R-Car H3 - renesas,usbhs-r8a7796 # R-Car M3-W - renesas,usbhs-r8a77961 # R-Car M3-W+-- 2.17.1
On Sat, Sep 19, 2020 at 11:54:05AM +0100, Lad, Prabhakar wrote:
Hi Greg,
On Thu, Jul 16, 2020 at 6:19 PM Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com wrote:
Document RZ/G2H (R8A774E1) SoC bindings.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com
Documentation/devicetree/bindings/usb/renesas,usbhs.yaml | 1 + 1 file changed, 1 insertion(+)
Could you please pick this patch.
Same here, doesn't a DT maintainer have to ack this?
thanks,
greg k-h
Hi Greg,
On Sun, Sep 20, 2020 at 4:08 PM Greg Kroah-Hartman gregkh@linuxfoundation.org wrote:
On Sat, Sep 19, 2020 at 11:54:05AM +0100, Lad, Prabhakar wrote:
On Thu, Jul 16, 2020 at 6:19 PM Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com wrote:
Document RZ/G2H (R8A774E1) SoC bindings.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com
Documentation/devicetree/bindings/usb/renesas,usbhs.yaml | 1 + 1 file changed, 1 insertion(+)
Could you please pick this patch.
Same here, doesn't a DT maintainer have to ack this?
And so *he did: https://lore.kernel.org/r/20200721033544.GA3505976@bogus
Gr{oetje,eeting}s,
Geert
Add binding for R8A774E1 SoC (RZ/G2H).
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com --- Documentation/devicetree/bindings/dma/renesas,usb-dmac.yaml | 1 + 1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/dma/renesas,usb-dmac.yaml b/Documentation/devicetree/bindings/dma/renesas,usb-dmac.yaml index 03aea6ae651f..ab287c652b2c 100644 --- a/Documentation/devicetree/bindings/dma/renesas,usb-dmac.yaml +++ b/Documentation/devicetree/bindings/dma/renesas,usb-dmac.yaml @@ -24,6 +24,7 @@ properties: - renesas,r8a774a1-usb-dmac # RZ/G2M - renesas,r8a774b1-usb-dmac # RZ/G2N - renesas,r8a774c0-usb-dmac # RZ/G2E + - renesas,r8a774e1-usb-dmac # RZ/G2H - renesas,r8a7790-usb-dmac # R-Car H2 - renesas,r8a7791-usb-dmac # R-Car M2-W - renesas,r8a7793-usb-dmac # R-Car M2-N
On Thu, Jul 16, 2020 at 7:19 PM Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com wrote:
Add binding for R8A774E1 SoC (RZ/G2H).
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com
Reviewed-by: Geert Uytterhoeven geert+renesas@glider.be
Gr{oetje,eeting}s,
Geert
Add usb dmac and hsusb device nodes to the RZ/G2H SoC dtsi.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com --- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 40 ++++++++++++++++++++++- 1 file changed, 39 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index 431eea1f3b97..c2797f496e9a 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -838,10 +838,48 @@ };
hsusb: usb@e6590000 { + compatible = "renesas,usbhs-r8a774e1", + "renesas,rcar-gen3-usbhs"; reg = <0 0xe6590000 0 0x200>; + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; + dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, + <&usb_dmac1 0>, <&usb_dmac1 1>; + dma-names = "ch0", "ch1", "ch2", "ch3"; + renesas,buswait = <11>; + phys = <&usb2_phy0 3>; + phy-names = "usb"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 704>, <&cpg 703>; status = "disabled"; + };
- /* placeholder */ + usb_dmac0: dma-controller@e65a0000 { + compatible = "renesas,r8a774e1-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65a0000 0 0x100>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 330>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 330>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb_dmac1: dma-controller@e65b0000 { + compatible = "renesas,r8a774e1-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65b0000 0 0x100>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 331>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 331>; + #dma-cells = <1>; + dma-channels = <2>; };
usb3_phy0: usb-phy@e65ee000 {
On Thu, Jul 16, 2020 at 7:19 PM Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com wrote:
Add usb dmac and hsusb device nodes to the RZ/G2H SoC dtsi.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com
Reviewed-by: Geert Uytterhoeven geert+renesas@glider.be i.e. will queue in renesas-devel for v5.10.
Gr{oetje,eeting}s,
Geert
Document SoC specific bindings for RZ/G2H (r8a774e1) SoC.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com --- Documentation/devicetree/bindings/sound/renesas,rsnd.txt | 1 + 1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt index 1596f0d1e2fe..b39743d3f7c4 100644 --- a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt +++ b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt @@ -271,6 +271,7 @@ Required properties: - "renesas,rcar_sound-r8a774a1" (RZ/G2M) - "renesas,rcar_sound-r8a774b1" (RZ/G2N) - "renesas,rcar_sound-r8a774c0" (RZ/G2E) + - "renesas,rcar_sound-r8a774e1" (RZ/G2H) - "renesas,rcar_sound-r8a7778" (R-Car M1A) - "renesas,rcar_sound-r8a7779" (R-Car H1) - "renesas,rcar_sound-r8a7790" (R-Car H2)
On Thu, Jul 16, 2020 at 7:20 PM Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com wrote:
Document SoC specific bindings for RZ/G2H (r8a774e1) SoC.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com
Reviewed-by: Geert Uytterhoeven geert+renesas@glider.be
Gr{oetje,eeting}s,
Geert
Add sound support for the RZ/G2H SoC (a.k.a. R8A774E1).
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com --- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 476 +++++++++++++++++++++- 1 file changed, 474 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index c2797f496e9a..ce9e5615b932 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -1416,6 +1416,19 @@ };
rcar_sound: sound@ec500000 { + /* + * #sound-dai-cells is required + * + * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; + * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; + */ + /* + * #clock-cells is required for audio_clkout0/1/2/3 + * + * clkout : #clock-cells = <0>; <&rcar_sound>; + * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; + */ + compatible = "renesas,rcar_sound-r8a774e1", "renesas,rcar_sound-gen3"; reg = <0 0xec500000 0 0x1000>, /* SCU */ <0 0xec5a0000 0 0x100>, /* ADG */ <0 0xec540000 0 0x1000>, /* SSIU */ @@ -1423,17 +1436,476 @@ <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+ clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clk_a>, <&audio_clk_b>, + <&audio_clk_c>, + <&cpg CPG_CORE R8A774E1_CLK_S0D4>; + clock-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", + "ssi.5", "ssi.4", "ssi.3", "ssi.2", + "ssi.1", "ssi.0", + "src.9", "src.8", "src.7", "src.6", + "src.5", "src.4", "src.3", "src.2", + "src.1", "src.0", + "mix.1", "mix.0", + "ctu.1", "ctu.0", + "dvc.0", "dvc.1", + "clk_a", "clk_b", "clk_c", "clk_i"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 1005>, + <&cpg 1006>, <&cpg 1007>, + <&cpg 1008>, <&cpg 1009>, + <&cpg 1010>, <&cpg 1011>, + <&cpg 1012>, <&cpg 1013>, + <&cpg 1014>, <&cpg 1015>; + reset-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", + "ssi.5", "ssi.4", "ssi.3", "ssi.2", + "ssi.1", "ssi.0"; status = "disabled";
- /* placeholder */ + rcar_sound,dvc { + dvc0: dvc-0 { + dmas = <&audma1 0xbc>; + dma-names = "tx"; + }; + dvc1: dvc-1 { + dmas = <&audma1 0xbe>; + dma-names = "tx"; + }; + }; + + rcar_sound,mix { + mix0: mix-0 { }; + mix1: mix-1 { }; + }; + + rcar_sound,ctu { + ctu00: ctu-0 { }; + ctu01: ctu-1 { }; + ctu02: ctu-2 { }; + ctu03: ctu-3 { }; + ctu10: ctu-4 { }; + ctu11: ctu-5 { }; + ctu12: ctu-6 { }; + ctu13: ctu-7 { }; + }; + + rcar_sound,src { + src0: src-0 { + interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x85>, <&audma1 0x9a>; + dma-names = "rx", "tx"; + }; + src1: src-1 { + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x87>, <&audma1 0x9c>; + dma-names = "rx", "tx"; + }; + src2: src-2 { + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x89>, <&audma1 0x9e>; + dma-names = "rx", "tx"; + }; + src3: src-3 { + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8b>, <&audma1 0xa0>; + dma-names = "rx", "tx"; + }; + src4: src-4 { + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8d>, <&audma1 0xb0>; + dma-names = "rx", "tx"; + }; + src5: src-5 { + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8f>, <&audma1 0xb2>; + dma-names = "rx", "tx"; + }; + src6: src-6 { + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x91>, <&audma1 0xb4>; + dma-names = "rx", "tx"; + }; + src7: src-7 { + interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x93>, <&audma1 0xb6>; + dma-names = "rx", "tx"; + }; + src8: src-8 { + interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x95>, <&audma1 0xb8>; + dma-names = "rx", "tx"; + }; + src9: src-9 { + interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x97>, <&audma1 0xba>; + dma-names = "rx", "tx"; + }; + }; + + rcar_sound,ssiu { + ssiu00: ssiu-0 { + dmas = <&audma0 0x15>, <&audma1 0x16>; + dma-names = "rx", "tx"; + }; + ssiu01: ssiu-1 { + dmas = <&audma0 0x35>, <&audma1 0x36>; + dma-names = "rx", "tx"; + }; + ssiu02: ssiu-2 { + dmas = <&audma0 0x37>, <&audma1 0x38>; + dma-names = "rx", "tx"; + }; + ssiu03: ssiu-3 { + dmas = <&audma0 0x47>, <&audma1 0x48>; + dma-names = "rx", "tx"; + }; + ssiu04: ssiu-4 { + dmas = <&audma0 0x3F>, <&audma1 0x40>; + dma-names = "rx", "tx"; + }; + ssiu05: ssiu-5 { + dmas = <&audma0 0x43>, <&audma1 0x44>; + dma-names = "rx", "tx"; + }; + ssiu06: ssiu-6 { + dmas = <&audma0 0x4F>, <&audma1 0x50>; + dma-names = "rx", "tx"; + }; + ssiu07: ssiu-7 { + dmas = <&audma0 0x53>, <&audma1 0x54>; + dma-names = "rx", "tx"; + }; + ssiu10: ssiu-8 { + dmas = <&audma0 0x49>, <&audma1 0x4a>; + dma-names = "rx", "tx"; + }; + ssiu11: ssiu-9 { + dmas = <&audma0 0x4B>, <&audma1 0x4C>; + dma-names = "rx", "tx"; + }; + ssiu12: ssiu-10 { + dmas = <&audma0 0x57>, <&audma1 0x58>; + dma-names = "rx", "tx"; + }; + ssiu13: ssiu-11 { + dmas = <&audma0 0x59>, <&audma1 0x5A>; + dma-names = "rx", "tx"; + }; + ssiu14: ssiu-12 { + dmas = <&audma0 0x5F>, <&audma1 0x60>; + dma-names = "rx", "tx"; + }; + ssiu15: ssiu-13 { + dmas = <&audma0 0xC3>, <&audma1 0xC4>; + dma-names = "rx", "tx"; + }; + ssiu16: ssiu-14 { + dmas = <&audma0 0xC7>, <&audma1 0xC8>; + dma-names = "rx", "tx"; + }; + ssiu17: ssiu-15 { + dmas = <&audma0 0xCB>, <&audma1 0xCC>; + dma-names = "rx", "tx"; + }; + ssiu20: ssiu-16 { + dmas = <&audma0 0x63>, <&audma1 0x64>; + dma-names = "rx", "tx"; + }; + ssiu21: ssiu-17 { + dmas = <&audma0 0x67>, <&audma1 0x68>; + dma-names = "rx", "tx"; + }; + ssiu22: ssiu-18 { + dmas = <&audma0 0x6B>, <&audma1 0x6C>; + dma-names = "rx", "tx"; + }; + ssiu23: ssiu-19 { + dmas = <&audma0 0x6D>, <&audma1 0x6E>; + dma-names = "rx", "tx"; + }; + ssiu24: ssiu-20 { + dmas = <&audma0 0xCF>, <&audma1 0xCE>; + dma-names = "rx", "tx"; + }; + ssiu25: ssiu-21 { + dmas = <&audma0 0xEB>, <&audma1 0xEC>; + dma-names = "rx", "tx"; + }; + ssiu26: ssiu-22 { + dmas = <&audma0 0xED>, <&audma1 0xEE>; + dma-names = "rx", "tx"; + }; + ssiu27: ssiu-23 { + dmas = <&audma0 0xEF>, <&audma1 0xF0>; + dma-names = "rx", "tx"; + }; + ssiu30: ssiu-24 { + dmas = <&audma0 0x6f>, <&audma1 0x70>; + dma-names = "rx", "tx"; + }; + ssiu31: ssiu-25 { + dmas = <&audma0 0x21>, <&audma1 0x22>; + dma-names = "rx", "tx"; + }; + ssiu32: ssiu-26 { + dmas = <&audma0 0x23>, <&audma1 0x24>; + dma-names = "rx", "tx"; + }; + ssiu33: ssiu-27 { + dmas = <&audma0 0x25>, <&audma1 0x26>; + dma-names = "rx", "tx"; + }; + ssiu34: ssiu-28 { + dmas = <&audma0 0x27>, <&audma1 0x28>; + dma-names = "rx", "tx"; + }; + ssiu35: ssiu-29 { + dmas = <&audma0 0x29>, <&audma1 0x2A>; + dma-names = "rx", "tx"; + }; + ssiu36: ssiu-30 { + dmas = <&audma0 0x2B>, <&audma1 0x2C>; + dma-names = "rx", "tx"; + }; + ssiu37: ssiu-31 { + dmas = <&audma0 0x2D>, <&audma1 0x2E>; + dma-names = "rx", "tx"; + }; + ssiu40: ssiu-32 { + dmas = <&audma0 0x71>, <&audma1 0x72>; + dma-names = "rx", "tx"; + }; + ssiu41: ssiu-33 { + dmas = <&audma0 0x17>, <&audma1 0x18>; + dma-names = "rx", "tx"; + }; + ssiu42: ssiu-34 { + dmas = <&audma0 0x19>, <&audma1 0x1A>; + dma-names = "rx", "tx"; + }; + ssiu43: ssiu-35 { + dmas = <&audma0 0x1B>, <&audma1 0x1C>; + dma-names = "rx", "tx"; + }; + ssiu44: ssiu-36 { + dmas = <&audma0 0x1D>, <&audma1 0x1E>; + dma-names = "rx", "tx"; + }; + ssiu45: ssiu-37 { + dmas = <&audma0 0x1F>, <&audma1 0x20>; + dma-names = "rx", "tx"; + }; + ssiu46: ssiu-38 { + dmas = <&audma0 0x31>, <&audma1 0x32>; + dma-names = "rx", "tx"; + }; + ssiu47: ssiu-39 { + dmas = <&audma0 0x33>, <&audma1 0x34>; + dma-names = "rx", "tx"; + }; + ssiu50: ssiu-40 { + dmas = <&audma0 0x73>, <&audma1 0x74>; + dma-names = "rx", "tx"; + }; + ssiu60: ssiu-41 { + dmas = <&audma0 0x75>, <&audma1 0x76>; + dma-names = "rx", "tx"; + }; + ssiu70: ssiu-42 { + dmas = <&audma0 0x79>, <&audma1 0x7a>; + dma-names = "rx", "tx"; + }; + ssiu80: ssiu-43 { + dmas = <&audma0 0x7b>, <&audma1 0x7c>; + dma-names = "rx", "tx"; + }; + ssiu90: ssiu-44 { + dmas = <&audma0 0x7d>, <&audma1 0x7e>; + dma-names = "rx", "tx"; + }; + ssiu91: ssiu-45 { + dmas = <&audma0 0x7F>, <&audma1 0x80>; + dma-names = "rx", "tx"; + }; + ssiu92: ssiu-46 { + dmas = <&audma0 0x81>, <&audma1 0x82>; + dma-names = "rx", "tx"; + }; + ssiu93: ssiu-47 { + dmas = <&audma0 0x83>, <&audma1 0x84>; + dma-names = "rx", "tx"; + }; + ssiu94: ssiu-48 { + dmas = <&audma0 0xA3>, <&audma1 0xA4>; + dma-names = "rx", "tx"; + }; + ssiu95: ssiu-49 { + dmas = <&audma0 0xA5>, <&audma1 0xA6>; + dma-names = "rx", "tx"; + }; + ssiu96: ssiu-50 { + dmas = <&audma0 0xA7>, <&audma1 0xA8>; + dma-names = "rx", "tx"; + }; + ssiu97: ssiu-51 { + dmas = <&audma0 0xA9>, <&audma1 0xAA>; + dma-names = "rx", "tx"; + }; + };
rcar_sound,ssi { + ssi0: ssi-0 { + interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x01>, <&audma1 0x02>; + dma-names = "rx", "tx"; + }; + ssi1: ssi-1 { + interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x03>, <&audma1 0x04>; + dma-names = "rx", "tx"; + }; ssi2: ssi-2 { - /* placeholder */ + interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x05>, <&audma1 0x06>; + dma-names = "rx", "tx"; + }; + ssi3: ssi-3 { + interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x07>, <&audma1 0x08>; + dma-names = "rx", "tx"; + }; + ssi4: ssi-4 { + interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x09>, <&audma1 0x0a>; + dma-names = "rx", "tx"; + }; + ssi5: ssi-5 { + interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0b>, <&audma1 0x0c>; + dma-names = "rx", "tx"; + }; + ssi6: ssi-6 { + interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0d>, <&audma1 0x0e>; + dma-names = "rx", "tx"; + }; + ssi7: ssi-7 { + interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0f>, <&audma1 0x10>; + dma-names = "rx", "tx"; + }; + ssi8: ssi-8 { + interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x11>, <&audma1 0x12>; + dma-names = "rx", "tx"; + }; + ssi9: ssi-9 { + interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x13>, <&audma1 0x14>; + dma-names = "rx", "tx"; }; }; };
+ audma0: dma-controller@ec700000 { + compatible = "renesas,dmac-r8a774e1", + "renesas,rcar-dmac"; + reg = <0 0xec700000 0 0x10000>; + interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 502>; + clock-names = "fck"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 502>; + #dma-cells = <1>; + dma-channels = <16>; + iommus = <&ipmmu_mp0 0>, <&ipmmu_mp0 1>, + <&ipmmu_mp0 2>, <&ipmmu_mp0 3>, + <&ipmmu_mp0 4>, <&ipmmu_mp0 5>, + <&ipmmu_mp0 6>, <&ipmmu_mp0 7>, + <&ipmmu_mp0 8>, <&ipmmu_mp0 9>, + <&ipmmu_mp0 10>, <&ipmmu_mp0 11>, + <&ipmmu_mp0 12>, <&ipmmu_mp0 13>, + <&ipmmu_mp0 14>, <&ipmmu_mp0 15>; + }; + + audma1: dma-controller@ec720000 { + compatible = "renesas,dmac-r8a774e1", + "renesas,rcar-dmac"; + reg = <0 0xec720000 0 0x10000>; + interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 501>; + clock-names = "fck"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 501>; + #dma-cells = <1>; + dma-channels = <16>; + iommus = <&ipmmu_mp0 16>, <&ipmmu_mp0 17>, + <&ipmmu_mp0 18>, <&ipmmu_mp0 19>, + <&ipmmu_mp0 20>, <&ipmmu_mp0 21>, + <&ipmmu_mp0 22>, <&ipmmu_mp0 23>, + <&ipmmu_mp0 24>, <&ipmmu_mp0 25>, + <&ipmmu_mp0 26>, <&ipmmu_mp0 27>, + <&ipmmu_mp0 28>, <&ipmmu_mp0 29>, + <&ipmmu_mp0 30>, <&ipmmu_mp0 31>; + }; + xhci0: usb@ee000000 { compatible = "renesas,xhci-r8a774e1", "renesas,rcar-gen3-xhci";
On Thu, Jul 16, 2020 at 7:20 PM Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com wrote:
Add sound support for the RZ/G2H SoC (a.k.a. R8A774E1).
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com
Reviewed-by: Geert Uytterhoeven geert+renesas@glider.be i.e. will queue in renesas-devel for v5.10.
Gr{oetje,eeting}s,
Geert
Add the compatible string for RZ/G2H (R8A774E1) to the list of supported SoCs.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com --- Documentation/devicetree/bindings/media/renesas,csi2.yaml | 1 + 1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/media/renesas,csi2.yaml b/Documentation/devicetree/bindings/media/renesas,csi2.yaml index c9e068231d4b..53b078622fd9 100644 --- a/Documentation/devicetree/bindings/media/renesas,csi2.yaml +++ b/Documentation/devicetree/bindings/media/renesas,csi2.yaml @@ -22,6 +22,7 @@ properties: - renesas,r8a774a1-csi2 # RZ/G2M - renesas,r8a774b1-csi2 # RZ/G2N - renesas,r8a774c0-csi2 # RZ/G2E + - renesas,r8a774e1-csi2 # RZ/G2H - renesas,r8a7795-csi2 # R-Car H3 - renesas,r8a7796-csi2 # R-Car M3-W - renesas,r8a77965-csi2 # R-Car M3-N
Hi Lad,
Thanks for your patch.
On 2020-07-16 18:18:31 +0100, Lad Prabhakar wrote:
Add the compatible string for RZ/G2H (R8A774E1) to the list of supported SoCs.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com
Reviewed-by: Niklas Söderlund niklas.soderlund+renesas@ragnatech.se
Documentation/devicetree/bindings/media/renesas,csi2.yaml | 1 + 1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/media/renesas,csi2.yaml b/Documentation/devicetree/bindings/media/renesas,csi2.yaml index c9e068231d4b..53b078622fd9 100644 --- a/Documentation/devicetree/bindings/media/renesas,csi2.yaml +++ b/Documentation/devicetree/bindings/media/renesas,csi2.yaml @@ -22,6 +22,7 @@ properties: - renesas,r8a774a1-csi2 # RZ/G2M - renesas,r8a774b1-csi2 # RZ/G2N - renesas,r8a774c0-csi2 # RZ/G2E
- renesas,r8a774e1-csi2 # RZ/G2H - renesas,r8a7795-csi2 # R-Car H3 - renesas,r8a7796-csi2 # R-Car M3-W - renesas,r8a77965-csi2 # R-Car M3-N-- 2.17.1
On Thu, 16 Jul 2020 18:18:31 +0100, Lad Prabhakar wrote:
Add the compatible string for RZ/G2H (R8A774E1) to the list of supported SoCs.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com
Documentation/devicetree/bindings/media/renesas,csi2.yaml | 1 + 1 file changed, 1 insertion(+)
Acked-by: Rob Herring robh@kernel.org
Document support for the VIN module in the Renesas RZ/G2H (R8A774E1) SoC.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com --- Documentation/devicetree/bindings/media/renesas,vin.yaml | 1 + 1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/media/renesas,vin.yaml b/Documentation/devicetree/bindings/media/renesas,vin.yaml index 53c0a7238bac..4e0de280c1e5 100644 --- a/Documentation/devicetree/bindings/media/renesas,vin.yaml +++ b/Documentation/devicetree/bindings/media/renesas,vin.yaml @@ -40,6 +40,7 @@ properties: - renesas,vin-r8a774a1 # RZ/G2M - renesas,vin-r8a774b1 # RZ/G2N - renesas,vin-r8a774c0 # RZ/G2E + - renesas,vin-r8a774e1 # RZ/G2H - renesas,vin-r8a7778 # R-Car M1 - renesas,vin-r8a7779 # R-Car H1 - renesas,vin-r8a7795 # R-Car H3
Hi Lad,
Thanks for your work.
On 2020-07-16 18:18:32 +0100, Lad Prabhakar wrote:
Document support for the VIN module in the Renesas RZ/G2H (R8A774E1) SoC.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com
Reviewed-by: Niklas Söderlund niklas.soderlund+renesas@ragnatech.se
Documentation/devicetree/bindings/media/renesas,vin.yaml | 1 + 1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/media/renesas,vin.yaml b/Documentation/devicetree/bindings/media/renesas,vin.yaml index 53c0a7238bac..4e0de280c1e5 100644 --- a/Documentation/devicetree/bindings/media/renesas,vin.yaml +++ b/Documentation/devicetree/bindings/media/renesas,vin.yaml @@ -40,6 +40,7 @@ properties: - renesas,vin-r8a774a1 # RZ/G2M - renesas,vin-r8a774b1 # RZ/G2N - renesas,vin-r8a774c0 # RZ/G2E
- renesas,vin-r8a774e1 # RZ/G2H - renesas,vin-r8a7778 # R-Car M1 - renesas,vin-r8a7779 # R-Car H1 - renesas,vin-r8a7795 # R-Car H3-- 2.17.1
On Thu, 16 Jul 2020 18:18:32 +0100, Lad Prabhakar wrote:
Document support for the VIN module in the Renesas RZ/G2H (R8A774E1) SoC.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com
Documentation/devicetree/bindings/media/renesas,vin.yaml | 1 + 1 file changed, 1 insertion(+)
Acked-by: Rob Herring robh@kernel.org
Add the MIPI CSI-2 driver support for RZ/G2H (R8A774E1) SoC. The CSI-2 module of RZ/G2H is similar to R-Car H3.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com --- drivers/media/platform/rcar-vin/rcar-csi2.c | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/drivers/media/platform/rcar-vin/rcar-csi2.c b/drivers/media/platform/rcar-vin/rcar-csi2.c index c6cc4f473a07..2325e3b103e4 100644 --- a/drivers/media/platform/rcar-vin/rcar-csi2.c +++ b/drivers/media/platform/rcar-vin/rcar-csi2.c @@ -1090,6 +1090,10 @@ static const struct of_device_id rcar_csi2_of_table[] = { .compatible = "renesas,r8a774c0-csi2", .data = &rcar_csi2_info_r8a77990, }, + { + .compatible = "renesas,r8a774e1-csi2", + .data = &rcar_csi2_info_r8a7795, + }, { .compatible = "renesas,r8a7795-csi2", .data = &rcar_csi2_info_r8a7795,
Hi Lad,
Thanks for your work.
On 2020-07-16 18:18:33 +0100, Lad Prabhakar wrote:
Add the MIPI CSI-2 driver support for RZ/G2H (R8A774E1) SoC. The CSI-2 module of RZ/G2H is similar to R-Car H3.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com
Reviewed-by: Niklas Söderlund niklas.soderlund+renesas@ragnatech.se
drivers/media/platform/rcar-vin/rcar-csi2.c | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/drivers/media/platform/rcar-vin/rcar-csi2.c b/drivers/media/platform/rcar-vin/rcar-csi2.c index c6cc4f473a07..2325e3b103e4 100644 --- a/drivers/media/platform/rcar-vin/rcar-csi2.c +++ b/drivers/media/platform/rcar-vin/rcar-csi2.c @@ -1090,6 +1090,10 @@ static const struct of_device_id rcar_csi2_of_table[] = { .compatible = "renesas,r8a774c0-csi2", .data = &rcar_csi2_info_r8a77990, },
- {
.compatible = "renesas,r8a774e1-csi2",.data = &rcar_csi2_info_r8a7795,- }, { .compatible = "renesas,r8a7795-csi2", .data = &rcar_csi2_info_r8a7795,
-- 2.17.1
Add the SoC specific information for RZ/G2H (R8A774E1) SoC. Also add the routing information between CSI2 and VIN (which is similar to R-Car H3 except it lacks CSI41).
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com --- drivers/media/platform/rcar-vin/rcar-core.c | 40 +++++++++++++++++++++ 1 file changed, 40 insertions(+)
diff --git a/drivers/media/platform/rcar-vin/rcar-core.c b/drivers/media/platform/rcar-vin/rcar-core.c index 7440c8965d27..4fb76d1df308 100644 --- a/drivers/media/platform/rcar-vin/rcar-core.c +++ b/drivers/media/platform/rcar-vin/rcar-core.c @@ -944,6 +944,42 @@ static const struct rvin_info rcar_info_gen2 = { .max_height = 2048, };
+static const struct rvin_group_route rcar_info_r8a774e1_routes[] = { + { .csi = RVIN_CSI40, .channel = 0, .vin = 0, .mask = BIT(0) | BIT(3) }, + { .csi = RVIN_CSI20, .channel = 0, .vin = 0, .mask = BIT(1) | BIT(4) }, + { .csi = RVIN_CSI40, .channel = 1, .vin = 0, .mask = BIT(2) }, + { .csi = RVIN_CSI20, .channel = 0, .vin = 1, .mask = BIT(0) }, + { .csi = RVIN_CSI40, .channel = 1, .vin = 1, .mask = BIT(1) | BIT(3) }, + { .csi = RVIN_CSI40, .channel = 0, .vin = 1, .mask = BIT(2) }, + { .csi = RVIN_CSI20, .channel = 1, .vin = 1, .mask = BIT(4) }, + { .csi = RVIN_CSI20, .channel = 1, .vin = 2, .mask = BIT(0) }, + { .csi = RVIN_CSI40, .channel = 0, .vin = 2, .mask = BIT(1) }, + { .csi = RVIN_CSI20, .channel = 0, .vin = 2, .mask = BIT(2) }, + { .csi = RVIN_CSI40, .channel = 2, .vin = 2, .mask = BIT(3) }, + { .csi = RVIN_CSI20, .channel = 2, .vin = 2, .mask = BIT(4) }, + { .csi = RVIN_CSI40, .channel = 1, .vin = 3, .mask = BIT(0) }, + { .csi = RVIN_CSI20, .channel = 1, .vin = 3, .mask = BIT(1) | BIT(2) }, + { .csi = RVIN_CSI40, .channel = 3, .vin = 3, .mask = BIT(3) }, + { .csi = RVIN_CSI20, .channel = 3, .vin = 3, .mask = BIT(4) }, + { .csi = RVIN_CSI20, .channel = 0, .vin = 4, .mask = BIT(1) | BIT(4) }, + { .csi = RVIN_CSI20, .channel = 0, .vin = 5, .mask = BIT(0) }, + { .csi = RVIN_CSI20, .channel = 1, .vin = 5, .mask = BIT(4) }, + { .csi = RVIN_CSI20, .channel = 1, .vin = 6, .mask = BIT(0) }, + { .csi = RVIN_CSI20, .channel = 0, .vin = 6, .mask = BIT(2) }, + { .csi = RVIN_CSI20, .channel = 2, .vin = 6, .mask = BIT(4) }, + { .csi = RVIN_CSI20, .channel = 1, .vin = 7, .mask = BIT(1) | BIT(2) }, + { .csi = RVIN_CSI20, .channel = 3, .vin = 7, .mask = BIT(4) }, + { /* Sentinel */ } +}; + +static const struct rvin_info rcar_info_r8a774e1 = { + .model = RCAR_GEN3, + .use_mc = true, + .max_width = 4096, + .max_height = 4096, + .routes = rcar_info_r8a774e1_routes, +}; + static const struct rvin_group_route rcar_info_r8a7795_routes[] = { { .csi = RVIN_CSI40, .channel = 0, .vin = 0, .mask = BIT(0) | BIT(3) }, { .csi = RVIN_CSI20, .channel = 0, .vin = 0, .mask = BIT(1) | BIT(4) }, @@ -1220,6 +1256,10 @@ static const struct of_device_id rvin_of_id_table[] = { .compatible = "renesas,vin-r8a774c0", .data = &rcar_info_r8a77990, }, + { + .compatible = "renesas,vin-r8a774e1", + .data = &rcar_info_r8a774e1, + }, { .compatible = "renesas,vin-r8a7778", .data = &rcar_info_m1,
Hi Lad,
Thanks for your work.
On 2020-07-16 18:18:34 +0100, Lad Prabhakar wrote:
Add the SoC specific information for RZ/G2H (R8A774E1) SoC. Also add the routing information between CSI2 and VIN (which is similar to R-Car H3 except it lacks CSI41).
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com
I do not have access to the datasheet so I can't verify the routing table so I trust it is correct.
Reviewed-by: Niklas Söderlund niklas.soderlund+renesas@ragnatech.se
drivers/media/platform/rcar-vin/rcar-core.c | 40 +++++++++++++++++++++ 1 file changed, 40 insertions(+)
diff --git a/drivers/media/platform/rcar-vin/rcar-core.c b/drivers/media/platform/rcar-vin/rcar-core.c index 7440c8965d27..4fb76d1df308 100644 --- a/drivers/media/platform/rcar-vin/rcar-core.c +++ b/drivers/media/platform/rcar-vin/rcar-core.c @@ -944,6 +944,42 @@ static const struct rvin_info rcar_info_gen2 = { .max_height = 2048, };
+static const struct rvin_group_route rcar_info_r8a774e1_routes[] = {
- { .csi = RVIN_CSI40, .channel = 0, .vin = 0, .mask = BIT(0) | BIT(3) },
- { .csi = RVIN_CSI20, .channel = 0, .vin = 0, .mask = BIT(1) | BIT(4) },
- { .csi = RVIN_CSI40, .channel = 1, .vin = 0, .mask = BIT(2) },
- { .csi = RVIN_CSI20, .channel = 0, .vin = 1, .mask = BIT(0) },
- { .csi = RVIN_CSI40, .channel = 1, .vin = 1, .mask = BIT(1) | BIT(3) },
- { .csi = RVIN_CSI40, .channel = 0, .vin = 1, .mask = BIT(2) },
- { .csi = RVIN_CSI20, .channel = 1, .vin = 1, .mask = BIT(4) },
- { .csi = RVIN_CSI20, .channel = 1, .vin = 2, .mask = BIT(0) },
- { .csi = RVIN_CSI40, .channel = 0, .vin = 2, .mask = BIT(1) },
- { .csi = RVIN_CSI20, .channel = 0, .vin = 2, .mask = BIT(2) },
- { .csi = RVIN_CSI40, .channel = 2, .vin = 2, .mask = BIT(3) },
- { .csi = RVIN_CSI20, .channel = 2, .vin = 2, .mask = BIT(4) },
- { .csi = RVIN_CSI40, .channel = 1, .vin = 3, .mask = BIT(0) },
- { .csi = RVIN_CSI20, .channel = 1, .vin = 3, .mask = BIT(1) | BIT(2) },
- { .csi = RVIN_CSI40, .channel = 3, .vin = 3, .mask = BIT(3) },
- { .csi = RVIN_CSI20, .channel = 3, .vin = 3, .mask = BIT(4) },
- { .csi = RVIN_CSI20, .channel = 0, .vin = 4, .mask = BIT(1) | BIT(4) },
- { .csi = RVIN_CSI20, .channel = 0, .vin = 5, .mask = BIT(0) },
- { .csi = RVIN_CSI20, .channel = 1, .vin = 5, .mask = BIT(4) },
- { .csi = RVIN_CSI20, .channel = 1, .vin = 6, .mask = BIT(0) },
- { .csi = RVIN_CSI20, .channel = 0, .vin = 6, .mask = BIT(2) },
- { .csi = RVIN_CSI20, .channel = 2, .vin = 6, .mask = BIT(4) },
- { .csi = RVIN_CSI20, .channel = 1, .vin = 7, .mask = BIT(1) | BIT(2) },
- { .csi = RVIN_CSI20, .channel = 3, .vin = 7, .mask = BIT(4) },
- { /* Sentinel */ }
+};
+static const struct rvin_info rcar_info_r8a774e1 = {
- .model = RCAR_GEN3,
- .use_mc = true,
- .max_width = 4096,
- .max_height = 4096,
- .routes = rcar_info_r8a774e1_routes,
+};
static const struct rvin_group_route rcar_info_r8a7795_routes[] = { { .csi = RVIN_CSI40, .channel = 0, .vin = 0, .mask = BIT(0) | BIT(3) }, { .csi = RVIN_CSI20, .channel = 0, .vin = 0, .mask = BIT(1) | BIT(4) }, @@ -1220,6 +1256,10 @@ static const struct of_device_id rvin_of_id_table[] = { .compatible = "renesas,vin-r8a774c0", .data = &rcar_info_r8a77990, },
- {
.compatible = "renesas,vin-r8a774e1",.data = &rcar_info_r8a774e1,- }, { .compatible = "renesas,vin-r8a7778", .data = &rcar_info_m1,
-- 2.17.1
Add VIN and CSI-2 nodes to RZ/G2H (R8A774E1) SoC dtsi.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com --- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 334 ++++++++++++++++++++++ 1 file changed, 334 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index ce9e5615b932..bd87c4c4dcaf 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -1415,6 +1415,246 @@ status = "disabled"; };
+ vin0: video@e6ef0000 { + compatible = "renesas,vin-r8a774e1"; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 811>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 811>; + renesas,id = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin0csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin0>; + }; + vin0csi40: endpoint@2 { + reg = <2>; + remote-endpoint = <&csi40vin0>; + }; + }; + }; + }; + + vin1: video@e6ef1000 { + compatible = "renesas,vin-r8a774e1"; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 810>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 810>; + renesas,id = <1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin1csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin1>; + }; + vin1csi40: endpoint@2 { + reg = <2>; + remote-endpoint = <&csi40vin1>; + }; + }; + }; + }; + + vin2: video@e6ef2000 { + compatible = "renesas,vin-r8a774e1"; + reg = <0 0xe6ef2000 0 0x1000>; + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 809>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 809>; + renesas,id = <2>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin2csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin2>; + }; + vin2csi40: endpoint@2 { + reg = <2>; + remote-endpoint = <&csi40vin2>; + }; + }; + }; + }; + + vin3: video@e6ef3000 { + compatible = "renesas,vin-r8a774e1"; + reg = <0 0xe6ef3000 0 0x1000>; + interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 808>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 808>; + renesas,id = <3>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin3csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin3>; + }; + vin3csi40: endpoint@2 { + reg = <2>; + remote-endpoint = <&csi40vin3>; + }; + }; + }; + }; + + vin4: video@e6ef4000 { + compatible = "renesas,vin-r8a774e1"; + reg = <0 0xe6ef4000 0 0x1000>; + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 807>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 807>; + renesas,id = <4>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin4csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin4>; + }; + }; + }; + }; + + vin5: video@e6ef5000 { + compatible = "renesas,vin-r8a774e1"; + reg = <0 0xe6ef5000 0 0x1000>; + interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 806>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 806>; + renesas,id = <5>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin5csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin5>; + }; + }; + }; + }; + + vin6: video@e6ef6000 { + compatible = "renesas,vin-r8a774e1"; + reg = <0 0xe6ef6000 0 0x1000>; + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 805>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 805>; + renesas,id = <6>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin6csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin6>; + }; + }; + }; + }; + + vin7: video@e6ef7000 { + compatible = "renesas,vin-r8a774e1"; + reg = <0 0xe6ef7000 0 0x1000>; + interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 804>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 804>; + renesas,id = <7>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin7csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin7>; + }; + }; + }; + }; + rcar_sound: sound@ec500000 { /* * #sound-dai-cells is required @@ -2136,6 +2376,100 @@ status = "disabled"; };
+ csi20: csi2@fea80000 { + compatible = "renesas,r8a774e1-csi2"; + reg = <0 0xfea80000 0 0x10000>; + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 714>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 714>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + csi20vin0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vin0csi20>; + }; + csi20vin1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vin1csi20>; + }; + csi20vin2: endpoint@2 { + reg = <2>; + remote-endpoint = <&vin2csi20>; + }; + csi20vin3: endpoint@3 { + reg = <3>; + remote-endpoint = <&vin3csi20>; + }; + csi20vin4: endpoint@4 { + reg = <4>; + remote-endpoint = <&vin4csi20>; + }; + csi20vin5: endpoint@5 { + reg = <5>; + remote-endpoint = <&vin5csi20>; + }; + csi20vin6: endpoint@6 { + reg = <6>; + remote-endpoint = <&vin6csi20>; + }; + csi20vin7: endpoint@7 { + reg = <7>; + remote-endpoint = <&vin7csi20>; + }; + }; + }; + }; + + csi40: csi2@feaa0000 { + compatible = "renesas,r8a774e1-csi2"; + reg = <0 0xfeaa0000 0 0x10000>; + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 716>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 716>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + csi40vin0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vin0csi40>; + }; + csi40vin1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vin1csi40>; + }; + csi40vin2: endpoint@2 { + reg = <2>; + remote-endpoint = <&vin2csi40>; + }; + csi40vin3: endpoint@3 { + reg = <3>; + remote-endpoint = <&vin3csi40>; + }; + }; + }; + }; + hdmi0: hdmi@fead0000 { reg = <0 0xfead0000 0 0x10000>; status = "disabled";
Hi Prabhakar,
On Thu, Jul 16, 2020 at 7:20 PM Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com wrote:
Add VIN and CSI-2 nodes to RZ/G2H (R8A774E1) SoC dtsi.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com
Reviewed-by: Geert Uytterhoeven geert+renesas@glider.be
However, before I queue this in renesas-devel for v5.10, I'd like to have some clarification about the issue below.
--- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
vin4: video@e6ef4000 {compatible = "renesas,vin-r8a774e1";reg = <0 0xe6ef4000 0 0x1000>;interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 807>;power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;resets = <&cpg 807>;renesas,id = <4>;status = "disabled";ports {#address-cells = <1>;#size-cells = <0>;port@1 {#address-cells = <1>;#size-cells = <0>;
"make dtbs W=1" says:
arch/arm64/boot/dts/renesas/r8a774e1.dtsi:1562.12-1572.7: Warning (graph_child_address): /soc/video@e6ef4000/ports/port@1: graph node has single child node 'endpoint@0', #address-cells/#size-cells are not necessary
(same for vin5-7 below)
reg = <1>;vin4csi20: endpoint@0 {reg = <0>;remote-endpoint = <&csi20vin4>;};
Gr{oetje,eeting}s,
Geert
-- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Geert,
Thank you for the review.
On Wed, Aug 5, 2020 at 12:19 PM Geert Uytterhoeven geert@linux-m68k.org wrote:
Hi Prabhakar,
On Thu, Jul 16, 2020 at 7:20 PM Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com wrote:
Add VIN and CSI-2 nodes to RZ/G2H (R8A774E1) SoC dtsi.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com
Reviewed-by: Geert Uytterhoeven geert+renesas@glider.be
However, before I queue this in renesas-devel for v5.10, I'd like to have some clarification about the issue below.
--- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
vin4: video@e6ef4000 {compatible = "renesas,vin-r8a774e1";reg = <0 0xe6ef4000 0 0x1000>;interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 807>;power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;resets = <&cpg 807>;renesas,id = <4>;status = "disabled";ports {#address-cells = <1>;#size-cells = <0>;port@1 {#address-cells = <1>;#size-cells = <0>;"make dtbs W=1" says:
arch/arm64/boot/dts/renesas/r8a774e1.dtsi:1562.12-1572.7: Warning(graph_child_address): /soc/video@e6ef4000/ports/port@1: graph node has single child node 'endpoint@0', #address-cells/#size-cells are not necessary
(same for vin5-7 below)
Referring to commit 5e53dbf4edb4d ("arm64: dts: renesas: r8a77990: Fix VIN endpoint numbering") we definitely need endpoint numbering. Probably the driver needs to be fixed to handle such cases.
Cheers, Prabhakar
reg = <1>;vin4csi20: endpoint@0 {reg = <0>;remote-endpoint = <&csi20vin4>;};Gr{oetje,eeting}s,
Geert-- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Prabhakar,
On Thu, Aug 6, 2020 at 1:17 PM Lad, Prabhakar prabhakar.csengg@gmail.com wrote:
On Wed, Aug 5, 2020 at 12:19 PM Geert Uytterhoeven geert@linux-m68k.org wrote:
On Thu, Jul 16, 2020 at 7:20 PM Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com wrote:
Add VIN and CSI-2 nodes to RZ/G2H (R8A774E1) SoC dtsi.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com
Reviewed-by: Geert Uytterhoeven geert+renesas@glider.be
However, before I queue this in renesas-devel for v5.10, I'd like to have some clarification about the issue below.
--- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
vin4: video@e6ef4000 {compatible = "renesas,vin-r8a774e1";reg = <0 0xe6ef4000 0 0x1000>;interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 807>;power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;resets = <&cpg 807>;renesas,id = <4>;status = "disabled";ports {#address-cells = <1>;#size-cells = <0>;port@1 {#address-cells = <1>;#size-cells = <0>;"make dtbs W=1" says:
arch/arm64/boot/dts/renesas/r8a774e1.dtsi:1562.12-1572.7: Warning(graph_child_address): /soc/video@e6ef4000/ports/port@1: graph node has single child node 'endpoint@0', #address-cells/#size-cells are not necessary
(same for vin5-7 below)
Referring to commit 5e53dbf4edb4d ("arm64: dts: renesas: r8a77990: Fix VIN endpoint numbering") we definitely need endpoint numbering. Probably the driver needs to be fixed to handle such cases.
reg = <1>;vin4csi20: endpoint@0 {reg = <0>;remote-endpoint = <&csi20vin4>;
On R-Car E3, the single endpoint is at address 2, so "make dtbs W=1"doesn't complain. Here it is at address 0.
Niklas?
Gr{oetje,eeting}s,
Geert
Hi Geert, Lad,
On 2020-08-06 13:47:58 +0200, Geert Uytterhoeven wrote:
Hi Prabhakar,
On Thu, Aug 6, 2020 at 1:17 PM Lad, Prabhakar prabhakar.csengg@gmail.com wrote:
On Wed, Aug 5, 2020 at 12:19 PM Geert Uytterhoeven geert@linux-m68k.org wrote:
On Thu, Jul 16, 2020 at 7:20 PM Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com wrote:
Add VIN and CSI-2 nodes to RZ/G2H (R8A774E1) SoC dtsi.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com
Reviewed-by: Geert Uytterhoeven geert+renesas@glider.be
However, before I queue this in renesas-devel for v5.10, I'd like to have some clarification about the issue below.
--- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
vin4: video@e6ef4000 {compatible = "renesas,vin-r8a774e1";reg = <0 0xe6ef4000 0 0x1000>;interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 807>;power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;resets = <&cpg 807>;renesas,id = <4>;status = "disabled";ports {#address-cells = <1>;#size-cells = <0>;port@1 {#address-cells = <1>;#size-cells = <0>;"make dtbs W=1" says:
arch/arm64/boot/dts/renesas/r8a774e1.dtsi:1562.12-1572.7: Warning(graph_child_address): /soc/video@e6ef4000/ports/port@1: graph node has single child node 'endpoint@0', #address-cells/#size-cells are not necessary
(same for vin5-7 below)
Referring to commit 5e53dbf4edb4d ("arm64: dts: renesas: r8a77990: Fix VIN endpoint numbering") we definitely need endpoint numbering. Probably the driver needs to be fixed to handle such cases.
reg = <1>;vin4csi20: endpoint@0 {reg = <0>;remote-endpoint = <&csi20vin4>;On R-Car E3, the single endpoint is at address 2, so "make dtbs W=1"doesn't complain. Here it is at address 0.
Niklas?
First the R-Car VIN driver makes decisions based on which endpoint is described, each endpoint 0-3 represents a different CSI-2 block on the other end (0: CSI20, 1: CSI21, 2: CSI40 and 3: CSI41).
Then how to handle the warning I'm not sure. I can only really see 2 options.
1. Ignore the warning. 2. Remove #address-cells, #size-cells and reg properties from port@ if the only endpoint described is endpoint@0.
I would prefers option 2. that is what we do in other cases (for example on Gen2 boards that only have a single parallel sensor in some early DTS files we don't have the ports node and just describe a single port with the same reasoning.
We are not at risk at someone describing a second CSI-2 bock as an overlay so I see no real harm in option 2. What are your thoughts Geert? You know more about DT then me.
Gr{oetje,eeting}s,
Geert-- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Niklas,
On Fri, Aug 7, 2020 at 1:27 PM Niklas Söderlund niklas.soderlund@ragnatech.se wrote:
On 2020-08-06 13:47:58 +0200, Geert Uytterhoeven wrote:
On Thu, Aug 6, 2020 at 1:17 PM Lad, Prabhakar prabhakar.csengg@gmail.com wrote:
On Wed, Aug 5, 2020 at 12:19 PM Geert Uytterhoeven geert@linux-m68k.org wrote:
On Thu, Jul 16, 2020 at 7:20 PM Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com wrote:
Add VIN and CSI-2 nodes to RZ/G2H (R8A774E1) SoC dtsi.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com
Reviewed-by: Geert Uytterhoeven geert+renesas@glider.be
However, before I queue this in renesas-devel for v5.10, I'd like to have some clarification about the issue below.
--- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
vin4: video@e6ef4000 {compatible = "renesas,vin-r8a774e1";reg = <0 0xe6ef4000 0 0x1000>;interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 807>;power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;resets = <&cpg 807>;renesas,id = <4>;status = "disabled";ports {#address-cells = <1>;#size-cells = <0>;port@1 {#address-cells = <1>;#size-cells = <0>;"make dtbs W=1" says:
arch/arm64/boot/dts/renesas/r8a774e1.dtsi:1562.12-1572.7: Warning(graph_child_address): /soc/video@e6ef4000/ports/port@1: graph node has single child node 'endpoint@0', #address-cells/#size-cells are not necessary
(same for vin5-7 below)
Referring to commit 5e53dbf4edb4d ("arm64: dts: renesas: r8a77990: Fix VIN endpoint numbering") we definitely need endpoint numbering. Probably the driver needs to be fixed to handle such cases.
reg = <1>;vin4csi20: endpoint@0 {reg = <0>;remote-endpoint = <&csi20vin4>;On R-Car E3, the single endpoint is at address 2, so "make dtbs W=1"doesn't complain. Here it is at address 0.
Niklas?
First the R-Car VIN driver makes decisions based on which endpoint is described, each endpoint 0-3 represents a different CSI-2 block on the other end (0: CSI20, 1: CSI21, 2: CSI40 and 3: CSI41).
That's my understanding, too.
Then how to handle the warning I'm not sure. I can only really see 2 options.
- Ignore the warning.
- Remove #address-cells, #size-cells and reg properties from port@ if the only endpoint described is endpoint@0.
I would prefers option 2. that is what we do in other cases (for example on Gen2 boards that only have a single parallel sensor in some early DTS files we don't have the ports node and just describe a single port with the same reasoning.
We are not at risk at someone describing a second CSI-2 bock as an overlay so I see no real harm in option 2.
Yeah, no overlay possible for on-SoC wiring ;-)
What are your thoughts Geert? You know more about DT then me.
You have too much faith in me ;-)
AFAIK we don't get this warning for e.g. SPI buses, which can have a single device at address 0, and #{address,size}-cells is mandatory there. So endpoints (or SPI?) are treated special?
Gr{oetje,eeting}s,
Geert
Hi Geert and Lad,
On 2020-08-07 13:36:46 +0200, Geert Uytterhoeven wrote:
Hi Niklas,
On Fri, Aug 7, 2020 at 1:27 PM Niklas Söderlund niklas.soderlund@ragnatech.se wrote:
On 2020-08-06 13:47:58 +0200, Geert Uytterhoeven wrote:
On Thu, Aug 6, 2020 at 1:17 PM Lad, Prabhakar prabhakar.csengg@gmail.com wrote:
On Wed, Aug 5, 2020 at 12:19 PM Geert Uytterhoeven geert@linux-m68k.org wrote:
On Thu, Jul 16, 2020 at 7:20 PM Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com wrote:
Add VIN and CSI-2 nodes to RZ/G2H (R8A774E1) SoC dtsi.
Signed-off-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Reviewed-by: Marian-Cristian Rotariu marian-cristian.rotariu.rb@bp.renesas.com
Reviewed-by: Geert Uytterhoeven geert+renesas@glider.be
However, before I queue this in renesas-devel for v5.10, I'd like to have some clarification about the issue below.
--- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
vin4: video@e6ef4000 {compatible = "renesas,vin-r8a774e1";reg = <0 0xe6ef4000 0 0x1000>;interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 807>;power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;resets = <&cpg 807>;renesas,id = <4>;status = "disabled";ports {#address-cells = <1>;#size-cells = <0>;port@1 {#address-cells = <1>;#size-cells = <0>;"make dtbs W=1" says:
arch/arm64/boot/dts/renesas/r8a774e1.dtsi:1562.12-1572.7: Warning(graph_child_address): /soc/video@e6ef4000/ports/port@1: graph node has single child node 'endpoint@0', #address-cells/#size-cells are not necessary
(same for vin5-7 below)
Referring to commit 5e53dbf4edb4d ("arm64: dts: renesas: r8a77990: Fix VIN endpoint numbering") we definitely need endpoint numbering. Probably the driver needs to be fixed to handle such cases.
reg = <1>;vin4csi20: endpoint@0 {reg = <0>;remote-endpoint = <&csi20vin4>;On R-Car E3, the single endpoint is at address 2, so "make dtbs W=1"doesn't complain. Here it is at address 0.
Niklas?
First the R-Car VIN driver makes decisions based on which endpoint is described, each endpoint 0-3 represents a different CSI-2 block on the other end (0: CSI20, 1: CSI21, 2: CSI40 and 3: CSI41).
That's my understanding, too.
Then how to handle the warning I'm not sure. I can only really see 2 options.
- Ignore the warning.
- Remove #address-cells, #size-cells and reg properties from port@ if the only endpoint described is endpoint@0.
I would prefers option 2. that is what we do in other cases (for example on Gen2 boards that only have a single parallel sensor in some early DTS files we don't have the ports node and just describe a single port with the same reasoning.
We are not at risk at someone describing a second CSI-2 bock as an overlay so I see no real harm in option 2.
Yeah, no overlay possible for on-SoC wiring ;-)
What are your thoughts Geert? You know more about DT then me.
You have too much faith in me ;-)
AFAIK we don't get this warning for e.g. SPI buses, which can have a single device at address 0, and #{address,size}-cells is mandatory there. So endpoints (or SPI?) are treated special?
That is a good question, I don't know if either of those are treated special. Lad could you look into this?
Gr{oetje,eeting}s,
Geert-- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
On Thu, 16 Jul 2020 18:18:15 +0100, Lad Prabhakar wrote:
This patch series adds support for the following peripherals on RZ/G2H SoC
- PCIe
- SATA
- USB2
- USB3
- Audio
- VIN
- CSI
[...]
Applied to
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next
Thanks!
[1/1] dt-bindings: sound: renesas, rsnd: Document r8a774e1 bindings commit: 92e37407811b98a7eb54eb6a6b3d65847a46e0e6
All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying to this mail.
Thanks, Mark
participants (11)
-
Geert Uytterhoeven -
Greg Kroah-Hartman -
Lad Prabhakar -
Lad, Prabhakar -
Mark Brown -
Niklas -
Niklas Söderlund
-
Rob Herring -
Vinod Koul -
Wolfram Sang -
Yoshihiro Shimoda