[alsa-devel] ASOC: For SND_SOC_DAIFMT_IB_IF what is invert baseed on?
Hi,
include/sound/soc.h /* * DAI hardware signal inversions */ #define SND_SOC_DAIFMT_NB_NF (0 << 8) /* normal bclk + frm */ #define SND_SOC_DAIFMT_NB_IF (1 << 8) /* normal bclk + inv frm */ #define SND_SOC_DAIFMT_IB_NF (2 << 8) /* invert bclk + nor frm */ #define SND_SOC_DAIFMT_IB_IF (3 << 8) /* invert bclk + frm */
What are frame cock and bit clock invert based on? I2S, PCM or some else bus protocols? Or just high level voltage or low level voltage?
Thanks Richard
On Sun, 2008-10-26 at 00:31 +0800, Richard Zhao wrote:
Hi,
include/sound/soc.h /*
- DAI hardware signal inversions
*/ #define SND_SOC_DAIFMT_NB_NF (0 << 8) /* normal bclk + frm */ #define SND_SOC_DAIFMT_NB_IF (1 << 8) /* normal bclk
- inv frm */
#define SND_SOC_DAIFMT_IB_NF (2 << 8) /* invert bclk
- nor frm */
#define SND_SOC_DAIFMT_IB_IF (3 << 8) /* invert bclk + frm */
What are frame cock and bit clock invert based on? I2S, PCM or some else bus protocols? Or just high level voltage or low level voltage?
Generic logic levels (high/low voltage) that can apply to I2S and PCM DAI's.
Liam
2008/10/27 Liam Girdwood lrg@slimlogic.co.uk:
On Sun, 2008-10-26 at 00:31 +0800, Richard Zhao wrote:
Hi,
include/sound/soc.h /*
- DAI hardware signal inversions
*/ #define SND_SOC_DAIFMT_NB_NF (0 << 8) /* normal bclk + frm */ #define SND_SOC_DAIFMT_NB_IF (1 << 8) /* normal bclk
- inv frm */
#define SND_SOC_DAIFMT_IB_NF (2 << 8) /* invert bclk
- nor frm */
#define SND_SOC_DAIFMT_IB_IF (3 << 8) /* invert bclk + frm */
What are frame cock and bit clock invert based on? I2S, PCM or some else bus protocols? Or just high level voltage or low level voltage?
Generic logic levels (high/low voltage) that can apply to I2S and PCM DAI's.
Liam
It's not bus protocol depended. For frame start, LRCLK normal is 1, invert is 0. For data valid, BCLK normal is 1, invert is 0 Is that what you meant?
But when wm8350 in i2s mode, it take SND_SOC_DAIFMT_NB_NF as LRCLK is 0 for frame start.
Thanks Richard
On Mon, 2008-10-27 at 11:00 +0800, Richard Zhao wrote:
2008/10/27 Liam Girdwood lrg@slimlogic.co.uk:
On Sun, 2008-10-26 at 00:31 +0800, Richard Zhao wrote:
Hi,
include/sound/soc.h /*
- DAI hardware signal inversions
*/ #define SND_SOC_DAIFMT_NB_NF (0 << 8) /* normal bclk + frm */ #define SND_SOC_DAIFMT_NB_IF (1 << 8) /* normal bclk
- inv frm */
#define SND_SOC_DAIFMT_IB_NF (2 << 8) /* invert bclk
- nor frm */
#define SND_SOC_DAIFMT_IB_IF (3 << 8) /* invert bclk + frm */
What are frame cock and bit clock invert based on? I2S, PCM or some else bus protocols? Or just high level voltage or low level voltage?
Generic logic levels (high/low voltage) that can apply to I2S and PCM DAI's.
Liam
It's not bus protocol depended.
Correct, it does not depend on bus protocol. Although, it wont apply to well defined protocols like AC97.
For frame start, LRCLK normal is 1, invert is 0. For data valid, BCLK normal is 1, invert is 0 Is that what you meant?
Not quite, the clock is simply inverted compared to it's normal level.
But when wm8350 in i2s mode, it take SND_SOC_DAIFMT_NB_NF as LRCLK is 0 for frame start.
I2S frame start is the LRC going high (from low) to indicate left channel PCM data is available after the next bit clock.
Do you have another issue that is causing you to check clock inversions ? Fwiw the wm8350 audio is mature and known to be working for some time.
Liam
On Mon, 2008-10-27 at 10:46 +0000, Liam Girdwood wrote:
On Mon, 2008-10-27 at 11:00 +0800, Richard Zhao wrote:
But when wm8350 in i2s mode, it take SND_SOC_DAIFMT_NB_NF as LRCLK is 0 for frame start.
I2S frame start is the LRC going high (from low) to indicate left channel PCM data is available after the next bit clock.
Correction. I've just noticed my datasheet is wrong here.
I2S LRC Left = low, right = high.
So frame start is LRC going low from high.
Liam
Not quite, the clock is simply inverted compared to it's normal level.
Well, what's the normal level? i2s LRCLK 's normal level is low for frame start, but pcm's normal level is high for frame start.
Different chips may have different meaning of "invert", because "normal level" is not well defined. SND_SOC_DAIFMT_NB_NF is a common macro, so it cannot depend on any chip. So, could you please explain in details what normal level and invert level of LRCLK/BCLK are in i2s, pcm, left/right justified?
Yes, wm8350 audio driver works. The problem is, when I write drivers from some cpu/codec DAIs, I'm often confused about the normal/invert levels.
Thanks Richard
On Mon, 2008-10-27 at 21:24 +0800, Richard Zhao wrote:
Not quite, the clock is simply inverted compared to it's normal level.
Well, what's the normal level? i2s LRCLK 's normal level is low for frame start, but pcm's normal level is high for frame start.
Different chips may have different meaning of "invert", because "normal level" is not well defined.
normal == standard.
I2S spec is here :-
http://www.nxp.com/acrobat_download/various/I2SBUS.pdf
and is well defined.
SND_SOC_DAIFMT_NB_NF is a common macro, so it cannot depend on any chip. So, could you please explain in details what normal level and invert level of LRCLK/BCLK are in i2s, pcm, left/right justified?
The wm8750 datasheet shows all this in diagrams :-
http://www.wolfsonmicro.com/uploads/documents/WM8750.pdf
It might be easier if you would send in your code so we can see what you are trying to accomplish.
Liam
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Richard Zhao