On Fri, 25 Sep 2009 07:31:47 -0700 Rick Bronson rick@efn.org wrote:

Hi Peter,

I forgot to tell you that if I deliberately misconfigure the McBXP_CLKS pin so that it's an output, the FSX -> DACLRC/ADCLRC signal stops. This should indicate that the CLKOUT signal is actually making it to the CLKS pin on the OMAP. Right?

Yes it is indicating so. I read through this thread I didn't find any simple reason why it's not working. Your setup is similar with the Pandora, i.e. McBSP functional clock is coming the codec and codec is slave.

The McBSP is operating if the FSX and CLKX are toggling in this setup. Is it so that you don't get any DMA interrupts or just few of them? Your CLKGDV divisor value 256 means too low bit clock and sample rate for both external 12.288 MHz and internal 96 MHz but still the DMA should be running (if there is no bug with this divisor value).

Can you try divisor value 8 does it work then? For 48 kHz sample rate with I2S you need a bit clock of 48 kHz*2*16 = 1.536 MHz and this you get by dividing the 12.288 MHz with 8.