Re: [alsa-devel] [PATCH] ASoC: fsl_esai: fix the channel swap issue after xrun
Hi
Sounds like a bug to me...should fix it first by marking the data registers as volatile.
The ETDR is a writable register, it is not volatile. Even we change it to Volatile, I don't think we can't avoid this issue. for the regcache_sync Just to write this register, it is correct behavior.
Is that so? Quoting the comments of regcache_sync(): "* regcache_sync - Sync the register cache with the hardware.
- @map: map to configure.
- Any registers that should not be synced should be marked as
- volatile."
If regcache_sync() does sync volatile registers too as you said, I don't mind having this FIFO reset WAR for now, though I think this mismatch between the comments and the actual behavior then should
get people's attention.
Thank you
ETDR is not volatile, if we mark it is volatile, is it correct?
Well, you have a point -- it might not be ideally true, but it sounds like a correct fix to me according to this comments.
We can wait for Mark's comments or just send a patch to the mail list for review.
Thanks you
I test this patch, we don't need to reset the FIFO, and regcache_sync didn't Write the ETDR even the EDTR is not volatile. This fault maybe caused by Legacy, in the beginning we add this patch in internal branch, there maybe Something cause this issue, but now can't reproduced.
So I will remove the reset of FIFO.
Best regards Wang Shengjiu
Hello Shengjiu,
On Wed, Jun 05, 2019 at 10:29:37AM +0000, S.j. Wang wrote:
ETDR is not volatile, if we mark it is volatile, is it correct?
Well, you have a point -- it might not be ideally true, but it sounds like a correct fix to me according to this comments.
We can wait for Mark's comments or just send a patch to the mail list for review.
I test this patch, we don't need to reset the FIFO, and regcache_sync didn't Write the ETDR even the EDTR is not volatile. This fault maybe caused by
The fsl_esai driver uses FLAT type cache so regcache_sync() would go through regcache_default_sync() that would bypass cache sync at the regcache_reg_needs_sync() check when the cached register value matches its default value: in case of ETDR who has a default value 0x0, it'd just "continue" without doing that _regmap_write() when the cached value equals to 0x0.
Legacy, in the beginning we add this patch in internal branch, there maybe Something cause this issue, but now can't reproduced.
The "legacy" case might happen to have two mismatched ETDR values between the cached value and default 0x0. And I am worried it may appear once again someday.
So I feel we still need to change ETDR to volatile type. And for your question "ETDR is not volatile, if we mark it is volatile, is it correct?", I double checked the definition of volatile_reg, and it says: * @volatile_reg: Optional callback returning true if the register * value can't be cached. If this field is NULL but
So it seems correct to me then, as the "volatile" should be also transcribed as "non-cacheable".
Thanks Nicolin
participants (2)
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Nicolin Chen -
S.j. Wang