[PATCH 0/8] Tegra186 and Tegra194 audio graph card
This series adds support for audio graph based solution on Tegra186 and Tegra194. This enables audio paths for I2S, DMIC and DSPK modules.
Depending on the platform Jetson TX2 or Jetson AGX Xavier, required I/O module instances are enabled. Since the latter board has on board audio codec, DT support for the same is enabled and external audio playback and capture can be used.
Sameer Pujar (8): ASoC: dt-bindings: rt5659: Update binding doc ASoC: dt-bindings: tegra: Add iommus property to Tegra graph card ASoC: audio-graph-card: Add clocks property to endpoint node ASoC: tegra: Select SND_SOC_RT5659 arm64: tegra: Add RT5658 device entry Revert "arm64: tegra: Disable the ACONNECT for Jetson TX2" arm64: tegra: Audio graph sound card for Jetson TX2 arm64: tegra: Audio graph sound card for Jetson AGX Xavier
.../bindings/sound/audio-graph-port.yaml | 3 + .../sound/nvidia,tegra-audio-graph-card.yaml | 3 + Documentation/devicetree/bindings/sound/rt5659.txt | 11 + arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 609 +++++++++++++++++++++ arch/arm64/boot/dts/nvidia/tegra186.dtsi | 22 + arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts | 468 ++++++++++++++++ arch/arm64/boot/dts/nvidia/tegra194.dtsi | 20 + sound/soc/tegra/Kconfig | 1 + 8 files changed, 1137 insertions(+)
Update following in rt5659.txt binding doc - Add JD source for Intel HDA header: Commit 041e74b71491 ("ASoC: rt5659: Add the support of Intel HDA Header") added driver support. Add missing info here.
- sound-name-prefix: Used to prefix component widgets/kcontrols with given prefix.
- ports: Helps to use the Codec with audio graph card
Signed-off-by: Sameer Pujar spujar@nvidia.com Reported-by: Jon Hunter jonathanh@nvidia.com Cc: Oder Chiou oder_chiou@realtek.com Cc: Bard Liao bardliao@realtek.com --- Documentation/devicetree/bindings/sound/rt5659.txt | 11 +++++++++++ 1 file changed, 11 insertions(+)
diff --git a/Documentation/devicetree/bindings/sound/rt5659.txt b/Documentation/devicetree/bindings/sound/rt5659.txt index 56788f5..c473df5 100644 --- a/Documentation/devicetree/bindings/sound/rt5659.txt +++ b/Documentation/devicetree/bindings/sound/rt5659.txt @@ -37,10 +37,21 @@ Optional properties: - realtek,jd-src 0: No JD is used 1: using JD3 as JD source + 2: JD source for Intel HDA header
- realtek,ldo1-en-gpios : The GPIO that controls the CODEC's LDO1_EN pin. - realtek,reset-gpios : The GPIO that controls the CODEC's RESET pin.
+- sound-name-prefix: Please refer to name-prefix.txt + +- ports: A Codec may have a single or multiple I2S interfaces. These + interfaces on Codec side can be described under 'ports' or 'port'. + When the SoC or host device is connected to multiple interfaces of + the Codec, the connectivity can be described using 'ports' property. + If a single interface is used, then 'port' can be used. The usage + depends on the platform or board design. + Please refer to Documentation/devicetree/bindings/graph.txt + Pins on the device (for linking into audio routes) for RT5659/RT5658:
* DMIC L1
Document 'iommus' property for APE (Audio Processing Engine) sound card.
Signed-off-by: Sameer Pujar spujar@nvidia.com --- .../devicetree/bindings/sound/nvidia,tegra-audio-graph-card.yaml | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-graph-card.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-graph-card.yaml index fc271f6..2499709 100644 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-graph-card.yaml +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-graph-card.yaml @@ -45,6 +45,9 @@ properties: minItems: 1 maxItems: 3
+ iommus: + maxItems: 1 + required: - clocks - clock-names
Add optional 'clocks' property to audio port 'endpoint' node. One such example is where SoC supplies a clock to external audio codec component.
Signed-off-by: Sameer Pujar spujar@nvidia.com Cc: Kuninori Morimoto kuninori.morimoto.gx@renesas.com Reviewed-by: Jon Hunter jonathanh@nvidia.com --- Documentation/devicetree/bindings/sound/audio-graph-port.yaml | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/sound/audio-graph-port.yaml b/Documentation/devicetree/bindings/sound/audio-graph-port.yaml index 766e910..08ed8f5 100644 --- a/Documentation/devicetree/bindings/sound/audio-graph-port.yaml +++ b/Documentation/devicetree/bindings/sound/audio-graph-port.yaml @@ -33,6 +33,9 @@ properties: properties: remote-endpoint: maxItems: 1 + clocks: + maxItems: 1 + description: Describes the clock used by audio component. mclk-fs: description: | Multiplication factor between stream rate and codec mclk.
Select SND_SOC_RT5659 to verify external audio over Jetson platforms. Jetson AGX Xavier has an on-board RT5658 audio codec and to use this enable required config.
Signed-off-by: Sameer Pujar spujar@nvidia.com Reviewed-by: Jonathan Hunter jonathanh@nvidia.com --- sound/soc/tegra/Kconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/sound/soc/tegra/Kconfig b/sound/soc/tegra/Kconfig index 6dc83ad..4a45163 100644 --- a/sound/soc/tegra/Kconfig +++ b/sound/soc/tegra/Kconfig @@ -120,6 +120,7 @@ config SND_SOC_TEGRA210_ADMAIF config SND_SOC_TEGRA_AUDIO_GRAPH_CARD tristate "Audio Graph Card based Tegra driver" depends on SND_AUDIO_GRAPH_CARD + select SND_SOC_RT5659 help Config to enable Tegra audio machine driver based on generic audio graph driver. It is a thin driver written to customize
On Fri, Jan 29, 2021 at 05:11:06PM +0530, Sameer Pujar wrote:
Select SND_SOC_RT5659 to verify external audio over Jetson platforms. Jetson AGX Xavier has an on-board RT5658 audio codec and to use this enable required config.
config SND_SOC_TEGRA_AUDIO_GRAPH_CARD tristate "Audio Graph Card based Tegra driver" depends on SND_AUDIO_GRAPH_CARD
- select SND_SOC_RT5659 help
This is a generic device, not something specific to Jetson, why force on a driver that may not be required on other boards using this driver?
On 1/29/2021 6:14 PM, Mark Brown wrote:
On Fri, Jan 29, 2021 at 05:11:06PM +0530, Sameer Pujar wrote:
Select SND_SOC_RT5659 to verify external audio over Jetson platforms. Jetson AGX Xavier has an on-board RT5658 audio codec and to use this enable required config.
config SND_SOC_TEGRA_AUDIO_GRAPH_CARD tristate "Audio Graph Card based Tegra driver" depends on SND_AUDIO_GRAPH_CARD
- select SND_SOC_RT5659 help
This is a generic device, not something specific to Jetson, why force on a driver that may not be required on other boards using this driver?
Yes specific boards using 'SND_SOC_TEGRA_AUDIO_GRAPH_CARD' may require 'SND_SOC_RT5659'. But there is no platform specific config. Is there a better way to enable config 'SND_SOC_RT5659' conditionally?
On Fri, Jan 29, 2021 at 09:02:52PM +0530, Sameer Pujar wrote:
On 1/29/2021 6:14 PM, Mark Brown wrote:
This is a generic device, not something specific to Jetson, why force on a driver that may not be required on other boards using this driver?
Yes specific boards using 'SND_SOC_TEGRA_AUDIO_GRAPH_CARD' may require 'SND_SOC_RT5659'. But there is no platform specific config. Is there a better way to enable config 'SND_SOC_RT5659' conditionally?
If the user wants a given CODEC driver then they should enable that driver.
On 1/29/2021 9:18 PM, Mark Brown wrote:
On Fri, Jan 29, 2021 at 09:02:52PM +0530, Sameer Pujar wrote:
On 1/29/2021 6:14 PM, Mark Brown wrote:
This is a generic device, not something specific to Jetson, why force on a driver that may not be required on other boards using this driver?
Yes specific boards using 'SND_SOC_TEGRA_AUDIO_GRAPH_CARD' may require 'SND_SOC_RT5659'. But there is no platform specific config. Is there a better way to enable config 'SND_SOC_RT5659' conditionally?
If the user wants a given CODEC driver then they should enable that driver.
Above card driver is intended to be used on multiple platforms. DT has already a way for user to describe the CODEC connection required for specific platform. So idea is enable these CODECs from driver point of view for this card driver and platform DT can use what is required. Also the CODEC driver will be a loadable module here.
If above does not seem fine, alternatively can I just enable CODEC config independently from defconfig?
On Fri, Jan 29, 2021 at 10:15:51PM +0530, Sameer Pujar wrote:
On 1/29/2021 9:18 PM, Mark Brown wrote:
If the user wants a given CODEC driver then they should enable that driver.
Above card driver is intended to be used on multiple platforms. DT has already a way for user to describe the CODEC connection required for specific platform. So idea is enable these CODECs from driver point of view for this card driver and platform DT can use what is required. Also the CODEC driver will be a loadable module here.
No, you're missing the point of a generic driver here. This will mean that if someone wants to build the driver into the kernel for their embedded board they will be forced to build in every CODEC driver someone has decided might be used with this generic driver, and even if they're building things modular someone trying to cut down the size of their kernel images is going to at least have to spend time building CODEC drivers they don't want to use. Distributions should just select all the CODEC drivers that are available in Kconfig, people configuring for a particular target audience should be able to build only the drivers they know they need.
If above does not seem fine, alternatively can I just enable CODEC config independently from defconfig?
Yes.
On 1/29/2021 10:49 PM, Mark Brown wrote:
On Fri, Jan 29, 2021 at 10:15:51PM +0530, Sameer Pujar wrote:
On 1/29/2021 9:18 PM, Mark Brown wrote:
If the user wants a given CODEC driver then they should enable that driver.
Above card driver is intended to be used on multiple platforms. DT has already a way for user to describe the CODEC connection required for specific platform. So idea is enable these CODECs from driver point of view for this card driver and platform DT can use what is required. Also the CODEC driver will be a loadable module here.
No, you're missing the point of a generic driver here. This will mean that if someone wants to build the driver into the kernel for their embedded board they will be forced to build in every CODEC driver someone has decided might be used with this generic driver, and even if they're building things modular someone trying to cut down the size of their kernel images is going to at least have to spend time building CODEC drivers they don't want to use. Distributions should just select all the CODEC drivers that are available in Kconfig, people configuring for a particular target audience should be able to build only the drivers they know they need.
OK, will drop this in v2. Thank you for details.
If above does not seem fine, alternatively can I just enable CODEC config independently from defconfig?
Yes.
Jetson AGX Xavier has an on-board audio codec whicn is connected to Tegra I2S1 interface. Hence add corresponding device node for the audio codec.
Signed-off-by: Sameer Pujar spujar@nvidia.com Reviewed-by: Jon Hunter jonathanh@nvidia.com --- arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts index 8697927..36f19c9 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts @@ -41,6 +41,21 @@ status = "okay"; };
+ i2c@c250000 { + status = "okay"; + + rt5658: audio-codec@1a { + status = "okay"; + + compatible = "realtek,rt5658"; + reg = <0x1a>; + interrupt-parent = <&gpio>; + interrupts = <TEGRA194_MAIN_GPIO(S, 5) GPIO_ACTIVE_HIGH>; + realtek,jd-src = <2>; + sound-name-prefix = "CVB-RT"; + }; + }; + /* SDMMC1 (SD/MMC) */ mmc@3400000 { status = "okay";
This reverts commit fb319496935b ("arm64: tegra: Disable the ACONNECT for Jetson TX2").
Signed-off-by: Sameer Pujar spujar@nvidia.com --- arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts index 6fd2e05..7e1723e 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts @@ -10,6 +10,18 @@ model = "NVIDIA Jetson TX2 Developer Kit"; compatible = "nvidia,p2771-0000", "nvidia,tegra186";
+ aconnect { + status = "okay"; + + dma-controller@2930000 { + status = "okay"; + }; + + interrupt-controller@2a40000 { + status = "okay"; + }; + }; + i2c@3160000 { power-monitor@42 { compatible = "ti,ina3221";
Enable support for audio-graph based sound card on Jetson TX2. Based on the board design following I/O modules are enabled. * All I2S instances (I2S1 ... I2S6) * All DSPK instances (DSPK1, DSPK2) * DMIC1, DMIC2 and DMIC3
Signed-off-by: Sameer Pujar spujar@nvidia.com --- arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 597 +++++++++++++++++++++ arch/arm64/boot/dts/nvidia/tegra186.dtsi | 22 + 2 files changed, 619 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts index 7e1723e..5e59584 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts @@ -20,6 +20,580 @@ interrupt-controller@2a40000 { status = "okay"; }; + + ahub@2900800 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + xbar_admaif0_ep: endpoint { + remote-endpoint = <&admaif0_ep>; + }; + }; + port@1 { + reg = <0x1>; + xbar_admaif1_ep: endpoint { + remote-endpoint = <&admaif1_ep>; + }; + }; + port@2 { + reg = <0x2>; + xbar_admaif2_ep: endpoint { + remote-endpoint = <&admaif2_ep>; + }; + }; + port@3 { + reg = <0x3>; + xbar_admaif3_ep: endpoint { + remote-endpoint = <&admaif3_ep>; + }; + }; + port@4 { + reg = <0x4>; + xbar_admaif4_ep: endpoint { + remote-endpoint = <&admaif4_ep>; + }; + }; + port@5 { + reg = <0x5>; + xbar_admaif5_ep: endpoint { + remote-endpoint = <&admaif5_ep>; + }; + }; + port@6 { + reg = <0x6>; + xbar_admaif6_ep: endpoint { + remote-endpoint = <&admaif6_ep>; + }; + }; + port@7 { + reg = <0x7>; + xbar_admaif7_ep: endpoint { + remote-endpoint = <&admaif7_ep>; + }; + }; + port@8 { + reg = <0x8>; + xbar_admaif8_ep: endpoint { + remote-endpoint = <&admaif8_ep>; + }; + }; + port@9 { + reg = <0x9>; + xbar_admaif9_ep: endpoint { + remote-endpoint = <&admaif9_ep>; + }; + }; + port@a { + reg = <0xa>; + xbar_admaif10_ep: endpoint { + remote-endpoint = <&admaif10_ep>; + }; + }; + port@b { + reg = <0xb>; + xbar_admaif11_ep: endpoint { + remote-endpoint = <&admaif11_ep>; + }; + }; + port@c { + reg = <0xc>; + xbar_admaif12_ep: endpoint { + remote-endpoint = <&admaif12_ep>; + }; + }; + port@d { + reg = <0xd>; + xbar_admaif13_ep: endpoint { + remote-endpoint = <&admaif13_ep>; + }; + }; + port@e { + reg = <0xe>; + xbar_admaif14_ep: endpoint { + remote-endpoint = <&admaif14_ep>; + }; + }; + port@f { + reg = <0xf>; + xbar_admaif15_ep: endpoint { + remote-endpoint = <&admaif15_ep>; + }; + }; + port@10 { + reg = <0x10>; + xbar_admaif16_ep: endpoint { + remote-endpoint = <&admaif16_ep>; + }; + }; + port@11 { + reg = <0x11>; + xbar_admaif17_ep: endpoint { + remote-endpoint = <&admaif17_ep>; + }; + }; + port@12 { + reg = <0x12>; + xbar_admaif18_ep: endpoint { + remote-endpoint = <&admaif18_ep>; + }; + }; + port@13 { + reg = <0x13>; + xbar_admaif19_ep: endpoint { + remote-endpoint = <&admaif19_ep>; + }; + }; + xbar_i2s1_port: port@14 { + reg = <0x14>; + xbar_i2s1_ep: endpoint { + remote-endpoint = <&i2s1_cif_ep>; + }; + }; + xbar_i2s2_port: port@15 { + reg = <0x15>; + xbar_i2s2_ep: endpoint { + remote-endpoint = <&i2s2_cif_ep>; + }; + }; + xbar_i2s3_port: port@16 { + reg = <0x16>; + xbar_i2s3_ep: endpoint { + remote-endpoint = <&i2s3_cif_ep>; + }; + }; + xbar_i2s4_port: port@17 { + reg = <0x17>; + xbar_i2s4_ep: endpoint { + remote-endpoint = <&i2s4_cif_ep>; + }; + }; + xbar_i2s5_port: port@18 { + reg = <0x18>; + xbar_i2s5_ep: endpoint { + remote-endpoint = <&i2s5_cif_ep>; + }; + }; + xbar_i2s6_port: port@19 { + reg = <0x19>; + xbar_i2s6_ep: endpoint { + remote-endpoint = <&i2s6_cif_ep>; + }; + }; + xbar_dmic1_port: port@1a { + reg = <0x1a>; + xbar_dmic1_ep: endpoint { + remote-endpoint = <&dmic1_cif_ep>; + }; + }; + xbar_dmic2_port: port@1b { + reg = <0x1b>; + xbar_dmic2_ep: endpoint { + remote-endpoint = <&dmic2_cif_ep>; + }; + }; + xbar_dmic3_port: port@1c { + reg = <0x1c>; + xbar_dmic3_ep: endpoint { + remote-endpoint = <&dmic3_cif_ep>; + }; + }; + xbar_dspk1_port: port@1e { + reg = <0x1e>; + xbar_dspk1_ep: endpoint { + remote-endpoint = <&dspk1_cif_ep>; + }; + }; + xbar_dspk2_port: port@1f { + reg = <0x1f>; + xbar_dspk2_ep: endpoint { + remote-endpoint = <&dspk2_cif_ep>; + }; + }; + }; + + admaif@290f000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + admaif0_port: port@0 { + reg = <0x0>; + admaif0_ep: endpoint { + remote-endpoint = <&xbar_admaif0_ep>; + }; + }; + admaif1_port: port@1 { + reg = <0x1>; + admaif1_ep: endpoint { + remote-endpoint = <&xbar_admaif1_ep>; + }; + }; + admaif2_port: port@2 { + reg = <0x2>; + admaif2_ep: endpoint { + remote-endpoint = <&xbar_admaif2_ep>; + }; + }; + admaif3_port: port@3 { + reg = <0x3>; + admaif3_ep: endpoint { + remote-endpoint = <&xbar_admaif3_ep>; + }; + }; + admaif4_port: port@4 { + reg = <0x4>; + admaif4_ep: endpoint { + remote-endpoint = <&xbar_admaif4_ep>; + }; + }; + admaif5_port: port@5 { + reg = <0x5>; + admaif5_ep: endpoint { + remote-endpoint = <&xbar_admaif5_ep>; + }; + }; + admaif6_port: port@6 { + reg = <0x6>; + admaif6_ep: endpoint { + remote-endpoint = <&xbar_admaif6_ep>; + }; + }; + admaif7_port: port@7 { + reg = <0x7>; + admaif7_ep: endpoint { + remote-endpoint = <&xbar_admaif7_ep>; + }; + }; + admaif8_port: port@8 { + reg = <0x8>; + admaif8_ep: endpoint { + remote-endpoint = <&xbar_admaif8_ep>; + }; + }; + admaif9_port: port@9 { + reg = <0x9>; + admaif9_ep: endpoint { + remote-endpoint = <&xbar_admaif9_ep>; + }; + }; + admaif10_port: port@a { + reg = <0xa>; + admaif10_ep: endpoint { + remote-endpoint = <&xbar_admaif10_ep>; + }; + }; + admaif11_port: port@b { + reg = <0xb>; + admaif11_ep: endpoint { + remote-endpoint = <&xbar_admaif11_ep>; + }; + }; + admaif12_port: port@c { + reg = <0xc>; + admaif12_ep: endpoint { + remote-endpoint = <&xbar_admaif12_ep>; + }; + }; + admaif13_port: port@d { + reg = <0xd>; + admaif13_ep: endpoint { + remote-endpoint = <&xbar_admaif13_ep>; + }; + }; + admaif14_port: port@e { + reg = <0xe>; + admaif14_ep: endpoint { + remote-endpoint = <&xbar_admaif14_ep>; + }; + }; + admaif15_port: port@f { + reg = <0xf>; + admaif15_ep: endpoint { + remote-endpoint = <&xbar_admaif15_ep>; + }; + }; + admaif16_port: port@10 { + reg = <0x10>; + admaif16_ep: endpoint { + remote-endpoint = <&xbar_admaif16_ep>; + }; + }; + admaif17_port: port@11 { + reg = <0x11>; + admaif17_ep: endpoint { + remote-endpoint = <&xbar_admaif17_ep>; + }; + }; + admaif18_port: port@12 { + reg = <0x12>; + admaif18_ep: endpoint { + remote-endpoint = <&xbar_admaif18_ep>; + }; + }; + admaif19_port: port@13 { + reg = <0x13>; + admaif19_ep: endpoint { + remote-endpoint = <&xbar_admaif19_ep>; + }; + }; + }; + }; + + i2s@2901000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + i2s1_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s1_ep>; + }; + }; + i2s1_port: port@1 { + reg = <1>; + i2s1_dap_ep: endpoint { + dai-format = "i2s"; + /* Placeholder for external Codec */ + }; + }; + }; + }; + + i2s@2901100 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + i2s2_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s2_ep>; + }; + }; + i2s2_port: port@1 { + reg = <1>; + i2s2_dap_ep: endpoint { + dai-format = "i2s"; + /* Placeholder for external Codec */ + }; + }; + }; + }; + + i2s@2901200 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + i2s3_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s3_ep>; + }; + }; + i2s3_port: port@1 { + reg = <1>; + i2s3_dap_ep: endpoint { + dai-format = "i2s"; + /* Placeholder for external Codec */ + }; + }; + }; + }; + + i2s@2901300 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + i2s4_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s4_ep>; + }; + }; + i2s4_port: port@1 { + reg = <1>; + i2s4_dap_ep: endpoint { + dai-format = "i2s"; + /* Placeholder for external Codec */ + }; + }; + }; + }; + + i2s@2901400 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + i2s5_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s5_ep>; + }; + }; + i2s5_port: port@1 { + reg = <1>; + i2s5_dap_ep: endpoint { + dai-format = "i2s"; + /* Placeholder for external Codec */ + }; + }; + }; + }; + + i2s@2901500 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + i2s6_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s6_ep>; + }; + }; + i2s6_port: port@1 { + reg = <1>; + i2s6_dap_ep: endpoint { + dai-format = "i2s"; + /* Placeholder for external Codec */ + }; + }; + }; + }; + + dmic@2904000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dmic1_cif_ep: endpoint { + remote-endpoint = <&xbar_dmic1_ep>; + }; + }; + dmic1_port: port@1 { + reg = <1>; + dmic1_dap_ep: endpoint { + /* Place holder for external Codec */ + }; + }; + }; + }; + + dmic@2904100 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dmic2_cif_ep: endpoint { + remote-endpoint = <&xbar_dmic2_ep>; + }; + }; + dmic2_port: port@1 { + reg = <1>; + dmic2_dap_ep: endpoint { + /* Place holder for external Codec */ + }; + }; + }; + }; + + dmic@2904200 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dmic3_cif_ep: endpoint { + remote-endpoint = <&xbar_dmic3_ep>; + }; + }; + dmic3_port: port@1 { + reg = <1>; + dmic3_dap_ep: endpoint { + /* Place holder for external Codec */ + }; + }; + }; + }; + + dspk@2905000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dspk1_cif_ep: endpoint { + remote-endpoint = <&xbar_dspk1_ep>; + }; + }; + dspk1_port: port@1 { + reg = <1>; + dspk1_dap_ep: endpoint { + /* Place holder for external Codec */ + }; + }; + }; + }; + + dspk@2905100 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dspk2_cif_ep: endpoint { + remote-endpoint = <&xbar_dspk2_ep>; + }; + }; + dspk2_port: port@1 { + reg = <1>; + dspk2_dap_ep: endpoint { + /* Place holder for external Codec */ + }; + }; + }; + }; + }; };
i2c@3160000 { @@ -114,6 +688,29 @@ status = "okay"; };
+ sound { + compatible = "nvidia,tegra186-audio-graph-card"; + status = "okay"; + + dais = /* FE */ + <&admaif0_port>, <&admaif1_port>, <&admaif2_port>, <&admaif3_port>, + <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, <&admaif7_port>, + <&admaif8_port>, <&admaif9_port>, <&admaif10_port>, <&admaif11_port>, + <&admaif12_port>, <&admaif13_port>, <&admaif14_port>, <&admaif15_port>, + <&admaif16_port>, <&admaif17_port>, <&admaif18_port>, <&admaif19_port>, + /* Router */ + <&xbar_i2s1_port>, <&xbar_i2s2_port>, <&xbar_i2s3_port>, + <&xbar_i2s4_port>, <&xbar_i2s5_port>, <&xbar_i2s6_port>, + <&xbar_dmic1_port>, <&xbar_dmic2_port>, <&xbar_dmic3_port>, + <&xbar_dspk1_port>, <&xbar_dspk2_port>, + /* I/O */ + <&i2s1_port>, <&i2s2_port>, <&i2s3_port>, <&i2s4_port>, + <&i2s5_port>, <&i2s6_port>, <&dmic1_port>, <&dmic2_port>, + <&dmic3_port>, <&dspk1_port>, <&dspk2_port>; + + label = "jetson-tx2-ape"; + }; + padctl@3520000 { status = "okay";
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 58c5196..0ba791f 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -680,6 +680,28 @@ status = "disabled"; };
+ sound { + status = "disabled"; + + clocks = <&bpmp TEGRA186_CLK_PLLA>, + <&bpmp TEGRA186_CLK_PLL_A_OUT0>; + clock-names = "pll_a", "plla_out0"; + assigned-clocks = <&bpmp TEGRA186_CLK_PLLA>, + <&bpmp TEGRA186_CLK_PLL_A_OUT0>, + <&bpmp TEGRA186_CLK_AUD_MCLK>; + assigned-clock-parents = <0>, + <&bpmp TEGRA186_CLK_PLLA>, + <&bpmp TEGRA186_CLK_PLL_A_OUT0>; + /* + * PLLA supports dynamic ramp. Below initial rate is chosen + * for this to work and oscillate between base rates required + * for 8x and 11.025x sample rate streams. + */ + assigned-clock-rates = <258000000>; + + iommus = <&smmu TEGRA186_SID_APE>; + }; + padctl: padctl@3520000 { compatible = "nvidia,tegra186-xusb-padctl"; reg = <0x0 0x03520000 0x0 0x1000>,
Enable support for audio-graph based sound card on Jetson AGX Xavier. Following I/O interfaces are enabled. * I2S1, I2S2, I2S4 and I2S6 * DMIC3
Signed-off-by: Sameer Pujar spujar@nvidia.com --- arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts | 453 +++++++++++++++++++++ arch/arm64/boot/dts/nvidia/tegra194.dtsi | 20 + 2 files changed, 473 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts index 36f19c9..bd7ee4c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts @@ -21,6 +21,410 @@ interrupt-controller@2a40000 { status = "okay"; }; + + ahub@2900800 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + xbar_admaif0_ep: endpoint { + remote-endpoint = <&admaif0_ep>; + }; + }; + port@1 { + reg = <0x1>; + xbar_admaif1_ep: endpoint { + remote-endpoint = <&admaif1_ep>; + }; + }; + port@2 { + reg = <0x2>; + xbar_admaif2_ep: endpoint { + remote-endpoint = <&admaif2_ep>; + }; + }; + port@3 { + reg = <0x3>; + xbar_admaif3_ep: endpoint { + remote-endpoint = <&admaif3_ep>; + }; + }; + port@4 { + reg = <0x4>; + xbar_admaif4_ep: endpoint { + remote-endpoint = <&admaif4_ep>; + }; + }; + port@5 { + reg = <0x5>; + xbar_admaif5_ep: endpoint { + remote-endpoint = <&admaif5_ep>; + }; + }; + port@6 { + reg = <0x6>; + xbar_admaif6_ep: endpoint { + remote-endpoint = <&admaif6_ep>; + }; + }; + port@7 { + reg = <0x7>; + xbar_admaif7_ep: endpoint { + remote-endpoint = <&admaif7_ep>; + }; + }; + port@8 { + reg = <0x8>; + xbar_admaif8_ep: endpoint { + remote-endpoint = <&admaif8_ep>; + }; + }; + port@9 { + reg = <0x9>; + xbar_admaif9_ep: endpoint { + remote-endpoint = <&admaif9_ep>; + }; + }; + port@a { + reg = <0xa>; + xbar_admaif10_ep: endpoint { + remote-endpoint = <&admaif10_ep>; + }; + }; + port@b { + reg = <0xb>; + xbar_admaif11_ep: endpoint { + remote-endpoint = <&admaif11_ep>; + }; + }; + port@c { + reg = <0xc>; + xbar_admaif12_ep: endpoint { + remote-endpoint = <&admaif12_ep>; + }; + }; + port@d { + reg = <0xd>; + xbar_admaif13_ep: endpoint { + remote-endpoint = <&admaif13_ep>; + }; + }; + port@e { + reg = <0xe>; + xbar_admaif14_ep: endpoint { + remote-endpoint = <&admaif14_ep>; + }; + }; + port@f { + reg = <0xf>; + xbar_admaif15_ep: endpoint { + remote-endpoint = <&admaif15_ep>; + }; + }; + port@10 { + reg = <0x10>; + xbar_admaif16_ep: endpoint { + remote-endpoint = <&admaif16_ep>; + }; + }; + port@11 { + reg = <0x11>; + xbar_admaif17_ep: endpoint { + remote-endpoint = <&admaif17_ep>; + }; + }; + port@12 { + reg = <0x12>; + xbar_admaif18_ep: endpoint { + remote-endpoint = <&admaif18_ep>; + }; + }; + port@13 { + reg = <0x13>; + xbar_admaif19_ep: endpoint { + remote-endpoint = <&admaif19_ep>; + }; + }; + xbar_i2s1_port: port@14 { + reg = <0x14>; + xbar_i2s1_ep: endpoint { + remote-endpoint = <&i2s1_cif_ep>; + }; + }; + xbar_i2s2_port: port@15 { + reg = <0x15>; + xbar_i2s2_ep: endpoint { + remote-endpoint = <&i2s2_cif_ep>; + }; + }; + xbar_i2s4_port: port@17 { + reg = <0x17>; + xbar_i2s4_ep: endpoint { + remote-endpoint = <&i2s4_cif_ep>; + }; + }; + xbar_i2s6_port: port@19 { + reg = <0x19>; + xbar_i2s6_ep: endpoint { + remote-endpoint = <&i2s6_cif_ep>; + }; + }; + xbar_dmic3_port: port@1c { + reg = <0x1c>; + xbar_dmic3_ep: endpoint { + remote-endpoint = <&dmic3_cif_ep>; + }; + }; + }; + + admaif@290f000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + admaif0_port: port@0 { + reg = <0x0>; + admaif0_ep: endpoint { + remote-endpoint = <&xbar_admaif0_ep>; + }; + }; + admaif1_port: port@1 { + reg = <0x1>; + admaif1_ep: endpoint { + remote-endpoint = <&xbar_admaif1_ep>; + }; + }; + admaif2_port: port@2 { + reg = <0x2>; + admaif2_ep: endpoint { + remote-endpoint = <&xbar_admaif2_ep>; + }; + }; + admaif3_port: port@3 { + reg = <0x3>; + admaif3_ep: endpoint { + remote-endpoint = <&xbar_admaif3_ep>; + }; + }; + admaif4_port: port@4 { + reg = <0x4>; + admaif4_ep: endpoint { + remote-endpoint = <&xbar_admaif4_ep>; + }; + }; + admaif5_port: port@5 { + reg = <0x5>; + admaif5_ep: endpoint { + remote-endpoint = <&xbar_admaif5_ep>; + }; + }; + admaif6_port: port@6 { + reg = <0x6>; + admaif6_ep: endpoint { + remote-endpoint = <&xbar_admaif6_ep>; + }; + }; + admaif7_port: port@7 { + reg = <0x7>; + admaif7_ep: endpoint { + remote-endpoint = <&xbar_admaif7_ep>; + }; + }; + admaif8_port: port@8 { + reg = <0x8>; + admaif8_ep: endpoint { + remote-endpoint = <&xbar_admaif8_ep>; + }; + }; + admaif9_port: port@9 { + reg = <0x9>; + admaif9_ep: endpoint { + remote-endpoint = <&xbar_admaif9_ep>; + }; + }; + admaif10_port: port@a { + reg = <0xa>; + admaif10_ep: endpoint { + remote-endpoint = <&xbar_admaif10_ep>; + }; + }; + admaif11_port: port@b { + reg = <0xb>; + admaif11_ep: endpoint { + remote-endpoint = <&xbar_admaif11_ep>; + }; + }; + admaif12_port: port@c { + reg = <0xc>; + admaif12_ep: endpoint { + remote-endpoint = <&xbar_admaif12_ep>; + }; + }; + admaif13_port: port@d { + reg = <0xd>; + admaif13_ep: endpoint { + remote-endpoint = <&xbar_admaif13_ep>; + }; + }; + admaif14_port: port@e { + reg = <0xe>; + admaif14_ep: endpoint { + remote-endpoint = <&xbar_admaif14_ep>; + }; + }; + admaif15_port: port@f { + reg = <0xf>; + admaif15_ep: endpoint { + remote-endpoint = <&xbar_admaif15_ep>; + }; + }; + admaif16_port: port@10 { + reg = <0x10>; + admaif16_ep: endpoint { + remote-endpoint = <&xbar_admaif16_ep>; + }; + }; + admaif17_port: port@11 { + reg = <0x11>; + admaif17_ep: endpoint { + remote-endpoint = <&xbar_admaif17_ep>; + }; + }; + admaif18_port: port@12 { + reg = <0x12>; + admaif18_ep: endpoint { + remote-endpoint = <&xbar_admaif18_ep>; + }; + }; + admaif19_port: port@13 { + reg = <0x13>; + admaif19_ep: endpoint { + remote-endpoint = <&xbar_admaif19_ep>; + }; + }; + }; + }; + + i2s@2901000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + i2s1_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s1_ep>; + }; + }; + i2s1_port: port@1 { + reg = <1>; + i2s1_dap_ep: endpoint { + dai-format = "i2s"; + remote-endpoint = <&rt5658_ep>; + }; + }; + }; + }; + + i2s@2901100 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + i2s2_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s2_ep>; + }; + }; + i2s2_port: port@1 { + reg = <1>; + i2s2_dap_ep: endpoint { + dai-format = "i2s"; + /* Place holder for external Codec */ + }; + }; + }; + }; + + i2s@2901300 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + i2s4_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s4_ep>; + }; + }; + i2s4_port: port@1 { + reg = <1>; + i2s4_dap_ep: endpoint { + dai-format = "i2s"; + /* Place holder for external Codec */ + }; + }; + }; + }; + + i2s@2901500 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + i2s6_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s6_ep>; + }; + }; + i2s6_port: port@1 { + reg = <1>; + i2s6_dap_ep: endpoint@0 { + dai-format = "i2s"; + /* Place holder for external Codec */ + }; + }; + }; + }; + + dmic@2904200 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dmic3_cif_ep: endpoint { + remote-endpoint = <&xbar_dmic3_ep>; + }; + }; + dmic3_port: port@1 { + reg = <1>; + dmic3_dap_ep: endpoint { + /* Place holder for external Codec */ + }; + }; + }; + }; + }; };
i2c@3160000 { @@ -53,6 +457,14 @@ interrupts = <TEGRA194_MAIN_GPIO(S, 5) GPIO_ACTIVE_HIGH>; realtek,jd-src = <2>; sound-name-prefix = "CVB-RT"; + + port { + rt5658_ep: endpoint { + remote-endpoint = <&i2s1_dap_ep>; + mclk-fs = <256>; + clocks = <&bpmp TEGRA194_CLK_AUD_MCLK>; + }; + }; }; };
@@ -66,6 +478,47 @@ status = "okay"; };
+ sound { + compatible = "nvidia,tegra186-audio-graph-card"; + status = "okay"; + + dais = /* ADMAIF (FE) Ports */ + <&admaif0_port>, <&admaif1_port>, <&admaif2_port>, <&admaif3_port>, + <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, <&admaif7_port>, + <&admaif8_port>, <&admaif9_port>, <&admaif10_port>, <&admaif11_port>, + <&admaif12_port>, <&admaif13_port>, <&admaif14_port>, <&admaif15_port>, + <&admaif16_port>, <&admaif17_port>, <&admaif18_port>, <&admaif19_port>, + /* XBAR Ports */ + <&xbar_i2s1_port>, <&xbar_i2s2_port>, <&xbar_i2s4_port>, + <&xbar_i2s6_port>, <&xbar_dmic3_port>, + /* BE I/O Ports */ + <&i2s1_port>, <&i2s2_port>, <&i2s4_port>, <&i2s6_port>, + <&dmic3_port>; + + label = "jetson-xavier-ape"; + + widgets = + "Microphone", "CVB-RT MIC Jack", + "Microphone", "CVB-RT MIC", + "Headphone", "CVB-RT HP Jack", + "Speaker", "CVB-RT SPK"; + + routing = + /* I2S1 <-> RT5658 */ + "CVB-RT AIF1 Playback", "I2S1 DAP-Playback", + "I2S1 DAP-Capture", "CVB-RT AIF1 Capture", + /* RT5658 Codec controls */ + "CVB-RT HP Jack", "CVB-RT HPO L Playback", + "CVB-RT HP Jack", "CVB-RT HPO R Playback", + "CVB-RT IN1P", "CVB-RT MIC Jack", + "CVB-RT IN2P", "CVB-RT MIC Jack", + "CVB-RT SPK", "CVB-RT SPO Playback", + "CVB-RT DMIC L1", "CVB-RT MIC", + "CVB-RT DMIC L2", "CVB-RT MIC", + "CVB-RT DMIC R1", "CVB-RT MIC", + "CVB-RT DMIC R2", "CVB-RT MIC"; + }; + padctl@3520000 { status = "okay";
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 852980f..04b5e4a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -824,6 +824,26 @@ status = "disabled"; };
+ sound { + status = "disabled"; + + clocks = <&bpmp TEGRA194_CLK_PLLA>, + <&bpmp TEGRA194_CLK_PLLA_OUT0>; + clock-names = "pll_a", "plla_out0"; + assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>, + <&bpmp TEGRA194_CLK_PLLA_OUT0>, + <&bpmp TEGRA194_CLK_AUD_MCLK>; + assigned-clock-parents = <0>, + <&bpmp TEGRA194_CLK_PLLA>, + <&bpmp TEGRA194_CLK_PLLA_OUT0>; + /* + * PLLA supports dynamic ramp. Below initial rate is chosen + * for this to work and oscillate between base rates required + * for 8x and 11.025x sample rate streams. + */ + assigned-clock-rates = <258000000>; + }; + xusb_padctl: padctl@3520000 { compatible = "nvidia,tegra194-xusb-padctl"; reg = <0x03520000 0x1000>,
participants (3)
-
Mark Brown
-
Sameer Pujar
-
Sameer Pujar