[PATCH 0/3] ASoC: codec: tlv3204: Codec workaround
This patch series enables some features on the tlv3204 codec and also fixes some issues faced while testing
v1: initial ASoC: codec: tlv3204: Codec workaround series
Michael Sit Wei Hong (3): ASoC: codec: tlv3204: Enable 24 bit audio support ASoC: codec: tlv3204: Increased maximum supported channels ASoC: codec: tlv3204: Moving GPIO reset and add ADC reset
sound/soc/codecs/tlv320aic32x4.c | 60 +++++++++++++++++++++++--------- 1 file changed, 44 insertions(+), 16 deletions(-)
Enable 24 bit in 32 bit container audio support. Using the params_physical_width to differentiate 24 bit in 32 bit container and 24 bit in 24 bit container modes. Use the sample rate, bit depth and channel parameters to calculate the bit clock needed.
Signed-off-by: Michael Sit Wei Hong michael.wei.hong.sit@intel.com Reviewed-by: Sia Jee Heng jee.heng.sia@intel.com Reviewed-by: Pierre-Louis Bossart pierre-louis.bossart@linux.intel.com --- sound/soc/codecs/tlv320aic32x4.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/sound/soc/codecs/tlv320aic32x4.c b/sound/soc/codecs/tlv320aic32x4.c index d087f3b20b1d..8534f9006e6a 100644 --- a/sound/soc/codecs/tlv320aic32x4.c +++ b/sound/soc/codecs/tlv320aic32x4.c @@ -665,7 +665,8 @@ static int aic32x4_set_processing_blocks(struct snd_soc_component *component, }
static int aic32x4_setup_clocks(struct snd_soc_component *component, - unsigned int sample_rate) + unsigned int sample_rate, unsigned int channel, + unsigned int bit_depth) { u8 aosr; u16 dosr; @@ -753,7 +754,8 @@ static int aic32x4_setup_clocks(struct snd_soc_component *component, dosr);
clk_set_rate(clocks[5].clk, - sample_rate * 32); + sample_rate * channel * + bit_depth); return 0; } } @@ -775,9 +777,11 @@ static int aic32x4_hw_params(struct snd_pcm_substream *substream, u8 iface1_reg = 0; u8 dacsetup_reg = 0;
- aic32x4_setup_clocks(component, params_rate(params)); + aic32x4_setup_clocks(component, params_rate(params), + params_channels(params), + params_physical_width(params));
- switch (params_width(params)) { + switch (params_physical_width(params)) { case 16: iface1_reg |= (AIC32X4_WORD_LEN_16BITS << AIC32X4_IFACE1_DATALEN_SHIFT); @@ -862,7 +866,8 @@ static int aic32x4_set_bias_level(struct snd_soc_component *component,
#define AIC32X4_RATES SNDRV_PCM_RATE_8000_192000 #define AIC32X4_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \ - | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) + | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_3LE \ + | SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops aic32x4_ops = { .hw_params = aic32x4_hw_params,
Increased maximum supported channel to 8 channels for audio capture running in TDM mode.
Signed-off-by: Michael Sit Wei Hong michael.wei.hong.sit@intel.com Reviewed-by: Sia Jee Heng jee.heng.sia@intel.com Reviewed-by: Pierre-Louis Bossart pierre-louis.bossart@linux.intel.com --- sound/soc/codecs/tlv320aic32x4.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sound/soc/codecs/tlv320aic32x4.c b/sound/soc/codecs/tlv320aic32x4.c index 8534f9006e6a..5af438a00f95 100644 --- a/sound/soc/codecs/tlv320aic32x4.c +++ b/sound/soc/codecs/tlv320aic32x4.c @@ -887,7 +887,7 @@ static struct snd_soc_dai_driver aic32x4_dai = { .capture = { .stream_name = "Capture", .channels_min = 1, - .channels_max = 2, + .channels_max = 8, .rates = AIC32X4_RATES, .formats = AIC32X4_FORMATS,}, .ops = &aic32x4_ops,
Moving GPIO reset to a later stage and before clock registration to ensure that the host system and codec clocks are in sync. If the host register clock values prior to gpio reset, the last configured codec clock is registered to the host. The codec then gets gpio resetted setting the codec clocks to their default value, causing a mismatch. Host system will skip clock setting thinking the codec clocks are already at the requested rate.
ADC reset is added to ensure the next audio capture does not have undesired artifacts. It is probably related to the original code where the probe function resets the ADC prior to 1st record.
Signed-off-by: Michael Sit Wei Hong michael.wei.hong.sit@intel.com Reviewed-by: Sia Jee Heng jee.heng.sia@intel.com Reviewed-by: Pierre-Louis Bossart pierre-louis.bossart@linux.intel.com --- sound/soc/codecs/tlv320aic32x4.c | 47 ++++++++++++++++++++++++-------- 1 file changed, 35 insertions(+), 12 deletions(-)
diff --git a/sound/soc/codecs/tlv320aic32x4.c b/sound/soc/codecs/tlv320aic32x4.c index 5af438a00f95..37e14558d7c0 100644 --- a/sound/soc/codecs/tlv320aic32x4.c +++ b/sound/soc/codecs/tlv320aic32x4.c @@ -50,6 +50,28 @@ struct aic32x4_priv { struct device *dev; };
+static int aic32x4_reset_adc(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); + u32 adc_reg; + + /* + * Workaround: the datasheet does not mention a required programming + * sequence but experiments show the ADC needs to be reset after each + * capture to avoid audible artifacts. + */ + switch (event) { + case SND_SOC_DAPM_POST_PMD: + adc_reg = snd_soc_component_read32(component, AIC32X4_ADCSETUP); + snd_soc_component_write(component, AIC32X4_ADCSETUP, adc_reg | + AIC32X4_LADC_EN | AIC32X4_RADC_EN); + snd_soc_component_write(component, AIC32X4_ADCSETUP, adc_reg); + break; + } + return 0; +}; + static int mic_bias_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { @@ -434,6 +456,7 @@ static const struct snd_soc_dapm_widget aic32x4_dapm_widgets[] = { SND_SOC_DAPM_SUPPLY("Mic Bias", AIC32X4_MICBIAS, 6, 0, mic_bias_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
+ SND_SOC_DAPM_POST("ADC Reset", aic32x4_reset_adc),
SND_SOC_DAPM_OUTPUT("HPL"), SND_SOC_DAPM_OUTPUT("HPR"), @@ -665,8 +688,8 @@ static int aic32x4_set_processing_blocks(struct snd_soc_component *component, }
static int aic32x4_setup_clocks(struct snd_soc_component *component, - unsigned int sample_rate, unsigned int channel, - unsigned int bit_depth) + unsigned int sample_rate, unsigned int channel, + unsigned int bit_depth) { u8 aosr; u16 dosr; @@ -957,12 +980,6 @@ static int aic32x4_component_probe(struct snd_soc_component *component) if (ret) return ret;
- if (gpio_is_valid(aic32x4->rstn_gpio)) { - ndelay(10); - gpio_set_value(aic32x4->rstn_gpio, 1); - mdelay(1); - } - snd_soc_component_write(component, AIC32X4_RESET, 0x01);
if (aic32x4->setup) @@ -1195,10 +1212,6 @@ int aic32x4_probe(struct device *dev, struct regmap *regmap) aic32x4->mclk_name = "mclk"; }
- ret = aic32x4_register_clocks(dev, aic32x4->mclk_name); - if (ret) - return ret; - if (gpio_is_valid(aic32x4->rstn_gpio)) { ret = devm_gpio_request_one(dev, aic32x4->rstn_gpio, GPIOF_OUT_INIT_LOW, "tlv320aic32x4 rstn"); @@ -1220,6 +1233,16 @@ int aic32x4_probe(struct device *dev, struct regmap *regmap) return ret; }
+ if (gpio_is_valid(aic32x4->rstn_gpio)) { + ndelay(10); + gpio_set_value_cansleep(aic32x4->rstn_gpio, 1); + mdelay(1); + } + + ret = aic32x4_register_clocks(dev, aic32x4->mclk_name); + if (ret) + return ret; + return 0; } EXPORT_SYMBOL(aic32x4_probe);
Hello
On 7/29/20 2:32 AM, Michael Sit Wei Hong wrote:
Moving GPIO reset to a later stage and before clock registration to ensure that the host system and codec clocks are in sync. If the host register clock values prior to gpio reset, the last configured codec clock is registered to the host. The codec then gets gpio resetted setting the codec clocks to their default value, causing a mismatch. Host system will skip clock setting thinking the codec clocks are already at the requested rate.
ADC reset is added to ensure the next audio capture does not have undesired artifacts. It is probably related to the original code where the probe function resets the ADC prior to 1st record.
Signed-off-by: Michael Sit Wei Hong michael.wei.hong.sit@intel.com Reviewed-by: Sia Jee Heng jee.heng.sia@intel.com Reviewed-by: Pierre-Louis Bossart pierre-louis.bossart@linux.intel.com
sound/soc/codecs/tlv320aic32x4.c | 47 ++++++++++++++++++++++++-------- 1 file changed, 35 insertions(+), 12 deletions(-)
diff --git a/sound/soc/codecs/tlv320aic32x4.c b/sound/soc/codecs/tlv320aic32x4.c index 5af438a00f95..37e14558d7c0 100644 --- a/sound/soc/codecs/tlv320aic32x4.c +++ b/sound/soc/codecs/tlv320aic32x4.c @@ -50,6 +50,28 @@ struct aic32x4_priv { struct device *dev; };
+static int aic32x4_reset_adc(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)+{
- struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
- u32 adc_reg;
- /*
* Workaround: the datasheet does not mention a required programming* sequence but experiments show the ADC needs to be reset after each* capture to avoid audible artifacts.*/- switch (event) {
- case SND_SOC_DAPM_POST_PMD:
adc_reg = snd_soc_component_read32(component, AIC32X4_ADCSETUP);
This gives me a build error
sound/soc/codecs/tlv320aic32x4.c: In function ‘aic32x4_reset_adc’: sound/soc/codecs/tlv320aic32x4.c:66:13: error: implicit declaration of function ‘snd_soc_component_read32’; did you mean ‘snd_soc_component_read’? [-Werror=implicit-function-declaration] 66 | adc_reg = snd_soc_component_read32(component, AIC32X4_ADCSETUP); | ^~~~~~~~~~~~~~~~~~~~~~~~ | snd_soc_component_read
Also you should check the return to make sure it is valid.
Dan
Hi Dan,
The code snippet is taken from the aic32x4_component_probe function of the driver in 5.8.
Could you have a look at that portion and see if it is the same?
Thanks, Regards, Michael
-----Original Message----- From: Dan Murphy dmurphy@ti.com Sent: Wednesday, 29 July, 2020 8:31 PM To: Sit, Michael Wei Hong michael.wei.hong.sit@intel.com; alsa-devel@alsa-project.org Cc: tiwai@suse.com; broonie@kernel.org; pierre-louis.bossart@linux.intel.com; Rojewski, Cezary cezary.rojewski@intel.com; Shevchenko, Andriy andriy.shevchenko@intel.com; liam.r.girdwood@linux.intel.com; Sia, Jee Heng jee.heng.sia@intel.com; a-estrada@ti.com; zakkaye@ti.com Subject: Re: [PATCH 3/3] ASoC: codec: tlv3204: Moving GPIO reset and add ADC reset
Hello
On 7/29/20 2:32 AM, Michael Sit Wei Hong wrote:
Moving GPIO reset to a later stage and before clock registration to ensure that the host system and codec clocks are in sync. If the host register clock values prior to gpio reset, the last configured codec clock is registered to the host. The codec then gets gpio resetted setting the codec clocks to their default value, causing a mismatch. Host system will skip clock setting thinking the codec clocks are already at the requested rate.
ADC reset is added to ensure the next audio capture does not have undesired artifacts. It is probably related to the original code where the probe function resets the ADC prior to 1st record.
Signed-off-by: Michael Sit Wei Hong michael.wei.hong.sit@intel.com Reviewed-by: Sia Jee Heng jee.heng.sia@intel.com Reviewed-by: Pierre-Louis Bossart
pierre-louis.bossart@linux.intel.com
sound/soc/codecs/tlv320aic32x4.c | 47 ++++++++++++++++++++++++-------- 1 file changed, 35 insertions(+), 12 deletions(-)
diff --git a/sound/soc/codecs/tlv320aic32x4.c b/sound/soc/codecs/tlv320aic32x4.c index 5af438a00f95..37e14558d7c0 100644 --- a/sound/soc/codecs/tlv320aic32x4.c +++ b/sound/soc/codecs/tlv320aic32x4.c @@ -50,6 +50,28 @@ struct aic32x4_priv { struct device *dev; };
+static int aic32x4_reset_adc(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event) {- struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
- u32 adc_reg;
- /*
* Workaround: the datasheet does not mention a required programming* sequence but experiments show the ADC needs to be reset after each* capture to avoid audible artifacts.*/- switch (event) {
- case SND_SOC_DAPM_POST_PMD:
adc_reg = snd_soc_component_read32(component, AIC32X4_ADCSETUP);
This gives me a build error
sound/soc/codecs/tlv320aic32x4.c: In function ‘aic32x4_reset_adc’: sound/soc/codecs/tlv320aic32x4.c:66:13: error: implicit declaration of function ‘snd_soc_component_read32’; did you mean ‘snd_soc_component_read’? [-Werror=implicit-function-declaration] 66 | adc_reg = snd_soc_component_read32(component, AIC32X4_ADCSETUP); | ^~~~~~~~~~~~~~~~~~~~~~~~ | snd_soc_component_read
Also you should check the return to make sure it is valid.
Dan
On Thu, Jul 30, 2020 at 05:46:20AM +0000, Sit, Michael Wei Hong wrote:
Hi Dan,
The code snippet is taken from the aic32x4_component_probe function of the driver in 5.8.
Could you have a look at that portion and see if it is the same?
You need to submit code against the current development branch unless it's a bug fix for the current release branch, sometimes interfaces change in the development version (as is the case here).
Please don't top post, reply in line with needed context. This allows readers to readily follow the flow of conversation and understand what you are talking about and also helps ensure that everything in the discussion is being addressed.
Please fix your mail client to word wrap within paragraphs at something substantially less than 80 columns. Doing this makes your messages much easier to read and reply to.
-----Original Message----- From: Mark Brown broonie@kernel.org Sent: Thursday, 30 July, 2020 8:34 PM To: Sit, Michael Wei Hong michael.wei.hong.sit@intel.com Cc: Dan Murphy dmurphy@ti.com; alsa-devel@alsa-project.org; tiwai@suse.com; pierre-louis.bossart@linux.intel.com; Rojewski, Cezary cezary.rojewski@intel.com; Shevchenko, Andriy andriy.shevchenko@intel.com; liam.r.girdwood@linux.intel.com; Sia, Jee Heng jee.heng.sia@intel.com; a-estrada@ti.com; zakkaye@ti.com Subject: Re: [PATCH 3/3] ASoC: codec: tlv3204: Moving GPIO reset and add ADC reset
On Thu, Jul 30, 2020 at 05:46:20AM +0000, Sit, Michael Wei Hong wrote:
Hi Dan,
The code snippet is taken from the aic32x4_component_probe function
of the driver in 5.8.
Could you have a look at that portion and see if it is the same?
You need to submit code against the current development branch unless it's a bug fix for the current release branch, sometimes interfaces change in the development version (as is the case here).
Please don't top post, reply in line with needed context. This allows readers to readily follow the flow of conversation and understand what you are talking about and also helps ensure that everything in the discussion is being addressed.
Please fix your mail client to word wrap within paragraphs at something substantially less than 80 columns. Doing this makes your messages much easier to read and reply to.
-----Original Message----- From: Alsa-devel alsa-devel-bounces@alsa-project.org On Behalf Of Sit, Michael Wei Hong Sent: Thursday, 30 July, 2020 1:46 PM To: Dan Murphy dmurphy@ti.com; alsa-devel@alsa-project.org Cc: Rojewski, Cezary cezary.rojewski@intel.com; a-estrada@ti.com; Shevchenko, Andriy andriy.shevchenko@intel.com; tiwai@suse.com; Sia, Jee Heng jee.heng.sia@intel.com; pierre- louis.bossart@linux.intel.com; liam.r.girdwood@linux.intel.com; broonie@kernel.org; zakkaye@ti.com Subject: RE: [PATCH 3/3] ASoC: codec: tlv3204: Moving GPIO reset and add ADC reset
Hi Dan,
The code snippet is taken from the aic32x4_component_probe function of the driver in 5.8.
Could you have a look at that portion and see if it is the same?
Thanks, Regards, Michael
-----Original Message----- From: Dan Murphy dmurphy@ti.com Sent: Wednesday, 29 July, 2020 8:31 PM To: Sit, Michael Wei Hong michael.wei.hong.sit@intel.com; alsa- devel@alsa-project.org Cc: tiwai@suse.com; broonie@kernel.org; pierre- louis.bossart@linux.intel.com; Rojewski, Cezary cezary.rojewski@intel.com; Shevchenko, Andriy andriy.shevchenko@intel.com; liam.r.girdwood@linux.intel.com; Sia, Jee Heng jee.heng.sia@intel.com; a-estrada@ti.com; zakkaye@ti.com Subject: Re: [PATCH 3/3] ASoC: codec: tlv3204: Moving GPIO reset and add ADC reset
Hello
On 7/29/20 2:32 AM, Michael Sit Wei Hong wrote:
Moving GPIO reset to a later stage and before clock registration to ensure that the host system and codec clocks are in sync. If the host register clock values prior to gpio reset, the last configured codec clock is registered to the host. The codec then gets gpio resetted setting the codec clocks to their default value, causing a mismatch. Host system will skip clock setting thinking the codec clocks are already at the requested rate.
ADC reset is added to ensure the next audio capture does not have undesired artifacts. It is probably related to the original code where the probe function resets the ADC prior to 1st record.
Signed-off-by: Michael Sit Wei Hong michael.wei.hong.sit@intel.com Reviewed-by: Sia Jee Heng jee.heng.sia@intel.com Reviewed-by: Pierre-Louis Bossart
pierre-louis.bossart@linux.intel.com
sound/soc/codecs/tlv320aic32x4.c | 47 ++++++++++++++++++++++++-
1 file changed, 35 insertions(+), 12 deletions(-)
diff --git a/sound/soc/codecs/tlv320aic32x4.c b/sound/soc/codecs/tlv320aic32x4.c index 5af438a00f95..37e14558d7c0 100644 --- a/sound/soc/codecs/tlv320aic32x4.c +++ b/sound/soc/codecs/tlv320aic32x4.c @@ -50,6 +50,28 @@ struct aic32x4_priv { struct device *dev; };
+static int aic32x4_reset_adc(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event) {- struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
- u32 adc_reg;
- /*
* Workaround: the datasheet does not mention a requiredprogramming
* sequence but experiments show the ADC needs to be resetafter each
* capture to avoid audible artifacts.*/- switch (event) {
- case SND_SOC_DAPM_POST_PMD:
adc_reg = snd_soc_component_read32(component,AIC32X4_ADCSETUP);
This gives me a build error
sound/soc/codecs/tlv320aic32x4.c: In function 'aic32x4_reset_adc': sound/soc/codecs/tlv320aic32x4.c:66:13: error: implicit declaration of function 'snd_soc_component_read32'; did you mean 'snd_soc_component_read'? [-Werror=implicit-function-declaration] 66 | adc_reg = snd_soc_component_read32(component, AIC32X4_ADCSETUP); | ^~~~~~~~~~~~~~~~~~~~~~~~ | snd_soc_component_read
Also you should check the return to make sure it is valid.
Dan
Hi Dan,
This code patch is created based on the kernel version 5.8-rc4. The register reading and writing are copied from the function aic32x4_component_probe. May I know the version of the kernel you are applying the patch on?
Thanks, Regards, Michael
On Mon, Aug 03, 2020 at 04:54:06AM +0300, Sit, Michael Wei Hong wrote:
From: Mark Brown broonie@kernel.org Sent: Thursday, 30 July, 2020 8:34 PM On Thu, Jul 30, 2020 at 05:46:20AM +0000, Sit, Michael Wei Hong wrote: From: Alsa-devel alsa-devel-bounces@alsa-project.org On Behalf Of Sit, Michael Wei Hong Sent: Thursday, 30 July, 2020 1:46 PM From: Dan Murphy dmurphy@ti.com Sent: Wednesday, 29 July, 2020 8:31 PM On 7/29/20 2:32 AM, Michael Sit Wei Hong wrote:
This code patch is created based on the kernel version 5.8-rc4. The register reading and writing are copied from the function aic32x4_component_probe.
Side note. When formatting the patch series, add --base to the `git format-patch`, so it will add it to cover letter.
On Mon, Aug 03, 2020 at 01:54:06AM +0000, Sit, Michael Wei Hong wrote:
This code patch is created based on the kernel version 5.8-rc4. The register reading and writing are copied from the function aic32x4_component_probe. May I know the version of the kernel you are applying the patch on?
The trees for each subsystem are listed in MAINTAINERS, or you can look and see the trees that linux-next is pulling from. In the case of ASoC
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next
Please delete unneeded context from mails when replying. Doing this makes it much easier to find your reply in the message, helping ensure it won't be missed by people scrolling through the irrelevant quoted material.
-----Original Message----- From: Sit, Michael Wei Hong Sent: Monday, 3 August, 2020 9:54 AM To: Dan Murphy dmurphy@ti.com Cc: Mark Brown broonie@kernel.org; alsa-devel@alsa- project.org; tiwai@suse.com; pierre-louis.bossart@linux.intel.com; Rojewski, Cezary cezary.rojewski@intel.com; Shevchenko, Andriy andriy.shevchenko@intel.com; liam.r.girdwood@linux.intel.com; Sia, Jee Heng jee.heng.sia@intel.com; a-estrada@ti.com; zakkaye@ti.com Subject: RE: [PATCH 3/3] ASoC: codec: tlv3204: Moving GPIO reset and add ADC reset
On 7/29/20 2:32 AM, Michael Sit Wei Hong wrote:
Moving GPIO reset to a later stage and before clock registration
to
ensure that the host system and codec clocks are in sync. If the host register clock values prior to gpio reset, the last configured codec clock is registered to the host. The codec then gets gpio resetted setting the codec clocks to their default value, causing a
mismatch.
Host system will skip clock setting thinking the codec clocks are already at the requested rate.
ADC reset is added to ensure the next audio capture does not
have
undesired artifacts. It is probably related to the original code where the probe function resets the ADC prior to 1st record.
Signed-off-by: Michael Sit Wei Hong
michael.wei.hong.sit@intel.com
Reviewed-by: Sia Jee Heng jee.heng.sia@intel.com Reviewed-by: Pierre-Louis Bossart
pierre-louis.bossart@linux.intel.com
sound/soc/codecs/tlv320aic32x4.c | 47
++++++++++++++++++++++++-
1 file changed, 35 insertions(+), 12 deletions(-)
diff --git a/sound/soc/codecs/tlv320aic32x4.c b/sound/soc/codecs/tlv320aic32x4.c index 5af438a00f95..37e14558d7c0 100644 --- a/sound/soc/codecs/tlv320aic32x4.c +++ b/sound/soc/codecs/tlv320aic32x4.c @@ -50,6 +50,28 @@ struct aic32x4_priv { struct device *dev; };
+static int aic32x4_reset_adc(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event){
- struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
- u32 adc_reg;
- /*
* Workaround: the datasheet does not mention a requiredprogramming
* sequence but experiments show the ADC needs to bereset
after each
* capture to avoid audible artifacts.*/- switch (event) {
- case SND_SOC_DAPM_POST_PMD:
adc_reg = snd_soc_component_read32(component,AIC32X4_ADCSETUP);
This gives me a build error
sound/soc/codecs/tlv320aic32x4.c: In function
'aic32x4_reset_adc':
sound/soc/codecs/tlv320aic32x4.c:66:13: error: implicit
declaration of
function 'snd_soc_component_read32'; did you mean 'snd_soc_component_read'? [-Werror=implicit-function-
declaration]
66 | adc_reg = snd_soc_component_read32(component,AIC32X4_ADCSETUP); | ^~~~~~~~~~~~~~~~~~~~~~~~ | snd_soc_component_read
Also you should check the return to make sure it is valid.
Dan
Hi Dan,
This code patch is created based on the kernel version 5.8-rc4. The register reading and writing are copied from the function aic32x4_component_probe. May I know the version of the kernel you are applying the patch on?
Thanks, Regards, Michael
I have tried to build the kernel with the patches applied on https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next branch and also on the linux-next branch from https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git Both of them are not throwing errors when I enable the config to build the codec driver.
Can you double confirm the branch you are building the kernel from?
participants (5)
-
Dan Murphy -
Mark Brown -
Michael Sit Wei Hong -
Shevchenko, Andriy -
Sit, Michael Wei Hong